TW320794B - Signal processing method and device of interpolation digital filter - Google Patents

Abstract

A digital filter, a L phase interpolation, generates the input sampling x([(t-l)/L]-i) according to the n coefficients of tap Pl(i) of L banks in which 1<=l<=L, 0<=i<=n-1. It includes 1. the first circuit to generate bankfilter terms at each time t which includes at least one combination of the two cross symmetric terms Under in-phase condition, Pk(i)x([(t-k)/L]-i)+PL-k+1(i).x([(t-(L-k+1))/L]-i) and Pk(n-1-i)x([(t-k)/L]-(n-1-i))+PL-k+1(n-1-i).x([(t-(L-k+1))/L]-(n-1-i)) Under non in-phase condition, Pk(i)x([(t-k)/L]-i)+PL-k+1(i-1)x([(t-(L-k+1))/L]-(i-1)) and Pk(n-i)x([(t-k)/L]-(n-i))+PL-k+1(n-1-i)x([(t-(L-k+1))/L]-(n-1-i)) 2. the second circuit to sum the above bankfilter terms at each time t for generating the output of the variation from time t-1 to t.

Description

320794 A? B7 V. Description of the invention (I) Field of the invention This invention relates to the use of a finite impulse response (FIR) filter to process digital signals. Background of the invention A finite impulse response filter is a digital filter composed of several tap coefficients or weights. An input signal x (t) in the sample is shifted into a finite impulse response filter, one sample per cycle. At each cycle t, the finite impulse response filter (the FIR filter, hereinafter referred to as FIR filter) calculates a sum (sum) y (t): n-1 Y (t) = Σ p (i) x (ti ) (1) (Please read the precautions on the back first and then fill in this page) --- ^ ---- τ --.--- f —install -------- order ----- In the th (1) printing form of the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, x (ti) is the ti sample of x (ti sample of x), and p (i) is the i-th branch of a FIR filter Contact coefficient, where σ S (n-1), and n is the total number of contact coefficients in the FIR filter. FIR filters are very useful in several applications. For example, interpolation. The first picture shows a multi-phase multiplier 100. It was published by J. Candy and G. Temes in IEEE Volume 69, Issue 3, March I988, pages 417 to 448 of "oversampling." The data paper format is applicable to China National Standard (CNS) A4 (210X297mm) 83. 3. 〇〇〇〇〇〇〇 32〇794 A7 B7 V. Description of the invention (2) Converter: theory, design and simulation , Oversampling Delta-Sigma Data Converters: Theory, Design and Simulation '. 〇 This frequency multiplier 100 is actually composed of L bank FIR filters 110-1, 110-2,..., 110-L And the input signal t of this multiplier

X

C) is processed by an L-fold frequency-increasing signal, (where

L represents the nearest integer less than or equal to C). In the second figure, (a) to (e) illustrate the sampling value X (t t

The shifting situation of L, where the sampling value X () is oversampled by L times

L Central Bureau of Standards ® Ministry of Economic Affairs ® C Industrial and Consumer Cooperatives Print sample / hold data. Suppose L = 5 and n = 3. Define a value V = t modulus (mod) L. When time t = 0, v = 0, the sampling value is shown in the second (a) graph. As shown in the figure, the value of each filter bank from 110-1 to 110-5 is the same. At this time, we can say that the filter rows 110-1 to 110-5 are in the same phase. When time t = l, (v = l) as shown in the second (b) graph, the sampling value χ (2) will be shifted into the filter bank 110-1. Therefore, filter I ---- 7-:-1 I installed ----- ^-I set ----- ί line (please read the precautions on the back first and then fill out this page) Using the Chinese National Standard (CNS) Α4 specification (210Χ297 mm) 83. 3.10,000 A7 B7 5. Description of the invention (3) The rows 110-1 and 110-2 to 110-5 are out of phase ). Similarly, the second (c) graph shows the situation where x (2) is shifted into the filter bank 110-2 at time t = 2 and v = 2. The second (d) diagram is the case where x (2) is shifted into the filter bank 110-3 at time t = 3 versus v = 3. The second (e) graph is the case where x (2) is shifted into the filter bank 110-4 at time t = 4 and v = 4. Finally, the second (f) graph shows the situation where χ (2) is shifted into the filter 110-5 at time t = 5 and v = 0. In Figure 2 (f). . The wave filter rows 110-1 to 110-5 will again be in the same phase. The output values of each FIR filter bank 110-1, 110-2, ..., 110-L are fed to a corresponding upsampling circuit 120-1, 120-2,..., 120-L, this circuit is to increase the output signal by sampling L times. See D. ELLIOT, Handbook of Digital Signal Processing Application Engineering (HANDBOOK OF DIGITAL SIGNAL PROCESSING.ENGINEERING APPICATIONS) page 239 (1987). These signals with increased sampling and filtering are yi (t), y2 (t), ..., YL (t) will be added together to generate the frequency-increasing signal g (t) of the input signal at time t. Here, each up-sampling filter signal, for example, yL (t), is the delay corresponding to the previous up-sampling filter signal, for example, yl-jl (t), the output value of a cycle unit z-1. Among them, the frequency-increasing signal g (t) can be expressed by formula (2): ί -------- ^ ------ lτ ------ a piece of paper (please read the precautions on the back first (Fill in this page) LL n-1 g (t) = Eye (*-i + 〇 = Σ Σ P (i) 4 = 1 1 = 1 i = o Λ t-printed by the Central Bureau of Standards of the Ministry of Economic Affairs and Industry and Consumer Cooperatives 1

L -i) (2) However, the problem is that the frequency multiplier 100 requires many FIR filters, so it will occupy valuable space in an integrated circuit chip. The third picture shows another 83.3. 10,000 The paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297 mm) 320794 A7 B7 5. Description of the invention (bucket) A multi-phase frequency multiplier traditionally used in audio 2 〇〇. In this frequency multiplier 200, it is assumed that: t 'x (.i) -0

L versus S is related to P, where if (t modulus L) is off 0, s = t modulus L and if t modulus L = 0, S = L. If the input signal X is sampled data, the above assumption is true. Therefore, equation (2) can be reduced to: g (t) = ys (t) n-1. = 0 (i) · x ((please read the precautions on the back before filling this page) ts • i ) (4) Printed in the third figure by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy, the filter 200 is accompanied by a random access memory (RAM) 210, in order to store n input sample values, for example, χ ( ○), x (l), ..., x (nl). Each sample is assumed to be b bits. Therefore, this RAM 210 is an nX b-bit RAM. A (LX η) X d bit read-only memory (ROM) 220 is used to store each possible d bit tap point coefficient Ps (i) (where, 11SSL and 〇SiSn-1). To calculate the g (t) value at a specific time t, a controller (not listed) continuously outputs η appropriate sampling values x (t-s

L i) and n corresponding tap coefficients PS (i) to the multiplier 230. This multiplier 23〇 multiplies each sampling value with its corresponding tap point coefficient and outputs the paper size applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 83. 3.10,000 prostitute 〇7q 4 A7 B7 5. Description of invention (5 &quot;) Each product goes to a totalizer 24. This accumulator 240 accumulates n such products to produce each g (t). The frequency multiplier 200 therefore uses n multiplications and n accumulations to generate g (t). If the input signal x is sample &quot; sample / hold data, then equation (2) can be simplified as follows: tk n-2 tg (t) = χ (---) · Σ P {(〇) + Σ X (— LL ″ Si = 1 i = 0 LL-t L Pi (i + 1)] + x (-η) · Σ Pi (L k • i -1) · [Σ Pi (i) + Σ p = K + 1 q = 1 L = k + i (5) _HJ «^^^ 1 ^ i_l tm I ^^^ 1 ^^ 1 (please read the precautions on the back before filling this page)

L where, HK5_L, and Σ Pjj (i) = 〇, if K = L. The conventional frequency multiplier J? = Κ + 1 can be modified to implement such a sample / hold frequency multiplier. In particular, a (n + 1) Xb bit RAM 210 is used to store n + 1 input sample values x (t), x (t —L ″ L L ″ 1)

1T Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs t x (

L

-n). Similarly, a (LX (n + 1)) Xd bit ROM 220 is also used to store the sum of LX (n + 1) different tap coefficients. In this equation (5), three tap points Coefficients and calculation equations are applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297 mm) for this paper scale 83. 3.10,000 V. Description of the invention (6) A7 B7 (5a), (Sb), and (sc), The required storage memory sizes are L, (n-1) XL and L, respectively. _ k Σ Ρ $ (Ο) (5a) L k Σ Pi (i) + Σ) = K + 1 A =

Pi (i + 1) (5b) L Σ Pj? (N-1) »= k + l (5c) Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs in order to §1 * count every time t The g (t) value, (not shown) continuously outputs n + 1 sampling values from the RAM 10 and n + 1 corresponding tap coefficient sums from the ROM 22〇 to the multiplier 23〇. According to equation (5), in order to generate g (t), the accumulator 24〇 accumulates the product of n + 1 multipliers 23〇. In this case, the frequency multiplier 200 must perform n + 1 times of multiplication and n + 1 times of accumulation. The fourth diagram is another conventional frequency multiplier 300 for upsampling audio sampling data. As before, the frequency multiplier 300 has an nXb bit RAM 310 and a (LX η) X b bit ROM 3 2.0. Unlike the foregoing, each tap coefficient Rjj (i) stored in the ROM 32 is selected as a secondary screen with only two or three non-zero bits (a power of two). In actual implementation, η sampling values are connected to a controller 83.3 · 10,000 I --- · ------ ^ —installed ----- 1--order ----- ^ line (please first Read the precautions on the back and fill in this page) A7 B7 5. Description of the invention (7) It is continuously output from RAM 31〇 to a shift register (shift register) 330. The corresponding n tap coefficients are The ground is connected to a control circuit 340. According to Booth's algorithm (Algorithm), this control circuit multiplies each tap point coefficient with its corresponding sampling value. That is, for each non-zero bit q, of which is 5_qSd-1, the sampling value is shifted to the left by q bits, and each shifted output result is accumulated using an accumulator 35. This accumulator 35〇 accumulates η multiplying rice at a specific time t to produce g (t). The fifth diagram shows another conventional frequency multiplier 400 that was disclosed in US Patent No. 4,862,402. This upconverter 400 ----.—---- ί -installed — (please read the $ item on the back and then fill in this page) is the sampling data of up-converted video (Video). This sampled data X -i) can be written as a binary representation as follows: X (t-s -i) b-l = Σ Χχη (t-s L L ″ m = 0 L L ″ • i) · 2 m t-s

L (6)

iT The Ministry of Economic Affairs Central Standards Bureau Staff Consumer Cooperative printed it, where Xm is a vector representing the input sampling value as a bit, 0 'or, i, combining equations (4) and (6), g ( t) can be written] as follows: bl g (t) = Σ m = 0 nl Σ ps i = 〇 (i) * Xm (ts i)

L 83. 3.10,000 This paper scale is applicable to the Chinese National Standard (CNS) A4 (210X297 mm). V. Description of the invention (8) A7 B7 Equation (7) is used to perform the use of Booth algorithm to calculate each sample The product of tap coefficients corresponding to him is very useful. (This algorithm is based on the qth bit of the tap coefficient to determine the displacement of each sampled signal, and then accumulates the shifted sampled signal. However, the frequency booster 400 uses a modified Booth algorithm. In this modified In the Booth algorithm, the adjacent qi, q2 bit pairs within the tap coefficients, 〇Sqi are also used to control the accumulation of the sampling signal shifted to the left by qx and q2 = qi + 1 bit. The input signal The addition operation from m = 0 to b-1 required by X is separated according to adjacent two-bit planes and combined into parallel even or odd addition operations. At this time, equation (7) can be rewritten as follows: b 2 2 · r + 1 n-1 g (t) = Σ [Σ [Σ Ps (i) · xm r = 0 τφ2 · ri = 0 ts i) · 2m)] (8)

L In the frequency multiplier 400, a module 410 is provided for pre-preprocessing tap coefficient ps (i) and outputs the processed result to modules 420-0, 420-1 , ..., 420-R, where b | ^ γ I bind X-rays (please read the precautions on the back before filling in this page) R: • 1 ° each tap point coefficient PS (i) via line 411 is The Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs printed and loaded into the module 410 continuously. The n tap coefficients Ps (i) are shifted into column 412 of the first shift register. Further, the multiplier 414 and the adder 416 calculate 3 · ps (i) for each coefficient, and connect the n 3. Ps (i) values into place. The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) 83. 3.10,000 A7 B7 V. Description of invention (?) Once column 418 of the shift register is fully loaded, the module 410 will output each slave in parallel according to the specific S value i = 〇 to nl pair coefficient Ps (i), 3 · Ps (i). Furthermore, according to each S value, the 412 and 418 columns of the shift register are used to provide L · n registers (for example, 412-0-1, 412-0-L) In order to store the coefficients ps (i), 3 · PS (i) separately. In addition, multiplexers (for example, 413-1, and 415-1) output appropriate coefficient pairs, and this coefficient pair (depending on the input sampling value t-s X (• i)).

L Each module 420-0, 420-1, ..., 420-R will receive a corresponding adjacent bit pair of t-s input sampling value X (-i)

L The Ministry of Economic Affairs Central Standards Bureau Beigong Consumer Cooperative printed X2 r, r + 1 (module 420-0 received bits X0, X1, and module 420-1 received bits X2, X3, etc.). In each module, for example, module 420-0, its input bit pair X0, Xi will be decoded in a decoder 421. These decoded bits are then input as n control multiplexers 422-0, 422-1, ..., 422- (11-1) like a control signal (selector control_signals). For the 1_th multiplexer (of which 〇SiSn-l) 422_i, a corresponding coefficient pair Ps (i), 3 · PS (i) is received, and 0, Ps (i), 2 · Ps ( i) 3 * PS (i) one of the values (depending on the decoded sampling bits) in order to produce a partial product: 2 · r + i Σ P s (i) Χχη (χη = 2 · r ts -i ) I --.-- ^-1 -installed -----. 丨 order ----- ί line (please read the precautions on the back before filling this page)

L This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) 83. 3.10,000 V. Description of invention (| 〇) A7 B7 The Ministry of Economic Affairs Central Bureau of Accreditation and Employee Cooperative Printing of the η partial products The multiplexer from 422_0 to 422- (nl) is output to a summation stage, 424, for summing the partial products to produce the following sum: ni 2 · r + i ts fr = Σ [Σ Ps (i) · Xm (i = 0 m = 2 · r Sum of each output from the multiplier module 420-0, 420-1,..., 42 0-R (t), fi (t), ..., fR (t) will be added by a plurality of adders to produce g (t). The plurality of adders are connected by a binary adder tree 430. The frequency-increasing technique has weaknesses. The reason why the frequency-multiplier 200 has weaknesses is that in order to obtain g (t), it takes a lot of time to perform the multiplication and addition actions, but the addition consumes less. Time. The reason why the frequency multiplier 3000 has a weakness is because each tap point coefficient must be a power of two. This will jeopardize the performance of the frequency multiplier 300. In particular, it will When the frequency multiplier 300 is used in a certain application field, it will be very difficult to meet the frequency response of certain specific needs. The speed of the frequency multiplier 400 is very fast, but it occupies too much surface space on the 1C chip. This is why The purpose of the invention is to provide a multi-phase finite impulse response filter to overcome the weaknesses of the aforementioned techniques. The summary of the present invention illustrates that the present invention will achieve these and other objectives as follows. The cross-symmetric bank filter terms are synthesized to form a merged filter term. Suppose there are L filter rows, numbered 1, · · · · · · · · · l, and in each

----; ---:-1 —installed-- (please read the precautions on the back and then fill in this page) The standard size of the used paper is Chinese National Standard (CNS) A4 specification (21〇Χ25> 7 Mm) 83.3.10,000 ^ 80794 A7 B7 5. Description of the invention (11)-There are several tap coefficients numbered 〇,..., I, in a filter bank. Therefore, it is said that the ith filter term of the ith row filter and the (η-i-1) row filter term in the (Li +1) filter row are cross-symmetric. At least two cross-symmetric filter items will be combined. The filter row items are as follows: In the case of the same phase: t-k

Pk (i) * X (-i), and

L

L t-k • (n-l-i)) + PL-κ + i (n-l-i) · X (t- (L-k + l) — (n—1—i)) L ″

L in the case of non-in-phase: except the product term Pl-κ (i) · χ (t_ (L-K + l) -i) and

L --- Γ .--.--- If -installed ------- order ----- ί ball (please read the precautions on the back before filling this page) tk Ρκ (nli) · X ((nli)), the parameter i will be replaced by the L · 1 printed by the Ponggong Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs, and the rest will be the same as in the same phase. At each time t, a sample value X (the size of the paper is easily calibrated in China (CNS> Α4 specification (210X297mm) t-k

L • i) will be bit 83. 3. 〇〇〇〇〇 5, invention description (丨 2) A7 B7 moved into one of the filter row, so changed the row of the wave reducer item in other filters The sampling value of the row has not changed. Define t = wL + K, where 1SKSL and where W is any non-negative whole 0,1,2, ...

L when + 1 SKSL, one sample X (t-k • i) is shifted into

L The Kth filter row, so that it is in the same phase as the (L-K + 1) th filter row that contains the cross-symmetric row filter term. on the other hand,

L when-, a sample X 2 t-k -i) is shifted into the first

L K filter rows so that it is not in the same phase as the (L-K + 1) th filter row including cross-symmetric row filter items.

L ---- J .-- ^-1 -installed ------ order ----- ί line (please read the precautions on the back before filling out this page) By combining cross-symmetric filter New filter items are printed by the Ministry of Economic Affairs, Central Bureau of Industry and Commerce, Beigong Consumer Cooperative. Η device rows will be formed, and this new filter row has U = device items, where e row filters represent the upper limit of e (the ceiling of The paper scale adopts the Chinese National Standard (CNS) Α4 specification (210Χ297mm) 83. 3.10,000 5. Description of the invention (丨 3) A7 B7 e) or the largest integer not less than e + l. Each time-seven and t-Ι, the &quot; merged &quot; (&quot; merged &quot;) filter row that is changed between the increased frequency output values g (t) and g (ti) is defined Is the following characteristic equation (assuming that η and L are even numbers): tk ni YJ (t) = Σ Pk (i) * X (i = 0 where

L -i) + Σ PL-κ + i (i) · X (t- (L-K + l) -i)

L --- Γ --.--- f installed-- (please read the notes on the back before filling in this page) and j = kif

L j = L-K + l if

1 &lt; K &lt; L (9)

L In the case of + 1SKSL, equation (9) can be reduced as follows: Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Υ-ι yj (t) = Σ (Pk (i) + pL-κ i = 0 ( i)) · (X (tk tk -i) + X (

L

L This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) 83.3.10,000 V. Description of the invention (丨 +)

L

In the case of 15_KS A7 B7, in order to make most of the cross-symmetric filter entries in the same phase, non-in-phase filter rows with cross-symmetric filter entries must be able to be displaced. Therefore, equation (9) can be reduced as follows: yj (t) = Ρκ (〇) · [X (tk) + Χ (t + k-1 LL "LL" -η))] U-2 Σ (Pk ( i) + PL-Κ + 1 (il)) * (Χ (tk tk i) + X (

L

t-k • L • (n-i))] 2 · Pk (U-l) · X ((11)

In short, an improved FIR filter multiplier has a combined filter bank formed by combining cross-symmetric filter banks. This combined filter bank can greatly reduce the processing time and required circuit size. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs-^^ 1 * 'n .13 ^^ 1 ^ II-I ......-^ 1 ------- -I- i-4 · Ball-II -.......---J. II I .....- 11- I (please read the $ item on the back and then fill in this page) CNS) A4 specification (210X297mm) 83. 3.10,000 shirts 0794 V. Description of invention (丨 5) Brief description of the printed patterns of the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The first figure is the first traditional FiR filter The second (a) -two (f) diagram of the multiplier describes the case where the sample / hold data is shifted into the FIR filter multiplier in the first diagram. The third diagram is the second traditional FIR filter frequency multiplier. The fourth diagram is the third traditional FIR filter frequency multiplier. The fifth diagram is the fourth traditional FIR filter frequency multiplier. The sixth (a) -six (b) diagram is a combination of cross-symmetric filter line items according to the present invention. The seventh figure is a FIR filter multiplier according to the first embodiment of the present invention. Figure 8 shows the function of a frequency multiplier, and selects the tap coefficient from it. (A)-(z), (aa), (bb), (cc) and (dd) of the ninth figure describe the state of the counter in the FIR filter upconverter in the seventh figure. The tenth figure is a FIR filter frequency multiplier according to the second embodiment of the present invention. The eleventh figure is a module core of the FIR filter of the tenth figure. Detailed description of the present invention The sixth (a) -six (b) is the combination of the cross-symmetric row filter items according to the present invention. The sixth (a) graph is an example of l = 5 filter rows 510, 520, 530, 540, and 550 with respect to the phases 12, 3, 4, and 5, and each filter row has a π = 5 tap coefficient. The filter banks 510, 5 2 0, 5 3 0, 540 and 550 have corresponding characteristic equations yi (t), y2 (t), Y3 (t), y4 (t) and y5 (t), when these When the equations are added together, I ---------- f -install ------ I order ----- ^ 4 (please read the note # ^ on the back before filling this page ) This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) 83. 3.10,000 A7 ______B7 V. Description of invention (丨 6)

Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs can produce the frequency increaser output value g (t). At time t, a sampling input value χ (2) is input to the tap array element 541 of the filter 54. At this time, k = 4 and t = wL + K = wL + 4 (where w is any non-negative integer 〇, 1, 2, ..., and 1SK $ _L, for example, t = 4,9, I4, etc.). (At time t-Ι, the sampling value X (1) originally at the tap array element 54; l is shifted to the tap array element 542, and at the time t-Ι, originally at the tap array element 542 The sampling value χ (〇) is shifted to tap point array element 543, etc.). The filter bank 510 and the filter bank 550 are not in the same phase. However, the filter bank 520 and the filter bank 540 are in the same phase. The sixth (b) figure is the cross symmetry of the filter line item. Generally speaking, the row filter term of the ith tap coefficient of the Kth filter row is the (η-i -1) th branch of the (L.-K + 1) thirteenth waver row The row filter terms of the contact coefficient are cross-symmetric. The row filter terms of the row filters 520 and 540 are cross-symmetric as follows: the row filter terms P2 (O) X (2) and P4 (4) X (-2) are cross-symmetric. The term P2 (1) · X (l) and the term P4 (3). X (-l) are cross-symmetric. The term P2 (2). X (0) and the term P4 (2) ♦ X (0) are cross-symmetric. Item P2 (3). X (-l) and the term P4 (1) · X (l) are cross-symmetric. The term P2 (4) · X (-2) is cross-symmetric with the term P4 (0) · Χ (2). The row filter terms of the filter bank 530 are cross-symmetrical to each other, and the term P3 (〇) · Χ (2) and the term P3 (4) · Χ (-2) are cross-symmetrical, the term P3 (1) ♦ X ( l) is cross-symmetric with the term P3 (3) · X (-l), and the term P3 (2) · X (0) is cross-symmetric with itself. The filter banks 510 and 550 are not in phase. Such as the sixth (b) This paper standard is applicable to the Chinese National Standard _ (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling this page) -----.------ --------._-----— iT --- Fifth, the description of the invention (丨 7) A7 B7 Figure m shows that by mobile wave reduction equipment row 5 and the editing of the remaining two Road t Μ: "Two squid filter duck bricks will tickle R. Item 5 (1) ΛΛ (H steam I two; two? 5 by · Χ (-2) is symmetrical to take long time. (Team ♦; milk p5 (2 &gt; · X (-from the halo XM called J is (; 3 Qi (_, Hui Sai. 3 p5 ⑴ · x (〇). Is a cross-symmetrical good p zai for ... cut U (, get a special shout,., .. ''... R S, · · ·. ..--,-·-&quot; '_ ·· .. ·· P5 (0) · Χ (1) is cross-symmetrical. Item ρι (0), χίϋ: ν! And item Ρ5 (4) · Χ (-3 &gt; is black dance mat ...: t

L

The merger described above will generate a row of '% Λ' # h which is merged with t, and each merged filter row will have a ν = contact array element. Each pair of crossed symmetrical filter terms is: For the case of the same phase: tk t- (L-K + l) Ρκ (i) · X (I -I -i) &gt; Pl-κ + i ⑴ · ϊί ( Ι I -i)

L

L points

tk t- (L ~ K + l) Pk (nli) · X (I-"-(nl-i>) and Pl-κ + i (nli) ·) ((dagger-j J-(nli)) l L ”L I --- ^ --.--- f I installed ------ order ----- f ball (please read the precautions on the back before filling in this page) Central Ministry of Economic Affairs The printing and printing pair of the industrial and consumer cooperative is in the same phase: except for the i parameter in the product term, Pl-κ t- (L-K + l) (i)

t-K X (

L -i) and PK (nli) · X (L) This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 83. 3. 10,000 V. Description of invention (丨 tooth) A7 B7 (n-1 -i)) will be replaced by ii, in other cases like phases, the above-mentioned paired cross-symmetric row filter item combination method is used, and the frequency-increasing feature of each combined filter row is' (interpolation ... ... characteristic) yj (t) produces the following (assuming L is even): y Π-1 yj (t) = E pr (i) · χ (tk n-1 -i) + E Pl-κ + 1 ( i) * X (t- (L-K + l) -i) (9)

L

L t-k For each time t, a sample value x (-i) is

Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy Shifted into a corresponding K-th filter row 51〇-55〇 of an up-frequency filter 500. Generally speaking, this will change the value of one of the filter banks 510, 520, 530, 540 or 550. Similarly, for each t, only a merged filter bank that has merged cross-symmetric bank filter terms will change its output value. Therefore, in order to find the value of g (t) at any time t, the output value of the combined filter bank that has been changed] must be determined using equation (9). This changed output value is therefore added to the output of the combined filter row that has been previously determined]] (t), and its value has not changed between ti and t (if any), ( As discussed below I &quot; 丨 J-: --- ^ I installed ----- ^-丨 order ----- one or (please read the precautions on the back and then fill out this page) This paper size is applicable China National Standard (CNS) A4 specification (210X297mm) 83. 3.10,000 A7 B7 V. Description of invention (丨 f theory, for the phase of L &gt; 2, at each time t, there is always a- (It will change the value of the combined filter bank). Equation (9) can be further simplified, but the degree of simplification depends on the time when the next sample value is received. In detail, if

L (1+-) S K S L (where, change the value of the combination 2 and the filter bank is just to combine the cross-symmetrical filter terms of the same phase. In (1 +

L (Please read the precautions on the back before filling in this book) Printed by the Ministry of Economic Affairs, Central Standard Falcon Bureau Employee Consumer Cooperatives tk wL + KK _ Li-— L-t + k-1. WL + K + K-1 — L ·-, If (1 + L) SK £ L, then 2 tk t + ki —L-_ L-

W W + 2K-1 (12) W + 1 Equation (9) can be rewritten as follows (assuming L and η are even numbers) 'ul tk nl tk yj (t) = Z PK (i). Χ (I ——I -i) * £ PK (i) · X (i = 0 LLJ i = | j L ~ J'n Ul Σ i = 0 fK-i -K ♦ t (i) · Χ (

LT

nl -in * zi = U t * Kl X (! -I -ii) (13) This paper uses the Chinese National Standard (CNS) A4 specification (21〇Χ: 297 mm) V. Description of the invention (Μ A7 B7 Reorganization equations (I2) and (I3) produce 〆U-1 tk y〇 (t) = Z (Pk (i) # + Pl-k + x (i)) · [X (i = o

L i) t-k X (at 1 &lt; K &lt;-

L 2 t-k L L t + k-i

In the case of L:

wL + K—K

= W (please read the notes on the back before filling out this page), clothing.

L 2K-1 The Ministry of Economic Affairs Central Standards Bureau employee consumption cooperation du printing wL + K + K—1 — L — — L-therefore-if 1 &lt; Κ &lt; L, then 2 tk t + Kl-L-— L-combination Equations (13) and (15) yield yj = Ρκ (〇) · [χ (tk) + X (t + k -1 -L--L--n)] u_2 tk Σ (PK (i) + Pl -κ + i (il)) · (X (i = l 2PK (Ul) · X (

= W

L (15) -i) + X (order L '' t-k

L t-k -W-l)

L (16) This paper scale applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 3 Total 〇794 A7 B7 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (21) In equation (I6) In, the first and last addends are generated because the row filter terms are not in phase (these terms do not have cross-symmetric row filter terms). When either η and L are not even numbers, equations (14) and (16) will be modified to have different addends. The seventh figure depicts a FIR filter frequency increasing circuit 600 according to an embodiment of the present invention. The frequency multiplier 600 has a random access memory (RAM) 610 for receiving and storing the input sample values X tk X (— * L — tk -i) to Χ (tk -L--L --in) N + 1 sampling values of _i). RAM 610 is used to store secondary capacity. The illustration shows that each sample has b bits. The RAM 610 receives a chopped value X (t-k i) for every L phases of time t.

L An address generator 620 is connected to the random access memory 610. The address generator includes a loadable up-counter 622 and a loadable down-counter 624. An up-counter latch 621 is connected to the output value of the multiplexer 626 and the output value of the latch 621 is connected to an input value of the up-counter 622. A lower count latch I Μ ------ &lt; · installation ----- ^-order ----- (please read the precautions on the back before filling in this page) This paper size is applicable to China National Standard (CNS) Α4 specification (210X297mm) 83. 3.10,000 V. Description of the invention (22) A7 B7 The Down-counter Latch 623 of the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is connected to the down counter The output value of 624, and the output value of latch 623 is connected to an input value of down counter 624, a multiplexer 626 is provided to select the output value of up counter 622 or the output value of down counter 624, depending on An external control signal. The output value of the multiplexer 626 is output to the address port of the random access memory 610. The diagram illustrates that a two phase clock is used to enable the up counter 622 to count up and use The down counter 624 can count down. The output value of the random access memory 610 is connected to the input value of a latch 612 and an adder 614. The output value of the latch 612 is connected to the second input value of the adder 614. The samples addressed by the address generator 620 in the random access memory 610 can be selectively output to the adder 614 or the latch 612. A read-only memory 630 is used to store the tap coefficients of each combined row filter term (eg, the sum of the tap coefficients of the cross-symmetric row filter term and the non-in-phase combined rank The two tap coefficients of the filter term). The read-only memory 630 must have a cd capacity, in which the tap coefficient may have a d bit precision n L degree (d bit precision) and C = L ·-+ -〇 to n = 4 2 2 and L = 4, the read-only memory 630 has a minimum capacity of 10 days. However, a read-only memory with a capacity of 14d was used for illustration. The extra capacity is used to store zero value separators that separate the tap coefficients corresponding to each combined filter bank. This (please read the precautions on the back before filling out this page) The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x297mm) 83. 3.10,000 V. Description of invention (23) A7 B7 Central Ministry of Economic Affairs The printing of samples by the Bureau ’s consumer cooperatives can simplify control. described as follows. The address generator of the read-only memory 63 may be a simple up counter 632. The tap coefficient and the sum of the addresses addressed by the ROM counter 632 will be output from the ROM 63 〇 to a multiplier 64 〇. The sample sum output by the adder 614 will also be used as the input of the multiplier 640. The multiplier 64o multiplies the sum of each sample value output by the adder 614 and its corresponding tap point coefficient value output by the read-only memory 63o. The product thus formed is a combined row filter term, and is output from a multiplier 640 to a multiplexer 642. The output value of the multiplexer 642 is connected to the accumulator 644. The accumulator 644 has an output value which is regarded as the second input and is reconnected to the accumulator 644 as usual. It is possible to add a series of products output from the multiplier 64 using the multiplexer 642 and the accumulator 644 connected to each other. For example, the combined bank filter term can produce the output y] (t) of the combined bank. Finally, the accumulator 644 will be reset first. Then, a filter bank sums up the total control signal (generated by a control circuit not listed) to cause the multiplexer 642 to select the product output by the multiplier 64. These products are added to the existing sum at a time by the feedback connection from the output of the accumulator 644 to the second input value of the accumulator 644. The existing sum is stored in the accumulator 644 in. In addition, the output value of the accumulator is connected to a latch 646. The output value of this latch is regarded as the second input and is generally connected to the multiplexer 642. The output value of a combined filter bank formed in the accumulator 644 (t) can be stored in the latch 646 I ---- ^ ------ f strike-- (please read first Note on the back and then fill out this page) The size of the revised paper is in accordance with the Chinese National Standard (CNS) A4 specification (210X297mm) 83. 3.10,000 A7 __ ^ _____ B7 5. Description of the invention (2 buckets). At the next time t + i, this combined filter bank output value yj (t) can be added to another combined filter bank output value formed in the accumulator 644 (t + 1). For each filter bank there are n = 4 tap coefficients and its L = 4 filter banks, there will be a total of 16 tap coefficients Pl (〇), ...,

Pi (.3), P2 (〇),..., P2 (3),..., P4 (3). However, there are only 8 unique tap coefficient values hD -h7, which are taken out as a function shown in the eighth figure. These unique coefficient values hD -h7 are assigned to any filter row and are summarized in Table 1 below: nn — J nn III (please read the precautions on the back before filling this page) -Subscribe-Table 1 Value h〇 hi h2 h3 h4 h5 he h? Tap Pi (〇) P2 (0) P3 (0) P4 (0) Pi (i) p2 (i) p3 (1) p4 (1) Tap P4 (3) P3 (3) P2 (3) Pi (3) P4 (2) P3 (2) p2 (2) Pi (2) Printed by the Peking Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs to substitute these tap point coefficients hQ -h7 After equations (11) and (I2), the characteristics of the filter bank that has been merged between each t and ti will change, as described below: This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 83.3.! 〇, 〇〇〇3 ^ 〇794 A7 ________B7 V. Description of the invention (25 *) Table of merged filter rows modified between t and ti t = l 典 t = 0 y! (1 ) = yi (l> + y4 (l) = h〇 (x (0) + x (-4)) + (h3 + h4) (χ (-1) + χ (-3)) ♦ 2h7 x (- 2) t = 2 Code t = l y2 (2) = y2 (2) * y3 (2) = h1 (x (0) * x (-4)) + (h2 + h5) (x (-1) + x (-3)) ♦ 2ht x (-2) t = 3 and t = 2 yz (3) = y2 (3) * ya (3) = (hi + hz) (x (0) + x (-3 )) + (hs * h4) (x (-1) * x (-2)) t = 4 Code t = 3 yi (4) = yi (4) * y4 (4) = (h〇 + h3) (x ( 0) * x (-3)) + (h4 * h7) (x (-1) * x (-2)) t = 5 Code yi (5) = yL (5) + y4 (5) = ha (x (1) + x (-3)) + (h3 + h4) (x (0) * x (-2)) + 2h? X (-l) t = 6 and t = 5 y2 (6) = y2 ( 6) + ya (6) = hl (x (1) + x (-3)) + (h2 + h5) (x (0) + x (-2)) 2h &amp; x (-l) t = 7 And t = 6 yi (7) = yz (7) + y3 (7) = (ht + h2) (x (1) + x (-2)) + (h5 + h6) (x (0) + x ( &quot; 1) &gt;----; ----- 威威 ------ (please read the notes on the back before filling in this book) Printed by Beigong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs More valuable is that g (t) can add the output value of the merged filter row that changes the value between ti and t] (t) to the merged filter that does not change the value between tl and t The output value of the device is yi (t), y 〖(t), 83. 3.10,000 The paper size is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 mm) A7 ________B7 V. Description of invention (26) Central Standard of the Ministry of Economic Affairs Bureau staff consumer cooperatives printed ..., yj-1 (t) »yj + 1 (t), yj + 2 (t), ..., y ^ J (t) were obtained. In the case of L = 4, there are only two merger filter banks. That is, a filter bank output value (t) that changes the value between t-1 and t and a filter bank output value y] (t) that does not change the value between t-1 and t. Now let ’s discuss the operation of the present invention in the ninth figures (a)-(z), (aa), (bb), (cc) and (dd) under the condition of L == 4 and N = 4. First, the first Figure 9 depicts the states of counters 622, 624, and 632, random access memory 610, and read-only memory 630. The read-only memory has 14 storage cells used to store the tap coefficients and the sum of the tap coefficients of the cross-symmetric filter. According to the changed merged filter bank shown in Table 2, the tap coefficients or the sum of tap coefficients will be grouped. This combination is separated by zero values. The random access memory 610 has n + 1 or 5 cells. It is first used to store 5 sample values x (〇), x (-1), x (-2), x (-3) and x (-4) ). For L time t-k periods, a new sampling value X (I--i) is shifted into the cell of random access memory 610 used to store the oldest sampling value. ----:-: --- ί Pack ----- ^-丨 Order ----- ί Bismuth (please read the precautions on the back before filling in this page) This paper size is suitable for Chinese national standards (CNS) Α4 specification (210X297mm) 83. 3.10,000 3 20794 A7 B7 V. Description of invention (27) The Ministry of Economic Affairs Central Standards Bureau Beigong Consumer Cooperative printed and read-only memory counter 632 was set from the initial value to read-only In the first cell of the memory 630 (for example, set to 0), the upper counter 622 is set to the first cell of the random access memory 610 (for example, set to 0) and the lower counter 624 is set Set the initial value point to the last cell of the random access memory 610 (for example, set to 4). The upper count latch 621 and the lower count latch 623 are set to initial values of 0 and 4 respectively. In the ninth (a) diagram of the first phase of the first clock pulse, the multiplexer 626 selects the count of the upper counter 622 to determine the address of the random access memory 610. The random access memory 61o therefore outputs the sample value x (0) indicated by the upper counter 622. The sample value x (〇) is stored in the latch 612. At the second phase of the first pulse clock (the ninth (b) diagram), the up counter 622 counts up to 1. The multiplexer 626 selects the number of the counter 624 to determine the address of the RAM 610. In response, the random access memory 610 outputs the sample value x (_4). The adder 614 adds the sample value x (_4) to the sample value x (0) stored in the latch 612◊The adder 614 outputs the sum x (〇) + x (_4) to the multiplier 64. Further, the read-only memory 63o outputs the h0 value addressed by the read-only memory counter 632 to the multiplier 640. The multiplication 640 multiplies h〇 with the sum x (〇) + Χ (_4) and outputs the product (eg, row filter term) hD (Χ (0) + x (-4)) to the multiplexer 642. This multiplexer outputs the product h0 (Χ (0) + x (-4)) to the accumulator 644. In the first phase 9 of the second cycle (the ninth (c) diagram), the multiplexer 626 selects the number of the upper counter 622 to determine the random access memory 610 ----.----- f Installation — (Please read the precautions on the back before filling in this page) This paper size is printed in Chinese National Standard (CNS) A4 (210X297mm) 83. 3.10,000 Printed by the Consumer Labor Cooperative of the Central Escalation Bureau of the Ministry of Economic Affairs Prostitute 07 94 A7 __ B7 V. Description of invention (2 points) Address. In response, the random access memory 610 stores the sample value x (-1) in the latch 612. Simultaneously, the down counter counts down to 3 and the read-only memory counter 632 counts up to 1. On the two phases of the second cycle of sound (the ninth (d) diagram), the multiplexer 626 selects the number of the counter 624 to locate the random access memory 610. In response, the random access memory 610 outputs the sampling value χ (-3) to the adder 614, where it is added to the sampling value X (-1) in the latch 612. Simultaneously, the read-only memory 630 outputs a combination of tap point coefficients h3 + h4 addressed by the counter 632. The sum h3 + h4 and the sum. X (-l) + X (_3) are multiplied in the multiplier 64〇 and the product (h3 + h4) (X (-l) + x (-3)) thus formed is Output to the multiplexer 642. The multiplexer 642 selects the product (h3 + h4) (χ (-1) + Χ (-3)) output from the multiplier 640 as the input value of the input accumulator 644. The accumulator 644 adds the product (h3 + h4) (χ (-1) + χ (_3)) to the product h〇 (Χ (0) + Χ (-4)) that has been stored in the n ° ° in the third On the first phase of the loop (Figure 9 (e)), the multiplexer 626 selects the number of the upper counter 622 to locate the random access memory 61. In response, the random access memory 610 stores the output of the sampling value χ (-2) in the latch 612. Simultaneously, the down counter counts down to 2 and the read-only memory counter 632 counts up to 2. On the second phase of the third cycle, the ninth (f) figure multiplexer 626 selects the number of the counter 624 to locate the random access memory 610. The random access memory 610 outputs the sample value x (-2) to the adder 614, where it is added to the sample value X (-2) in the latch 612, and at the same time, the read-only memory 63 will be Read the tapping point coefficient I of the memory 632 location address ---------- f · install ------ order ----- (please read the precautions on the back before filling this page) This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 83. 3.10,000 32〇tg4 A7 ___________B7 V. Description of invention (2?) Printed by the Industrial and Consumer Cooperative Cooperative of the Zhongshang Standards Bureau of the Ministry of Economic Affairs . The tap coefficient h7 is multiplied by 2 x (-2) in the multiplier 640, and the product 2h7 x b 2) thus formed is output to the multiplexer 642. The multiplexer 642 selects the product 2h? X (_2) output by the multiplier 64〇 as the input value of the accumulator 644. The accumulator 644 adds the product 2h7 χ (-2) to the product sum (h3 + h4) (χ (-ι) + χ (-3)) + h0 (x (0) + x (-4) ) Add. Therefore, the accumulator 644 produces the output 〆yi (t). Up and down counters 622 and 624 on the first phase of the fourth cycle (the ninth (g) diagram) will be stored with the latches 621 and 623 respectively connected to them. Number of loads. Further, the read-only memory counter 632 counts down to 3. The product sum 2h7 x (-2) + (h3 + h4) (x (-i) + x (-3)) + h〇 (x (0) + X (_4)) is stored in the accumulator 644 and is Output to latch 636 and store there. The product represents the portion of g (t + i) that will not change between t and t + i. That is, the output value yl (t) of the merge filter row that does not change between t = l and t + l = 2. On the second phase of the fourth cycle (Figure 9 (h)), the read-only memory counter 632 locates the read-only memory 630. However, the value of the located address is zero, and therefore, only the zero value is output from the multiplier 640. On the first phase of the fifth cycle (Figure 9 (i)), the multiplexer 626 selects the number of the up counter 622 to address the random access memory 610. This causes the sample value X (O) to be output from the random access memory 610 and stored in the latch 612. Read-only memory counter 632 counts up to 4 〇 (please read the precautions on the back before filling in this page) This paper size is suitable for China National Standard (CNS) A4 specification (210X297mm) 83. 3.10,000 A7 ____B7 3. Description of the invention (3) On the second phase of the fifth cycle printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (Figure 9 (j)), the multiplexer 626 selects the number of counters 624 to be Random access memory 610 location address. This causes the sample value output from the random access memory 610 to be input to the adder 614. This adder adds the sample value X (-4) to the sample value χ (〇> stored in the latch 612, and outputs the sum χ (_4) + χ (0) to the multiplier 640. Read only The memory counter 632 locates the address in the read-only memory 630 so that the hi value is output to the multiplier 640. The multiplier 640 multiplies the hi value by the sum x (-4) + x (0), and will The product hi (x (-4) + X (0)) is output to the multiplexer 642. The multiplexer 642 outputs the product hi (X (-4) + X (0)) to the accumulator 644, where the product is Store it. On the first phase of the sixth cycle (the ninth (K) diagram), the multiplexer 626 selects the number of the up counter 622 to locate the random access memory 610. This makes the sampling value X (-l ) Is output from the random access memory and stored in the latch 612. The read-only memory counter 632 counts up to 5. Further, the down counter 624 counts down to 3. On the second phase of the sixth cycle ( (Ninth (1)), the multiplexer 626 selects the number of the counter 624 as the random access memory 610 location address. This causes the sample value x (_3) to be output from the random access memory 61〇 to the adder 614. This adder will sample the value X (-3) is added to the sample value X (-l) stored in the latch 612 and the sum x (_3) + x (_l) is output to the multiplier 640. The read-only memory counter 63 2 will be in The read-only memory 630 there is located so that the h2 + h5 value is output to the multiplier 640. The multiplier 640 multiplies the h2 + h5 value by the sum x (-3) + x (-l) and multiplies the product ( h2 + h5) (Χ (-3) + Χ (-1)) output to the multiplexer 642, the multiplexer 642 outputs the product (h2 + h5) (x (-3) + x (-l)) to the cumulative I ------; I:-^ -installed ------ ordered (please read the $ item on the back and then fill in this page) This paper size is applicable to China National Standard (CNS) A4 specification (210X297 Mm) 83. 3.10,000 V. Description of the invention (31) A7 B7 The Ministry of Economic Affairs, Central Bureau of Economic Development, Beigong Consumer Cooperative printed a meter 644, where the product is added to the product hi (X (X ( -4) +} £ (〇)). The number of the down counter 634 is stored in the latch 623 ° The first phase of the seventh cycle (the ninth (m) figure) multiplexer 626 is selected up The number of the counter 622 is used to locate the random access memory 610. This allows the random access memory 610 to store the samples stored in the latch 612 X (-2) output. The read-only memory counter 632 counts up to 6. Further, the down counter counts down to 2. The second phase of the seventh cycle (the ninth (η) diagram), multiplexing The device 626 selects the number of the counter 624 to locate the random access memory 610. This causes the random access memory 610 to output the sampling value χ (-2) to the adder 614. The adder 614 adds the sample value x (-2) to the sample value x (-2) stored in the latch 612 and outputs the · 2Χ (_2) value to the multiplier 640. At the same time, the read-only memory counter 632 positions the read-only memory 630 there, so that the read-only memory 630 outputs the h6 value to the multiplier 64〇, and the multiplier 64〇 compares the h6 value with 2 x (_2) Multiply and output the product 2h6 X (-2) to the multiplexer 642. The multiplexer 642 outputs the product 2h6 X (_2) to the accumulator 644, where it is. The product is added to the product sum stored there (h2 + h5) (x (-3) + x (-l)) + hi (X (-4) + X (0)). The sum (h2 + h5) (xi-SJ + xi-lH + hi (x (-4) + x (0)) + 2h6 x (-2) generated by the accumulator 644 is the combined filter row yl ( t) The output value. On the first phase of the eighth cycle (the ninth (〇) diagram), the upper counter 622 and the lower counter 624 will be connected to the latch 621 or 623 m. 1 ^ 1 m I (please read the precautions on the back before filling in this page)-Order &quot; This paper size is applicable to China National Standard (CNS) A4 specifications (210X297mm) 83. 3.10,000 320794 A7 B7 V. Invention description (more 2) The Ministry of Economic Affairs, Central Bureau of Accreditation and Employee Consumer Cooperatives printed and stored separately. However, the first phase of the first cycle (ninth (a) diagram) and the first phase of the fourth cycle ( (The ninth (g) diagram) is different. The number input to the down counter 624 is 3. (In the second phase of the sixth cycle, this number has been stored in the latch 623). The read-only memory counter 632 counts up to 7. The multiplexer 642 selects the sum corresponding to g (2 &gt; unchanged part) as the input value of the accumulator 644. As a result, the accumulator outputs the unchanged filter row output value yi (1 ) Is added to the changed filter bank output value h (2) just calculated. This sum corresponding to g (2) is output to the accumulator 644. As shown in Table 2, the combined filter bank The output value (2) changes again between t = 2 and t + l = 3, for example, y2 (3) is not equal to (2). However, yi (t) does not change between t = 2 and t + l = 3 Will change. Therefore, the combined filter bank output value y2 (2) will not be stored in the latch 646. Instead, the latch 646 retains the combined filter bank output value Yi (t) to determine g (3). ： —.--- f.- 装 ----- ^ — 定 ----- &lt; swimming (please read the precautions on the back first and then fill out this page) Standard (CNS) A4 specification (210X297mm) 83. 3.10,000 V. Description of invention (33) A7 B7 The Ministry of Economic Affairs Central Bureau of Labor and Industry Employees Consumer Cooperative printed on the second phase of the eighth cycle (ninth) (P) graph), the read-only memory counter 632 causes the read-only memory 630 to output a zero value (which has no effect on the calculation of g (t)). At the first phase of the ninth cycle (ninth (q) graph ), The multiplexer 626 selects the number of the counter 622 Addressing the random access memory 610. This causes the random access memory 610 to output the sample value X (O) to the latch 612 and store it there. The read-only memory counter 632 counts up to 8. In the second phase of the ninth cycle (ninth (r) diagram), the multiplexer 626 selects the number of the down counter 624 to locate the random access memory 610. In response, the random access memory 610 outputs the sample value x (-3) to the adder 614. The adder 614 adds the sample value x (_3) to the sample value X (〇) stored in the latch 612, and outputs the sum X (〇) + X (-3) to the multiplier 64. At the same time, the read-only memory counter 632 addresses the read-only memory 630. In response, the read-only memory 63o outputs hi + h2 to the multiplier 640. The multiplier 640 multiplies hi + h2 and χ (0) + χ (-3) to produce a product (hi + h2) (χ (0) + Χ (-3)). This product is output to the accumulator 644 via the multiplexer 642 and stored there. The above process is carried out in a similar way to calculate each g (t), as shown in the ninth (s)-(z), (aa), (bb), (cc) and (dd) diagrams . Both the upper counter 622 and the lower counter 624 count through zero (count through 0). That is, after counting up to 4., counting up HI- ί — Jn----1 ^^ 1 ^ I (please read the precautions on the back and then fill out this page) Order 1 This paper size is suitable for Chinese countries Standard (CNS &gt; A4 specification (210X297mm) 83. 3.10,000 V. Description of the invention (3 buckets) A7 B7 device 622 counts to 0. Similarly, after counting down to 0, the counter 624 counts to 4. The number of the counter 624 is the second phase in the sixth cycle (the ninth (1) diagram, which is stored in the down counter of the latch 623. The output value of the multiplexer 626 is the first in the twelfth cycle The two phases (ninth (X) graph) and the first phase in the fifteenth cycle (ninth (CC) graph) are stored in the up counter of the latch 621. At each time t mod L = l, a new sampling value tk -i) is written in the random access memory 610 ◊for example I ----------- f attack-- (please read the note $ item on the back first (Fill in this page again)

At t = 5, x (l) is shifted into the addressed cell (addressed cell) 4. When t-k a new sample value x (-i) is written in random access memory

In L 610, an appropriate control signal is transmitted on control line 617 (low signal). This allows data to be written into random access memory 610, and enables data to be transmitted through tristate buffer 616 to be printed on bus 618 by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Therefore, an input sample value t-k • i) is output on the bus and written to the random access memory

L This paper scale is applicable to China National Standard (CNS) A4 (210X297mm) 83. 3.10,000 ^ 0794 V. Description of the invention (35) A7 B7 Central Government Bureau of Economic Affairs, Ministry of Economic Affairs, Unemployed Consumer Cooperatives printed tk memory 610. When the input sample value x (--i) is written, an L-a high signal is sent on the control line 61 * 7, at this time, it can be read again from the random access memory 610 Sampling value, and through the three-state buffer 616 so that it does not transmit data. In the subsequent process, the changed and merged filter bank output value y'2 (t) determined by t = 5 is stored in the latch 646 because the output value y2 (t) is at t = No change between 5 and t = 6. On the other hand, the output value yl (t) of the combined filter bank will change its value between t = 5 and t = 6, so it can be discarded. In the calculation of each g (t), the frequency multiplier 600 performs a 2-addition with the adder 614 η prepared to proliminarily sample the value to be added. However, this can be improved by replacing it with circuits 620, 610, 612, and 614. Such a circuit can properly store and store the sample input values and output them to the multiplier 64 at the appropriate time. This (please read the precautions on the back and then fill out this page) This paper scale is applicable to the Chinese National Standard (CNS) 八四 说 格 (21〇χ297mm) m _〇〇A7 B7 V. Description of the invention (36) Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, when multiplying the sample value by the tap coefficient or the η sum of the tap coefficient, the multiplier 64 will perform at most-+ 1 multiplication. Accumulator 644 Adding the filter term for the addition of 2 η needs to be performed — an addition to form the output value of the filter row 2] (t) ° Further, the accumulator 644 outputs the output value of the addition filter row κ L yi (t ) Needs to perform an addition to form g (t). 2 Very differently, the filter 200 (third figure) uses at least η multiplications and several additions to calculate each g (t) ° frequency increase 600 has been described in the case of n = 4 and L = 4. However, a frequency multiplier 600 can be used in any case of n and L. Random access memory 61〇 and read-only memory 630 must be adjusted according to the difference of n. In addition, the tap coefficient stored in the read-only memory 630 must be recalculated according to η and L. Further, The sequence of counters 622, 624 and 632, multiplexer 626 and latches 621 and 623 must be properly modified. When L = 2, there is only one merge filter bank. A tl and t change. Therefore, the latch 646 and the worker 642 can be removed. Instead, the accumulator is directly connected to the output value of the multiplier 64. (Please read the notes on the back before filling in This page is loaded · This paper scale is applicable to the Chinese National Standard (CMS> A4 size (210X297 mm) 83. 3.! 0, 〇〇〇A7 _B7 V. Invention description (37) Employee consumption of the Central Standards Bureau of the Ministry of Economic Affairs Cooperative society splits L> 4, the output value of more than one merge filter row (t) remains unchanged between t-ι and t. Therefore, the latch 646 can be used by one multiplexer and one To store the output value yi (t) of each unchanged filter bank. The multiplexer is connected to the output value of the accumulator 644 and alternately stores the value generated in the accumulator 644 in each A latch. Similarly, the multiplexer 642 can be appropriately modified to select one by one, The output value (t) of the filter bank stored in each of these latches in a cyclic manner is unchanged, and is accumulated with the calculated and changed output value of the filter bank (t) in the accumulator 644 To determine the value of each g (t). The tenth figure shows a frequency multiplier 700 of the second embodiment used in a video application according to the present invention. The frequency multiplier 700 differs from The conventional finite impulse response filter 400 in the fifth diagram is similar. The frequency multiplier 700 has a module core 710 and a binary adder tree 790 with an adder 791. The difference is that The symmetric row filter term combination method uses a synthesis filter row to replace the bit planes method of combining input sampling values (using the qth, (q + 1) th bit neighboring pairs to perform calculations . Therefore, the processing based on the aforementioned technique of the finite impulse response filter 400 requires --------- f -installed ----- 1 order ------ ih (please read the notes on the back first (Fill in this page again) This paper scale is applicable to the Chinese National Standard (CNS &gt; A4 specification (21〇X297mm) 83. 3.10,000 ^ 0794 V. Invention description (3 teeth) A7 B7 request (required circuit processing time) It mainly depends on the number of bits b of the input sampling value, and the processing demand of the multiplier 700 depends on the number of tap coefficients η. The eleventh figure shows an embodiment of the module core 710. The module core 710 has one Will the input sampling value χι tj? I) Selectivity

The L grounds are added together to form the preprocessing stage of the sum of the sampling values. This preprocessing stage has a shift register 722. The scratchpad has n + 1 scratchpads, which are connected together in tandem. This previous processing stage 720 also has U + l multiplexers 724-0, 724-1, (please read the precautions on the back before filling out this page) to install. Order.-). Every Uth Multi-Ministry of Economic Affairs Central Bureau of Industry and Commerce Beigong Consumer Cooperative Printed η »724-η», 724-U (where U = worker 724-U (where 〇SuSU). Except for multiplexer 724 -u, will receive t &quot; t- I sample value X (-n + u-i + 1), X (LL ”— L _ -n + ui) and this sample value is stored in the register 722- (nul ) And 722-nu. For example, the multiplexer 724-0 receives sampling values x () from the registers 722- (nl) and t-s 722-n, respectively.

L 83. 3.10,000 The size of this paper adopts the Chinese National Standard (CNS) A4 specification (210X297mm)

X I t-1

The L device 722- η A7 B7 multiplexer 724_u takes the value and zero value stored in the temporary storage as input values. The multiplexer 724-0 · ’724_u selected one of the input values under the control of an externally generated signal ct2. This preface 丨〗 ~ The processing stage 72〇 also has U adders 726-0, 726-1 &quot; ·, 726_u, · _ · ,. Each u-th adder (of which HUSU-I) 726_u will store the sample stored in the u-th temporary register 722_u-X (t-

L • U-i) are added to the sampling value selected by the u-th multiplexer. The sum of these sampling values is suitable for multiplying the tap point coefficient values corresponding to the combined filter bank. The sampling value and the sum of the sampling value are output from the adder 726-0,..., 726-U-1 and the multiplexer 724-U in parallel to a multiplying stage 730. --- ： ---: --- 1 '赛 ----- 1-5 (please read the precautions on the back before filling this page). The paper size of the printed paper is printed by the Employee Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs. Applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) 83. 3.10,000 A7 B7 V. Description of invention (4〇) Multiplied by the Central Bureau of Standards of the Ministry of Economic Affairs Beigong Consumer Cooperatives 73. U + 1 A number of selector point coefficient selector circuits (selector circuits) 735 is connected to 0,735-1, ..., 735-u, ..., 735_U, which are connected together in tandem. Each selection circuit 735-0, ..., 735-U corresponds to a specific merge row filter item selection circuit 735-0, 735_U corresponding to each merge filter row and outputs a minute in parallel at each time t Contact coefficient value. Each selection circuit 735-u includes a multiplexer 732-u connected to a shift register 734-u. For example, the selection circuit 735-1 includes a multiplexer 732-1 connected to the shift register 734-1. Multiplexer 732-U tap point coefficient value output from its own displacement register 734_u, or tap point coefficient value output from the previous selection circuit 73〇-ul's displacement register 734-ul, both Among them, choose one according to an external control signal Ctl. (The multiplexer 732-0 is an exception. It selects one of the tap coefficient values output from its own shift register 734-0 or the tap coefficient values input on line 736.) The shift register 734-u stores L tap coefficient values, that is, one tap coefficient value under each merge filter row. These tap-point coefficient values are stored in each shift register 734-U in the same order. The tap point coefficient value is fed back to its corresponding multiplexer. Therefore, each shift register 734-U cyclically repeats every L time period at time t, from which tap coefficients are output. The multiplication stage 730 has U + 1 multipliers 740-0, 740-1, ..., 740-U, ..., 740-U. These multipliers 740-u may be any one (please read the precautions on the back before filling in this page) • Installed · This paper size is suitable for China National Standard (CNS) A4 specification (210X297mm) 83. 3. 10,000 Fifth, the invention description (41) A7 B7, the Central Standards Bureau of the Ministry of Economic Affairs, the Ministry of Economy, Labor and Consumer Cooperation, the Duyin multipliers, including the optimal Booth's algorithm multipliers (optimized Booth7s algorithm multipliers). Each uth multiplier 74. u receives the output value of a corresponding tap point coefficient selector 735_u. (In particular, the tap point coefficient value is shifted out from the shift register stage 734-u bit). Each of the multipliers 740-0, 740-1, ..., 740-U-1 adds the tap point coefficient values to the adders 726-0, 726-1, ... of the previous processing class 720. , The output value of 726-U-1 is multiplied. The multiplier 74〇-U multiplies the tap point coefficient value it receives by the output value of the multiplexer 724_u. Each multiplier 740-U outputs a corresponding merged row filter term yxD, yxi,..., Yxu..., Yxv, these merged row filter terms yxD, yxj_,..., Yxu... , Yxu are each received by a corresponding binary adder 791 (Figure 10) of the binary addition tree 79 (710). This binary addition tree 790 adds the combined row filter terms yx〇, yxu, yxu, yxu at any time t. This binary addition tree 790 outputs y (t). The latch sub-circuit 760 includes J individual latch I ~ b π registers (where J =-). In order to calculate each g (t), the first 2 first, store the changed merge filter output value] (t) in the multi-I- —JI--—-1 -installed-- (please Read the precautions on the back first and then fill out this page) Order 4- This paper scale uses the Chinese National Standard (CNS) A4 specification (210X297 mm) 83.3.! 0, 〇〇〇A7 _B7 V. Description of the invention (Order 2) Among the j-th latches of the latch sub-circuit 77〇 selected by the printing tool 760 of the Male Workers ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. The control line 755 is then used to clear the accumulator 750. In the second step, the multiplexer 78 selects the output value of each jth latch from 1 to J, (which stores the output value y / (t) of the jth merge bank filter). The selected jth latch output value is input to an input value of the accumulator 75〇. By calculating the output value y / (t) of all the combined row filters, the accumulator 75 generates the up-sampled output value (the interpolated sample output) g (t). The tenth and eleventh figures will be discussed in detail below The operation of the frequency multiplier 700 is shown. Assuming that the frequency multiplier 700 is an L = 4 phase and n = 4 tap coefficient multiplier, it is multiplied by b bit t-jj sampling value X (--i ). In this inert shape, u = 2. First, ctl_L_ is set to zero. Therefore, the multiplexer stage multiplexer 732-0 selects the tap coefficient input on the input line 736. The other multiplexers 732-1 and 732-2 select the tap coefficient values output from the previous selection circuit 735-0 or 735-1. The displacement registers 734_〇, 734-1 and 734-2 are first loaded with their tap point coefficient values via the input line 736. Table 3 summarizes the contents of I ---------- &lt; outfit -------- order ----- ^ i (please read the precautions on the back before filling this page) Applicable to China National Standard (CNS) A4 specification (210X297mm) 83. 3.10,000 32〇794 at — B7 Mingfa into each displacement memory 734-0, 734-1 and 734_2 branch point coefficient value ： Table 3 Displacement register tap coefficient value (in order of output value ·· from left to right) 734-0 734-1 734-2 h〇f hi 9 hj ^ + h2, h〇 + 1¾ h3 + ¾., H2 + h5, h5, 1¾ + h7 2h7, 2h &amp;, 0,0 Pack-(please read the notes on the back before filling this page) Employee consumption cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs is printed, then, The ctl is set so that the multiplexers 732_〇, 7324, and 732-2 select the tap point system output from the corresponding displacement registers 734_〇, 7344, and 734 ~ 2. For every L-time welcome period at time t, repeat the following steps. First, the next (next) sample value x (--i) is shifted into the shift register of the previous processing stage — L ″ 7 22. The signal Ct2 is set to 1, so that the multiplexer 724-u selects the sampling value stored in the register 724_ (n-u). That is, the multiplexer 724-0 selects the sampling value stored in the toilet 722_4, the multiplexer 724_1 selects the sampling value stored in 722_3 and the multiplexer 724-2 selects the sampling stored in 722_2 value. As a result, the adder 726_〇 adds the sample values stored in the register 722-0 and 72 2-4, that is, Χ (0) + Χ (_4). This sum is output to the multiplier 740-0. Similar to the size of this paper, the Chinese National Standard (CNS) A4 specification (21〇X297mm) is applicable 83. 3. 10,000 A7

V. Description of Invention (Wf) Printed by the Ministry of Economic Affairs Central Bureau of Accuracy and the Beigong Consumer Cooperatives' adder 726_1 will be the sum of the sampling values stored in the registers 722_1 and 722_3, ie, Χ (-1) + χ (- 3), output to the multiplier 74. The multiplexer 724_2 outputs the sample value stored in the register 722_2 to the multiplier 740-2, that is, χ (-2). The selector 73〇-0 outputs the coefficient value of the first tap point there, for example, hD, to the multiplier 74〇_〇. The multiplier 74〇_〇 multiplies the corrected coefficient by the sum of the sample values output from the adder 726-0. This product is output as the first row filter term yxQ. Similarly, the selector 73〇-1 outputs the coefficient value of the first tap point stored in that loop, for example, h3 + h4, to the multiplier 74〇-1. The multiplier 740-1 multiplies the corrected coefficient by the sum of the sample values output from the adder 726_1. This multiplication is regarded as the output of the second row filter term yXl. The selector 730_2 will store the coefficient value of the first tap point stored in that center, for example, 2h7 and output it to the multipliers 74〇 ~ 2. The multiplier 74〇_2 multiplies the corrected coefficient by the sample value output from the multiplexer 724_2. This product is output like the third row filter term yx2. The row filter terms yX (), yXl, and yx2 are output in parallel to the binary addition tree 790.

L In the next cycle to the kth-Jth cycle, the multiplexers 724-0, 724_1 and 724_2 select the same sampling value, and the adders 726_〇 and 726-1 output the sum of the same sampling value. The selectors 735-0, 735-1 and 735-2 output the tap coefficient values corresponding to that cycle. That is, ----.----- ^ -installed ----- ^-ordered (please read the precautions on the back before filling in this page) This paper size is in accordance with Chinese national standards (CNS &gt; A4 specification (210X297 mm) 83.3.10,000 3807 (A7 B7) 5. Description of invention (4 left) Printed by the tec industrial and consumer cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs in the second cycle, selector 735-0 outputs hi, selector 735-1 outputs h2 + h5, and selector 735_2 outputs 2h. Multipliers 740-0, 740-1, and 740-2 will correspond to the sampling value from the multiplexer 724-2 or from the adder 724_〇 and Sampling and multiplying 724 to generate individual row filter terms yx〇, yxi and yx2 0 L Starting from cycle-+ 1, the control signal Ct2 is changed to -2 ″ is 〇. This makes each multiplexer 724 -u (except the multiplexer 724-U) to select the sampling value stored in the register 722-nul as the input value of the adder 726-U. That is, the multiplexer 724_〇 has selected to store in 722- 3 The sampling value in the register and the multiplexer 724-1 select the sampling value stored in the temporary device 722_2. The multiplexer 724_2 selects the zero value. Therefore, the adder 726_0 will be stored in the register 722_0 and The sampling and output in 722-3, for example, χ (0) + χ (-3). The adder 726-1 will output the sum of the sampling values stored in the registers 722-1 and 722-2, namely χ (-ι) + χ (-2) 〇L In the (-J +1) th cycle, the selector 735-u outputs the coefficient value of the (-+ 1) th tap point stored in L. For example , In the second cycle of -2-, the selector 735-〇 output coefficient hi + h2, the selector 735-1 output coefficient h5 + h6 and the selector 735_2 output zero. Multiplication (please read the notes on the back before filling in this Page) This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 83. 3. 10,000 V. Description of the invention (and) A7 B7 Printer 740-0 of the Zhengong Consumer Cooperative Society of the Central Bureau of Economic Development of the Ministry of Economic Affairs Then multiply the coefficient hi + h2 by the sum X (0) + X (_3). The multiplier 740-1 multiplies the coefficient h5 + h6 by the sum X (-l) + X (_2), and the multiplier will be The number zero is multiplied by zero. These products are treated as row filter terms yx〇, yh, and yx2, respectively, and output to the binary addition tree and accumulated to determine the value of yj (t). For each cycle, multiplexers 724_0, 724-1 and 724-2 are selected Zhi the same sampling and 726_1 and the adder 726-0 output and at the same sampling Zhi. The selectors 735-0, 735_1, and 735_2 output the tap coefficients relative to that loop. That is, in the fourth cycle, the selector 735-0 outputs hD + h3, and the selector 735-1 outputs h4 + h7, and the selector 735-2 outputs zero. The multipliers 740-0 and 740-1 are multiplied by the sum of the corresponding sampling values output from the adder 724-0 or 724-1 to generate individual modified row filter terms yxQ, yxi (multiplication The multiplier 74〇_2 multiplies the coefficient zero by the zero value output from the multiplexer 724_2 to generate the combined bank filter term yX2 = 0.) These combined bank filter terms yxQ, yXl, and yX2 are added in binary Tree 79〇 accumulated to determine the value of yj (t). Finally, after accumulating all J numbers of the output value yj (t) of the merge filter, the accumulator 750 outputs g (t). The above process is then repeated, that is, the next sampling value t-1 x (| ^ — J _i + l) (called, x (l)) is shifted to the previous place (please read the back side first) Note $ item and then fill out this page). 装 · Order _ This paper size is suitable for China National Standard (CNS) Α4 specification (210X297 mm) 83. 3.10,000 A7 B7 Printed by Beigong Consumer Cooperative Cooperative of Central Central Bureau of Economic Affairs System 5. Description of Invention (47) The shift register 722 of the management stage 710, and the signal ct2 is set to 1, and so on. At the beginning, the shift register 722 may be mostly empty. Therefore, the initial determination of * g (t) may not be very useful. Conversely, the shift register 722 can be pre-loaded with approximate sampling data so that all decision values of g (t) are available. The frequency multiplier 700 requires very low processing requirements compared to the FIR filter 400 (fifth figure). The binary adder tree 790 of the frequency multiplier 700 requires n adders to previously process the input sample value and less than (approximately 2 n ground)-adders used in the binary adder tree. The multiplication stage 730 requires 2 η. If-+ 1 multiplier is required, or an amount equal to the Booth multiplier is used by 2 n b, (-+ 1)-adders are required. Therefore, the 2 2 frequency multiplier according to the present invention can be executed with approximately ((ϋ + 1) .- ^-+ η) 2 adders. Conversely, the binary addition tree 43〇 of the finite impulse response (FIR) b filter 400 requires approximately (n + 1) -2 adders. Therefore, the traditional finite impulse response filter 40 (/ requires the following more adders: This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm) 83. 3.10,000 ^ — ^ 1, -... ..I n 1-— ^ ϋ In I (Please read the precautions on the back before filling in this page) Order A7 B7 V. Description of invention (fight?) Bn bnb (n + 1) ·--((-+ 1 ).-+ n) =-(--2) 2 2 2 2 2 Generally speaking, each video sampling value is more than 4 bits, that is, b &gt; 4 ° Therefore, use an upconverter 700 can achieve a saving effect. In short, the present invention discloses a multiplier with a combined filter bank by combining cross-symmetric filter banks. With this combination of filter banks, the processing process can be reduced Requirements (that is, the number of circuits, the space occupied by the circuits, and the processing time) without hindering the accuracy or efficiency of the frequency multiplier. However, the illustrations disclosed above in the present invention are only for the present invention. Embodiments, for those who are familiar with the skills of the case, according to the spirit of the case, the equivalent changes or modifications of the embodiment, It should be covered in the following patent applications in this case: ^^ 1 '— ^ 1 ^^ 1- ^^ 1 — ^ 1 · _ϋ— ^ (please read the precautions on the back before filling out this page) Order_Ministry of Economic Affairs Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards 83. 3.10,000 This paper size is suitable for China National Standard (CNS) Α4 specification (210X297 mm)

Claims (1)

Patent application scope A8 B8 C8 D8-a digital filter, based on L filter rows and n. Tap coefficients Pj? (I) for each filter row of the line, where; and to generate an input sample ^ L of x (tl • i)-L phase {ϋ interpolation (L phase interpolation), the digital filter contains ·: a first circuit used to generate, for each time t, a merge The culvert of the draining wave filter! The bank filter terms (bankfilter terms), whose output value changes between the previous time ti and the time t, the line generating row filter term includes at least two crossed symmetric row filter terms -A combination of: in the same phase: tk (please read the notes on the back before filling this page) Pk (i) x (-i) + PL-x +! (I) 'x (tk L -i) and L t- (L-K + l) _ (nli)) L Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs in the case of different phases: tk Pk (i) · x (i) +? L-k + i (il) · x (t- (L-K + l) L -1 L This paper scale adopts the Chinese National Standard (CNS) Μ specification (210X297mm). The scope of patent application tk Pk (n -i) · χ (L A8 B8 C8 D8-(ni)) + pL-κ + i (n-l'-i). X (L and the basis of the position filter: Min L filter row Any non-negative integer w, t = w · L + K; and the second circuit is used to sum up, for each time t, the row of filter items generated in the first circuit of raft i to produce The output value of the technical alignment filter that changes at the time t-1 and the time t. 2. As described in item 1 of the patent application scope, it includes the following steps: a Three circuits are used to sum up, and at each time t, η combine the output values of the filter to produce the frequency-increasing value. 3. The digital filter as described in item 1 of the patent application scope, for each At time t, j the first circuit produced the merger of the aforementioned changes η (please read the precautions on the back before filling in this page). Order -1 filter row to multiple row filter items. 2 Central Bureau of Economics employees Printed by the consumer cooperative 4. The digital filter as described in item 2 of the patent application, for the third circuit every L time t, the 2 combined wave filter output This paper scale is applicable to the Chinese national standard _ (CNS) A4 specification (210X297 mm). Patent scope A8 B8 C8 D8 t- The output value is added to generate the input sampling value x (-i) L An increased frequency value g (t). 5 · For the digital filter described in item 1 of the patent application scope, hold L for a fixed time t such that-+ 1 &lt; K &lt; L. The output value of the combined filter row changed is as follows: U-1 Σ 1 = 0 tk tk + 1 ⑴) · [χ (-i) + x (LL · "Dagger Li"-(nil))] r- L (please read the precautions on the back and then fill out this page), where η and L are Even number 6 · The digital filter as described in item 1 of the patent application scope is printed on the time when a consumer ’s consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, namely, I5_k III-the changed merger filter Row 2. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). The output value of the patent application range is as follows: yj (t) = pk (〇). [X (U = 2 L A8 B8 C8 D8 tk- n) + x (L Σ (Ρχ (1) + Pl-κ + x (il)) · [X (tk)] tk tk u L (please read the precautions on the back before filling this page) +2 · Pk (Ul) x (-U ^ l) L where n and L are even numbers, and L is set • a frequency multiplier with a combined wave bank, which is symmetrical by combining the parent fork of the frequency multiplier Row filter As a result, the aforementioned frequency upconverter includes: a first circuit for receiving a series of sampling values printed by Χ (幻 至 x (ti 乙 -in) printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. The paper scale is applicable to China National Standard Falcon (CNS) Α4 specification (210X297 mm) 4 β07 β θ ABCD In the patent application scope, L · is the phase number of the trial multiplier, η is each filter of the pre-merger multiplier The number of tap coefficients in the device bank, and 〇Si &lt; (η-l), and the sampling value used to output a series of applications combined to form a cross-symmetric filter bank; a second circuit * 'Rain to output a Series tap coefficients, which include a group that requires the tap coefficients of the aforementioned cross-symmetrical row filter term; and-a second circuit to receive the serial sampling value and the series of points The third circuit of the contact coefficient value is used to generate a multiplication of each sampling value of the series sampling value and the corresponding tap coefficient value of the 4. series tap coefficient value, and by Cheng. Multiplication Zhen, produces an increased frequency. 8. As the frequency increaser described in item 7 of the patent application, select the third circuit, and use ^ a self-technical product whose output value changes between the previous time tl and a current (current) time t. An output value of, and by adding the determined output value to the output value of at least one other merger filter, at least one of which asks t-Ι in the previous one and asks t in the present not Change the output value to determine the increase value. 9. The frequency increaser as described in Item 8 of the patent scope, in which the third circuit includes: Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) An accumulator that adds the multiplier to produce ^. The changed merge filter row output value, and is used to add the changed merge filter row output value to at least one unchanged The output value of the filter_wave filter; and, the paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210X297mm) A8 B8 • C8 D8. Please patent a frequency memory, used to store the aforementioned The output value of the combined filter bank generated by the accumulator described above does not change between time t and the next time t + 1. ίο. The frequency increaser as described in item 7 of the patent application scope, wherein the aforementioned first circuit includes: a random access memory for storing the aforementioned self-t-SL t-ί. x (-i ) To x (~ L ”—L” i-η); and an adder used to add the aforementioned continuous sampling values of the random access memory output to produce a combination of the aforementioned sampling values . 11. The frequency increaser as described in item 10 of the patent application scope, wherein the aforementioned first circuit includes: a plurality of counters, which are used to address the aforementioned random access memory, and to enable the The random access memory can continuously output pairs of samples according to the cross-symmetry filter term. 12. The frequency increaser as described in item 7 of the patent application Fan Gu, in which the aforementioned second circuit includes: Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) -A read-only memory, used to store the aforementioned tap coefficients and the tap-point coefficient combinations; and a counter * at each time, t is used to locate the aforementioned read-only memory so that the Only the memory outputs a series of tap point coefficient values of the merge filter row that changed the value at the previous time t and the time t. This paper 1 is applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm) A8 B8 C8 D8 Patent Application Fan Garden 13. As described in item 7 of the scope of the patent application frequency increaser, at each time t, the aforementioned The first circuit executes up to multiple phase 2 forces η, and among them, the aforementioned m three circuits execute up to 2 —Π -1 addition and-+ 1 multiplication to produce each merger that has 2 changes The output value of the filter bank. 14 · The frequency increaser as described in item 8 of the patent application scope, for every-time * |-L-t, the aforementioned third circuit is executed at most--1 merger 2 ~ 'waveform row output value To add the aforementioned frequency increase value. 15. A multiplier with a combined filter bank is formed by combining the cross-symmetrical bank filter items of the multiplier. This multiplier contains (please read the precautions on the back before filling in this Page) · —The paper printed by the Ministry of Economic Affairs Zhongshen Standard Falcon Bureau Employee Consumer Cooperative applies the Chinese national standard (CNS &gt; M specifications (210 &gt; &lt; 297mm). Patent scope A8 B8 C8 D8-a 丨 Wu Module core, used to receive-series t-1 tl from |-| -i) to x (LL • i_n) input sampling value Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy, where L is the aforementioned frequency increase The phase of the filter, n is the amount of tap coefficients in each filter bank before the frequency multiplier is combined, and 0 &lt; i &lt; n -1, and a series of corresponding tap coefficients, these systems馼 値 includes a combination of tap coefficients with a cross-symmetric row filter term combination. The aforementioned module core is also used to output in parallel. The combined filter row is The sampling value is formed by multiplying a corresponding tap coefficient value; and an addition tree circuit is used to generate a combined row output from the aforementioned row filter term output from the aforementioned module core The output value of the wave filter. 16. The frequency multiplier as described in item IS of the patent application scope further includes: a circuit for storing the output value of the aforementioned combined bank filter generated by the aforementioned adder circuit, and the combined bank filter The output values are added together to produce a multiplier sampling value. 17. The frequency multiplier as described in item 15 of the patent application scope, wherein the aforementioned module core includes a previous processing stage for generating a plurality of sampling values from the aforementioned input samples, including at least one corresponding to This sampling value combination of the aforementioned dividing point coefficients. (Please read the precautions on the back before filling in this page) The size of the revised paper is in accordance with the Chinese National Standard (CNS) A4 (210X297 mm). 6. Scope of Patent Application Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy. The frequency increaser described in item 17 of the patent scope, wherein the aforementioned previous processing stage includes: t -1 a shift register for storing the aforementioned from x (--1) —L — to x (- -in) input sampling value; -L-a plurality of multiplexers, including at least one multiplexer, used to receive the two aforementioned sampling values stored in the displacement register as input values; A plurality of adder circuits, including at least one adder circuit, for receiving a sample value stored in the shift register and a sample value output from the multiplexer, as Enter the value. _ 19. The frequency increaser as described in item 17 of the patent application scope, wherein the aforementioned module core further includes: a plurality of selector circuits for storing the aforementioned tap point coefficient values, and at specific cycles, The aforementioned tap coefficients stored therein are output in parallel; and, a plurality of multipliers executed in parallel, each multiplier sequentially selects one of the sampled values output from the previous processing stage, and selects from the aforementioned The output of the converter circuit is multiplied by a corresponding tap point coefficient value. (Please read the precautions on the back before filling in this page) The size of the revised paper applies to the Chinese National Standard (CNS) A4 (210X297mm) 6. Scope of patent application A8 B8 C8 D8 2 The frequency multiplier described above, wherein the aforementioned modular η group cores include an adder 2 η adder circuit for adding the sampling values together, and − + 1 2 for generating a combined filter row The multiplier circuit and the aforementioned addition tree circuit include approximately n-adder circuits. 2 21. The frequency multiplier as described in item 20 of the patent application scope, wherein the multiplier. The circuit is Booth ’s algorithm multiplier circuit, each circuit b of which includes an adder circuit, and wherein the frequency multiplier The circuit contains 2 nb approximate ((-+ 1) ·-+ n) adder circuits. 2 2 Printed by the Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm)