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TW202038434A - 積體電路結構及其形成方法 - Google Patents

積體電路結構及其形成方法 Download PDF

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Publication number
TW202038434A
TW202038434A TW108125360A TW108125360A TW202038434A TW 202038434 A TW202038434 A TW 202038434A TW 108125360 A TW108125360 A TW 108125360A TW 108125360 A TW108125360 A TW 108125360A TW 202038434 A TW202038434 A TW 202038434A
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Taiwan
Prior art keywords
die
memory die
semiconductor substrate
forming
dielectric layers
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TW108125360A
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English (en)
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TWI721499B (zh
Inventor
余振華
蔡仲豪
王垂堂
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台灣積體電路製造股份有限公司
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Abstract

一種方法，包含：使元件晶粒的半導體基底薄化以顯露延伸至半導體基底中的多個基底穿孔；以及形成第一重佈結構，包含在半導體基底上方形成多個第一介電層及在多個第一介電層中形成多個第一重佈線。多個第一重佈線電連接至多個基底穿孔。方法更包含將第一記憶體晶粒置放在第一重佈結構上方，及在第一重佈結構上方形成多個第一金屬支柱。多個第一金屬支柱電連接至多個第一重佈線。第一記憶體晶粒密封在第一密封體中。多個第二重佈線形成於多個第一金屬支柱及第一記憶體晶粒上方且電連接至多個第一金屬支柱及第一記憶體晶粒。

Description

晶粒堆疊及其形成方法
高效能計算（High-Performance Computing；HPC）系統通常包含接合至邏輯晶粒的高帶寬記憶體（High-Bandwidth-Memory；HBM）堆疊。HBM堆疊通常包含堆疊在一起的多個記憶體晶粒，其中較高的記憶體晶粒經由微型凸塊而經由焊料接合或金屬直接接合（metal direct bonding）而接合至下部記憶體晶粒。矽穿孔（Through-Silicon Vias；TSV）形成於記憶體晶粒中，使得上部晶粒可經由TSV電連接至邏輯晶粒。
以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。以下描述組件及配置的具體實例以簡化本發明。當然，這些組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外，本發明可在各種實例中重複圖式元件符號及/或字母。此重複是出於簡化及清楚之目的，且自身並不規定所論述之各種實施例及/或組態之間的關係。
此外，為易於描述，可在本文中使用空間相對術語，諸如「在...之下」、「在...下方」、「下部」、「上覆」、「上部」以及類似術語，以描述如圖式中所說明的一個元件或特徵與另一（一些）元件或特徵的關係。除圖式中所描繪的定向以外，空間相對術語意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
根據各種實施例提供包含記憶體晶粒的晶粒堆疊及其形成方法。根據一些實施例說明形成晶粒堆疊的中間階段。論述一些實施例的一些變化。貫穿各種視圖及說明性實施例，相同的圖式元件符號用以指代相同元件。根據本發明的一些實施例，晶粒堆疊包含接合至元件晶粒（諸如邏輯晶粒）的記憶體晶粒堆疊。代替在記憶體晶粒中形成矽穿孔（TSV），介電質穿孔形成於用於密封記憶體晶粒的密封體（諸如，模製化合物）中，且TSV用於將記憶體晶粒連接至邏輯晶粒。若TSV形成於記憶體晶粒的半導體基底中，則半導體基底將由於TSV與半導體基底之間的寄生電容而不利地引起對TSV之負載。根據本發明的一些實施例，介電質穿孔形成於介電質密封體中，且因此不存在負載。由於負載可引起信號衰減，因此藉由形成介電質穿孔，可避免信號衰減。
應理解，將相對於具體上下文（即包含接合至元件晶粒的記憶體晶粒的晶粒堆疊）描述實施例。所論述實施例的概念亦可應用於所述結構，且對其他結構的處理包含且不限於形成邏輯晶粒堆疊、IO晶粒堆疊或具有一或多個混合邏輯晶粒、一或多個IO晶粒、一或多個記憶體晶粒以及類似者的晶粒堆疊。本文中論述的實施例將提供使得能夠製備或使用本發明的主題的實例，且本領域的技術人員將易於理解在屬於不同實施例的所設想範疇內的情況下可進行的修改。以下圖式中的相同圖式元件符號及字符指代相同組件。儘管方法實施例可論述為以特定次序執行，但其他方法實施例可以任何邏輯次序執行。
圖1至圖8說明根據本發明的一些實施例的在晶粒堆疊的形成中的中間階段的橫截面圖。對應製程亦示意性地反映於圖33中所展示的製程流程300中。
參看圖1，提供載體30，且離型膜32形成於載體30上。載體30由透明材料形成，且可為玻璃載體、陶瓷載體、有機載體或類似者。載子30可具有圓形俯視圖形狀，且可具有矽晶圓之大小。離型膜32形成於載體30上方，且可由光-熱轉換（Light-To-Heat-Conversion；LTHC）塗佈材料形成。離型膜32可經由塗佈而塗覆至載體30上。根據本發明的一些實施例，離型膜32能夠在光/輻射（諸如雷射束）的加熱下分解，且因此可使載體30自形成於其上的結構釋放。
元件晶圓20置放於離型膜32上方。各別製程被示出為圖33中所展示的製程流程中的製程302。根據一些實施例，元件晶圓20可為包含多個邏輯晶粒20'的邏輯晶圓。相應地，元件晶圓20亦稱為邏輯晶圓，且元件晶粒20'在下文中亦稱為邏輯晶粒。根據替代實施例，元件晶圓20為另一類型的晶圓，諸如輸入-輸出晶圓、中介物（interposer）晶圓或類似者。根據本發明的一些實例實施例，元件晶粒20'為中央處理單元（Central Processing Unit；CPU）晶粒、圖形處理單元（Graphic Processing Unit；GPU）晶粒、行動應用程式晶粒、微控制單元（Micro Control Unit；MCU）晶粒、基頻（BaseBand；BB）晶粒、應用程式處理器（Application processor；AP）晶粒或類似者。元件晶粒20'包含半導體基底22及形成於半導體基底22上的內連線結構24。
內連線結構24示意性地說明於圖1中，且一些細節根據一些實例展示於圖26中。參考圖26，元件晶圓20包含基底22。根據一些實施例，基底22為半導體基底，其可包含或為結晶矽基底，但其可包括其他半導體材料，諸如矽鍺、矽碳或類似者。根據一些實施例，元件晶粒20'包含主動電路220，所述主動電路包含主動元件，諸如形成於半導體基底22的頂部表面處的電晶體（未展示）。根據元件晶圓20為中介物晶圓的一些實施例，在元件晶圓20的頂部表面處不存在電路。穿孔（有時稱為基底穿孔（Through-Substrate Vias；TSV））26可形成為延伸至基底22中。TSV 26在形成於矽基底中時有時亦稱為矽穿孔。TSV 26中的每一者可由隔離襯裡28環繞，所述隔離襯裡由諸如氧化矽、氮化矽或類似者的介電材料形成。隔離襯裡28將各別TSV 26與半導體基底22隔離。TSV 26及隔離襯裡28自半導體基底22的頂部表面延伸至半導體基底22的頂部表面與底部表面之間的中間位準。
內連線結構24形成於半導體基底22上方。內連線結構24可包含多個介電層224。金屬線228及通孔226形成於介電層224中，且電連接至TSV 26及主動電路220。根據一些實施例，介電層224由氧化矽、氮化矽、碳化矽、氮氧化矽、其組合及/或其多層形成。介電層224可包括由具有低介電常數（k）值的低k介電材料形成的一或多個金屬間介電質（Inter-Metal-Dielectric；IMD）層，所述k值可為例如低於約3.0或介於約2.5與約3.0之間的範圍內。
電連接器230形成於元件晶粒20'的頂部表面處。根據一些實施例，電連接器230包括金屬柱、金屬襯墊、金屬凸塊（有時稱為微凸塊）或類似者。電連接器230的材料可包含非焊料材料，其可包含且可為銅、鎳、鋁、金、其多層、其合金或類似者。電連接器230可經由一些其他導電特徵（未展示）及經由金屬線228及通孔226來電連接至積體電路（主動電路220），所述一些其他導電特徵包含但不限於鋁襯墊、後鈍化內連線（Post Passivation Interconnect；PPI）或類似者。此外，在電連接器230與金屬線228之間，可存在介電層，諸如低k介電層、鈍化（非低k）層、聚合物層或類似者。電連接器230可密封在介電層232中。根據本發明的一些實施例，介電層232為由例如聚苯并噁唑（polybenzoxazole；PBO）、聚醯亞胺、苯并環丁烯（benzocyclobutene；BCB）或類似者形成的聚合物層。
根據一些實施例，亦如圖26中所展示，代替具有電連接器230作為元件晶粒20'的頂部導電特徵，金屬支柱38可形成為在元件晶粒20'（元件晶圓20）的其餘部分上方突出。金屬支柱38展示為虛線的由此展示所述金屬支柱可形成於這一階段處或形成於圖3中所展示之步驟中。根據一些實施例，介電層232不形成，且金屬支柱38直接形成於金屬襯墊233上。當採用這些實施例時，跳過用於形成如圖3中所展示的金屬支柱38的製程。
貫穿描述，半導體基底22的具有主動電路220及內連線結構24的側面稱為半導體基底22的前側（或主動側），且相對側稱為半導體基底22的背側（或被動側）。此外，半導體基底22的前側亦稱為元件晶粒20'（及元件晶圓20）的前側（或主動側），且半導體基底22的背側亦稱為元件晶粒20'（元件晶圓20）的背側（或被動側）。
返回參看圖1，元件晶圓20以前側面向載體30的方式置放。內連線結構24的細節不展示，且參考圖26可見。接著，如圖2中所展示，基底22例如在化學機械研磨（Chemical Mechanical Polish；CMP）製程或機械研磨製程中經薄化。因此，TSV 26經暴露。各別製程在圖33中所展示的製程流程中說明為製程304。
圖3說明重佈結構41（41A）的形成，所述重佈結構包含介電層34（包含介電層34A及介電層34B）及重佈線（Redistribution Lines；RDL）36。各別製程被示出為圖33中所展示的製程流程中的製程306。根據一些實施例，介電層34由諸如PBO、聚醯亞胺或類似者的聚合物形成。形成方法包含塗佈呈可流動形式的介電層34，且接著固化對應介電層。根據本發明的替代性實施例，介電層34由諸如氮化矽、氧化矽、碳化矽、其多層、其組合或類似者的無機介電材料形成。形成方法可包含塗佈、化學氣相沈積（Chemical Vapor Deposition；CVD）、原子層沈積（Atomic Layer Deposition；ALD）、電漿增強型化學氣相沈積（Plasma-Enhanced Chemical Vapor Deposition；PECVD）或其他可適用的沈積法。介電層34可包含介電層34A及介電層34B，且更多介電層可依據佈線要求而形成。
RDL 36經形成為具有延伸至介電層34A中的通孔部分及位於介電層34A上方的跡線部分。形成製程可包含：使介電層34A圖案化以形成開口，其中TSV 26經由所述開口暴露；形成毯狀金屬晶種層（未展示）；形成鍍覆罩幕（諸如光阻）並使所述鍍覆罩幕圖案化以顯露金屬晶種層的一些部分；將RDL 36鍍覆在鍍覆罩幕中的開口中；去除鍍覆罩幕；以及蝕刻先前由鍍覆罩幕覆蓋的金屬晶種層的部分。根據本發明的一些實施例，金屬晶種層包含鈦層及鈦層上方的銅層。金屬晶種層的形成可包含例如PVD。根據本發明的一些實施例，鍍覆材料包含銅或銅合金。鍍覆可包含電化學鍍覆或無電極鍍覆。貫穿描述，將介電層34及形成於其中的RDL 36組合地稱為重佈結構41。
儘管說明RDL 36的一個層，但可形成RDL的更多層。隨後形成金屬支柱38。各別製程被示出為圖33中所展示的製程流程中的製程308。根據一些實施例，形成製程包含：使介電層34B圖案化以形成開口，其中RDL 36的一些襯墊部分經由開口暴露；形成毯狀金屬晶種層（未展示）；形成另一鍍覆罩幕（諸如光阻）並將所述另一鍍覆罩幕圖案化以顯露金屬晶種層的一些部分；將金屬支柱38鍍覆在鍍覆罩幕中的開口中；去除鍍覆罩幕；以及蝕刻先前由鍍覆罩幕覆蓋的金屬晶種層的部分以形成金屬支柱38。通孔40亦形成於與形成金屬支柱38相同的製程中，且延伸至介電層34B中。
圖4說明第一層（tier-1）記憶體晶粒42的置放。各別製程被示出為圖33中所展示的製程流程中的製程310。記憶體晶粒42可經由作為黏著膜的晶粒附接膜（Die-Attach Films；DAF）44附接至介電層34。在晶圓被切割為記憶體晶粒42之前，DAF 44可預附接於在其中具有多個記憶體晶粒42的各別晶圓上。記憶體晶粒42可包含具有與各別DAF 44實體接觸的背表面（面向下的表面）的半導體基底（240，圖28）。由於載體30處於晶圓級，雖然兩個記憶體晶粒42被說明為一群組，但多個相同記憶體群組置放在重佈結構41上方，其中所述群組中的每一者與元件晶粒20'中的一者交疊。此外，在群組中可存在更多記憶體晶粒，諸如4個、6個、8個或大於8個。
記憶體晶粒42的細節未展示於圖4中，且細節中的一些根據本發明的一些實施例而說明於圖28中。圖28除了記憶體晶粒42之外亦說明在後續段落中將論述的一些其他部分。記憶體晶粒42可包含半導體基底240、積體電路242，所述積體電路可包含主動元件，諸如電晶體、二極體或類似者。不存在穿透半導體基底240的穿孔。記憶體晶粒42可包含記憶體，諸如動態隨機存取記憶體（Dynamic Random Access Memories；DRAM）、靜態隨機存取記憶體（Static Random Access Memories；SRAM）或其他類型的記憶體。舉例而言，圖28說明可用於DRAM中的一些堆疊電容器。亦說明頂部金屬接觸件（Top metal contact；CTM）252及底部接觸金屬250。根據一些實施例，底部接觸金屬250用作位元線，且字元線256可嵌入於半導體基底240中。內連線結構244形成於基底240上方，且可包含介電層、金屬線、通孔以及類似者。介電層可包含低k介電層及/或非低k介電層。根據一些實施例，內連線結構244包含多個金屬層，諸如如圖28中所展示的金屬層M1、金屬層M2、金屬層M3及金屬層M4（或更多個金屬層）。由諸如未摻雜的矽酸鹽玻璃、氧化矽、氮化矽或其多層的非低k介電材料形成的鈍化層246形成於內連線結構244上方。可為金屬層M4的部分的金屬襯墊248形成於內連線結構244中的金屬線及通孔上方且電耦接至所述金屬線及通孔。舉例而言，金屬襯墊248可由鋁銅形成。可由銅、鎳、鈦或類似者形成的電連接器48可形成於金屬襯墊248上方且連接至所述金屬襯墊。可形成可由PBO、聚醯亞胺或類似者形成的介電層46以密封電連接器48。
返回參看圖4，記憶體晶粒42及金屬支柱38密封在密封體50中。各別製程被示出為圖33中所展示的製程流程中的製程312。密封體50填充相鄰金屬支柱38之間的間隙及金屬支柱38與記憶體晶粒42之間的間隙。密封體50可包含模製化合物、模製底部填充物、環氧樹脂及/或樹脂。密封體50的頂部表面高於電連接器48及金屬支柱38的頂部端。密封體50在由模製化合物形成時可包含基礎材料及基礎材料中的填充劑顆粒，所述基礎材料可為聚合物、樹脂、環氧樹脂或類似者。填充劑顆粒可為SiO2 、Al2 O3 、二氧化矽或類似者之介電顆粒，且可具有球形形狀。此外，球形填充劑顆粒可具有多個不同的直徑。
在後續步驟中，執行諸如CMP製程或機械研磨製程的平面化製程以薄化密封體50及記憶體晶粒42，直至暴露金屬支柱38及電連接器48為止。由於平面化製程，金屬支柱38的頂部端與電連接器48的頂部表面大體上齊平（共面），且與密封體50的頂部表面大體上共面。金屬支柱38在後續段落中由於其穿過密封體50而經替代地稱作穿孔38。
圖5說明另一重佈結構41（41B）的形成，所述另一重佈結構包含RDL 36及介電層34。各別製程被示出為圖33中所展示的製程流程中的製程314。為了區分重佈結構41的不同層級，在記憶體晶粒42之下的重佈結構41稱為（第一層）重佈結構41A，且上覆於記憶體晶粒42的重佈結構41稱為（第二層）重佈結構41B。此外，所說明的第一層記憶體晶粒42可識別為記憶體晶粒42A，且所說明的穿孔38可識別為（第一層）穿孔38A。
第二層重佈結構41B中的RDL 36電連接至穿孔38A及記憶體晶粒42中的電連接器48。相應地，穿孔38A將記憶體晶粒42電連接至元件晶粒20'。應理解，RDL 36經示意性地展示，而RDL 36並不使多個穿孔38及多個電連接器48電短接在一起。替代地，不同穿孔38可經由不同RDL 36連接至不同電連接器48。類似地，RDL 36並不使多個電連接器48電短接在一起。
圖6說明具有記憶體晶粒42（包含記憶體晶粒42B、記憶體晶粒42C以及記憶體晶粒42D）、穿孔38（包含穿孔38B、穿孔38C以及穿孔38D）以及重佈結構41（包含重佈結構41C、重佈結構41D以及重佈結構41E）等的更多層的形成/黏著。各別製程被示出為圖33中所展示的製程流程中的製程316。形成製程及對應材料參考圖3至圖5的論述可見，且因此不在本文中重複。記憶體晶粒42C及記憶體晶粒42D可與記憶體晶粒42A及記憶體晶粒42B一致或不同。在最終結果中，所有記憶體晶粒42以電氣方式及以信號方式連接至元件晶粒20'之下的各別部分。貫穿描述，離型膜32上方的特徵組合地統稱為重構晶圓54。
隨後例如藉由將雷射束投影於離型膜32上自載體30卸下重構晶圓54。離型膜32在雷射束的熱量下分解。所得重構晶圓54展示於圖7中。接著，如圖8中所展示，重佈結構52根據一些實施例形成於元件晶粒20'的內連線結構24上。各別製程被示出為圖33中所展示的製程流程中的製程318。根據替代實施例，可省略重佈結構52的形成。相應地，圖33中的製程318使用虛線來說明，以指示可執行或可不執行所述製程。在重佈結構52形成之前，覆蓋電連接器230的介電層232（圖26）被薄化，直至暴露電連接器230為止。不展示重佈結構52的細節。可例如使用用於形成重佈結構41的類似製程及材料來形成重佈結構52。重佈結構52包含介電層及介電層中的重佈線。電連接器55隨後形成於重佈結構52上，且經由重佈結構52電連接至元件晶粒20'。各別製程被示出為圖33中所展示的製程流程中的製程320。電連接器55可包含金屬柱、焊料區、凸塊下金屬（Under-Bump Metallurgies；UBM）以及類似者。
圖27說明根據一些實施例的在重佈結構52及電連接器55形成後的元件晶粒20'。不展示元件晶粒20'上方的重佈結構及記憶體晶粒堆疊。
返回參看圖8，重構晶圓54在晶粒切割製程中經單體化。各別製程被示出為圖33中所展示的製程流程中的製程322。舉例而言，鋸片可切割穿過元件晶粒20'之間的切割道以將重構晶圓54分離至多個相同封裝體54'中，所述多個相同封裝體各自具有如根據一些實例所說明的結構。封裝體54'可隨後接合至另一封裝組件（未展示），諸如中介物、封裝基底、印刷電路板或類似者，且例如底部填充物安置於所述封裝體與所述封裝組件之間。
在圖8中，穿孔38被繪示為形成由所有層級的記憶體晶粒42共用的通用信號通道。根據替代實施例，記憶體晶粒42中的每一者可具有一或多個專用信號通道，且穿孔38中的一些可連接至一個或一些（但並非全部）層級的記憶體晶粒42。
圖28說明根據一些實施例的圖8中的區域91的放大視圖。在放大視圖中，記憶體晶粒42密封在密封體50中，且金屬襯墊48的頂部表面與穿孔38的頂部表面共面。重佈結構41形成於記憶體晶粒42及穿孔38上方。儘管說明RDL 36的一個層，但可存在RDL 36的多個層（諸如兩個層、三個層或大於三個層）。
圖29至圖32說明根據本發明的一些實施例的圖8中的區域92的放大視圖。參考圖29，DAF 44將記憶體晶粒42黏著至重佈結構41中的頂部介電層34。RDL 36具有與金屬襯墊48的頂部表面接觸的通孔部分，所述金屬襯墊48位於介電層46中。介電層46可為可由聚醯亞胺、PBO或類似者形成的聚合物層。金屬襯墊248可為含鋁金屬襯墊，其可為根據一些實施例的鋁銅襯墊。替代地，金屬襯墊248可由諸如銅或銅合金的其他材料形成。鈍化層246可由氧化矽、氮化矽、其多層或其組合形成。
圖30說明根據替代實施例的圖8中的區域92的放大視圖。除了頂部金屬層（其為在其中包括金屬襯墊48的相同金屬層）亦用於佈線目的之外，這些實施例類似於圖29中所展示的實施例。替代地陳述，存在與金屬襯墊48處於相同層級且同時形成的金屬線，其中如示意性地所說明的金屬線可水平地延伸以佈線電信號。相應地，將金屬襯墊48定位於其中的金屬層視為記憶體晶粒42中的金屬層中的一者（出於佈線目的）。根據一些實施例，金屬襯墊48及對應通孔坐落於其上的金屬襯墊248為鋁襯墊或鋁銅襯墊。
圖31說明根據替代實施例的圖8中的區域92的放大視圖。除了RDL 36的兩個層被示出為一實例之外，這些實施例類似於圖29中所展示的實施例。
圖32說明根據替代實施例的圖8中的區域92的放大視圖。除了不存在直接形成於金屬襯墊48之下的鋁襯墊之外，這些實施例類似於圖29中所展示的實施例。確切而言，金屬襯墊48的通孔部分坐落在頂部金屬層（例如，M3）中的銅襯墊上。
在圖8中所展示的結構中，記憶體晶粒42不包括對應半導體基底中的基底穿孔。經由穿孔38得到上部層記憶體晶粒與元件晶粒20'的電連接。由於穿孔38形成於由介電材料形成的密封體50中，因此在穿孔38與密封體50之間（不同於TSV與半導體基底之間）不存在寄生電容，且所得封裝體亦不含可存在於矽穿孔中的負載。
圖9、圖10、圖11A以及圖11B說明根據替代實施例形成的封裝體54'。除非另外規定，否則這些實施例（及圖12至圖28中所展示的實施例）中的組件的材料及形成製程實質上與類似組件相同，所述類似組件由圖1至圖8中所展示的實施例中的類似圖式元件符號表示。關於圖9至圖28中所展示的組件的形成製程及材料的細節因此在圖1至圖8中所展示的實施例的論述中可見。
在以上所論述的實施例中，穿孔38形成於多個記憶體晶粒42之間，且TSV 26形成於元件晶粒20'的中間部分中。相應地，所得結構並不需要將TSV 26連接至穿孔38的長水平RDL。圖9說明與圖8中所展示的實施例類似的實施例，其例外之處在於在每一層中及在元件晶粒20'中的每一者上方可存在單個記憶體晶粒42，且穿孔38相應地形成於記憶體晶粒42的相對側上。根據一些實施例，TSV 26如所說明形成於元件晶粒20'的中間部分中。根據替代實施例，TSV 26可形成於區域57中，所述區域57接近元件晶粒20'的邊緣以減小重佈結構41A中的橫向分佈線的長度。
圖10說明與圖8中所展示的實施例類似的實施例，其不同之處在於穿孔38形成於多個記憶體晶粒42的相對側上而非多個記憶體晶粒42之間。根據一些實施例，TSV 26可經形成為接近元件晶粒20'的邊緣。代替將單個記憶體晶粒42置放在每一層中，單個記憶體晶粒的功能可分割成兩個記憶體晶粒，且記憶體晶粒42可接近元件晶粒20'的相對邊緣置放，使得水平RDL 36的長度可縮短。當元件晶粒20'具有比記憶體晶粒42的橫向大小大得多的橫向大小時，可應用這些實施例。類似地，TSV 26可形成於如所說明的元件晶粒20'的中間部分中，或可形成於區域57中，所述區域57接近元件晶粒20'的邊緣以減小重佈結構41A中的橫向分佈線36的長度。
圖11A說明與圖8中所展示的實施例類似的實施例，其不同之處在於在每一層中，置放多個記憶體封裝體43而非多個記憶體晶粒。多個記憶體封裝體43可與彼此一致或可彼此不同。多個記憶體封裝體43中的每一者可包含可與彼此相同或彼此不同的多個記憶體晶粒42'及多個記憶體晶粒42"。多個記憶體晶粒42'及多個記憶體晶粒42"中的每一者可密封在密封體58中，所述密封體例如可為模製化合物。密封體58亦可包含基礎材料及其中的填充劑顆粒，所述基礎材料諸如環氧樹脂、樹脂、聚合物或類似者。填充劑顆粒可為球形的，且可具有不同直徑。可形成與重佈結構41的形成方式類似的重佈結構41'於下伏記憶體晶粒42'及下伏記憶體晶粒42"上方，且電連接至所述下伏記憶體晶粒42'及下伏記憶體晶粒42"。重佈結構41'亦可包含其中的介電層及RDL。穿孔61可形成於上部的密封體58中，且將記憶體晶粒42'電連接至重佈結構41中的RDL 36。
圖11B說明與圖8中所展示的實施例類似的實施例，其不同之處在於記憶體晶粒42面向下而非面向上。相應地，多個記憶體晶粒42中的一些（諸如第三層及第四層晶粒）可與對應穿孔38交疊，所述對應穿孔將這些記憶體晶粒42連接至元件晶粒20'。此外，接合襯墊48中的每一者可與不同層級處的多個穿孔38交疊。一些記憶體晶粒（諸如第一層晶粒及第二層晶粒）的一些其他接合襯墊48仍可連接至水平RDL 36。
圖12至圖18說明根據替代實施例的晶粒堆疊的形成中的中間階段的橫截面圖。這些實施例與圖1至圖10、圖11A以及圖11B中所展示的實施例類似，其不同之處在於記憶體晶粒附接至元件晶粒的前側（而非背側）。參考圖12，提供包含元件晶粒20'的元件晶圓20。元件晶圓20的前側面向上展示，其中內連線結構24在半導體基底22及TSV 26上方。如展示內連線結構24的一些細節的圖26中所展示，在內連線結構24中，電連接器230由介電層232覆蓋。隨後執行平面化製程以薄化介電層232，直至暴露電連接器230為止。
接著，參考圖13，形成第一層重佈結構41及金屬支柱38。形成製程及材料實質上與前述實施例中所論述相同，且此處不重複。一些重佈線36可與如圖26中所展示的電連接器230中的一些實體接觸。
圖14說明第一層記憶體晶粒42的置放及密封體50中的記憶體晶粒42及金屬支柱38的密封。隨後對密封體50執行平面化製程以顯露金屬支柱38及電連接器48。接著，如圖15中所展示，形成第二層重佈結構41。在後續製程中，形成更多層的金屬支柱38、密封體50以及重佈結構41，且所得結構展示於圖16中，所述結構在下文中稱為重構晶圓54。
參考圖17，圖17與圖16相比較將重構晶圓54繪示為上下顛倒翻轉的，執行平面化製程，諸如CMP製程或機械研磨製程，直至暴露TSV 26為止。接著，如圖18中所展示，重佈結構52'形成於元件晶粒20'的半導體基底22上。可例如使用用於形成重佈結構41的類似製程及材料來形成重佈結構52'。重佈結構52'可包含介電層53A及介電層53B以及介電層53A及介電層53B中的重佈線59。根據本發明的一些實施例，介電層53A及介電層53B由諸如PBO或聚醯亞胺的聚合物形成。介電層53A可與半導體基底22及可能的TSV 26兩者實體接觸。電連接器55隨後形成於重佈結構52'上方，且經由重佈線59電連接至元件晶粒20'。電連接器55可包含金屬柱、焊料區、凸塊下金屬（UBM）及/或類似者。在後續製程中，重構晶圓54在單體化製程中被切割開至離散封裝體54'中，所述離散封裝體54'可隨後接合至額外封裝組件，諸如中介物、封裝基底、印刷電路板或類似者，其中底部填充物安置在其間。
圖19至圖25說明根據替代實施例的在記憶體晶粒堆疊及對應封裝體的形成中的中間階段的橫截面圖。這些實施例與如圖1至圖18中所展示的實施例類似，其不同之處在於記憶體晶粒堆疊首先經形成，且接著經由接合製程接合至邏輯晶粒，而非直接與邏輯晶粒/晶圓形成記憶體晶粒堆疊。
參考圖19，提供載體60，其中離型膜62形成於其上。逐層地形成包含多個記憶體晶粒42、多個金屬支柱38、密封體50以及多個重佈結構41的記憶體晶粒堆疊66。記憶體晶粒堆疊66亦可包含可由例如PBO或聚醯亞胺形成或包含PBO或聚醯亞胺的緩衝介電質39。記憶體晶粒堆疊66的形成製程及材料類似於參考圖1至圖8中所展示的實施例所論述的，且不在本文中重複。應理解，在第一層密封體50中，不形成穿孔38。接著，參考圖20，形成電連接器64以電耦接至RDL 36及穿孔38。電連接器64可包含金屬柱、金屬襯墊、焊料區及/或類似者。因此形成重構晶圓66。在後續製程中，在將重構晶圓66切割至多個記憶體堆疊66'中的單體化製程之前，自載體60剝離重構晶圓66。
圖21至圖25說明記憶體堆疊66'與元件晶圓20（及元件晶粒20'）的接合。參考圖21，元件晶圓20經由離型膜72置放於載體70上。元件晶圓20使其前側面向下，且因此內連線結構24位於半導體基底22與載體70之間。根據一些實施例，焊料區74（有時稱為預焊料區）預形成於中介物晶圓（元件晶圓20）上，且可形成於可由諸如PBO、聚醯亞胺或類似者的聚合物形成或包含所述聚合物的介電層76中。焊料區74可形成於如圖26中所展示的電連接器230上且有可能接觸所述電連接器。替代地，焊料區74可替換如圖26中所展示的電連接器230。
接著，如圖22中所展示，對半導體基底22執行諸如CMP製程或機械研磨製程的平面化製程以顯露TSV 26。元件晶圓20隨後經單體化以形成多個元件晶粒20'，其中多個元件晶粒20'中的一者展示於圖23中。圖23亦說明元件晶粒20'經由焊料區74接合至中介物晶圓78上。根據一些實施例，除了中介物晶圓78並不包含諸如主動元件的積體電路（主動電路220）於其中之外，中介物晶圓78具有與如圖26中所展示的元件晶圓20類似的結構。中介物晶圓78可包含或可不含諸如電阻器、電容器、電感器或類似者的被動元件於其中。TSV 82經形成為延伸至半導體基底81中，所述半導體基底81可為諸如矽基底的半導體基底。絕緣襯裡83環繞TSV 82。中介物晶圓78可包含其前部表面處的內連線結構80。內連線結構80的結構未被展示，且可類似於如圖26中所展示的內連線結構24。根據本發明的一些實施例，中介物晶圓78的前側（具有內連線結構80的側面）面向上，如圖23中所展示。根據本發明的替代性實施例，中介物晶圓78的前側面向下，且焊料區74可直接接合至TSV 82，所述TSV 82藉由研磨中介物晶圓78中的基底（半導體基底81）暴露。底部填充物84安置於元件晶粒20'與中介物晶圓78之間。儘管展示一個元件晶粒20'，但多個元件晶粒20'置放於中介物晶圓78上，例如是多個元件晶粒20'中的每一者與中介物晶圓78中的多個中介物晶粒中的一者交疊。
圖24說明多個記憶體堆疊66'各自接合至多個元件晶粒20'中的一者上。底部填充物84'安置於記憶體堆疊66'與元件晶粒20'之間。密封體86（例如，模製化合物、環氧樹脂或類似者）經密封在記憶體堆疊66'及元件晶粒20'上以形成重構晶圓88。密封體86亦可包含基礎材料及基礎材料中的球形填充物。
在後續製程中，研磨中介物晶圓78以薄化半導體基底81，從而暴露TSV 82。焊料區90（圖25）可形成於TSV 82上。替代地，另一重佈結構可經形成以將焊料區90連接至TSV 82。重構晶圓88可隨後被切割以形成多個封裝體88'。中介物晶圓78被切割為多個中介物晶粒，其中多個中介物晶粒78'中的一者展示於圖25中。圖25亦說明封裝體88'接合至封裝組件92，所述封裝組件可為封裝基底、框架、印刷電路板或類似者。
在以上所說明實施例中，根據本發明的一些實施例論述一些製程及特徵以形成三維（three-dimensional；3D）封裝體。亦可包含其他特徵及製程。舉例而言，可包含測試結構以輔助對3D封裝體或3DIC元件的驗證測試。測試結構可包含例如形成於重佈層中或基底上的測試襯墊，其允許測試3D封裝體或3DIC、使用探針及/或探測卡以及類似者。可對中間結構及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可結合併入有對良裸晶粒的中間驗證的測試方法而使用，以提高良率且降低成本。
本發明的實施例具有一些有利特徵。藉由直接從元件晶粒（諸如邏輯晶粒）及/或記憶體晶粒來形成重佈線，可經由從元件晶粒及記憶體晶粒直接形成的RDL來得到邏輯晶粒與記憶體晶粒之間的內連線，而不是經由金屬凸塊或焊料區。所得封裝體的高度由於移除金屬凸塊及焊料區而減小，從而允許在相同高度中堆疊更多記憶體晶粒。此外，穿孔形成於密封體材料中而非記憶體晶粒的半導體基底中。相應地，可消除由記憶體晶粒中的TSV與半導體基底之間的寄生電容所產生的負載。由於記憶體晶粒通常佔據比下伏元件晶粒更小的覆蓋面積，因此穿孔在密封體中的形成並不引起封裝體的佔據面積增大。
根據本發明的一些實施例，方法包含形成記憶體晶粒堆疊，包括：將第一記憶體晶粒置放在下部介電層上；在下部介電層上方形成多個第一金屬支柱；將第一記憶體晶粒密封在第一密封體中；形成第一重佈結構，包括在第一密封體上方形成多個第一介電層及在多個第一介電層中形成多個第一重佈線，其中多個第一重佈線電連接至多個第一金屬支柱及第一記憶體晶粒；將第二記憶體晶粒置放在第一重佈結構上方；在第一重佈結構上方形成多個第二金屬支柱，其中多個第二金屬支柱電連接至多個第一金屬支柱；將第二記憶體晶粒密封在第二密封體中；形成第二重佈結構，包括在第二密封體上方形成多個第二介電層及在多個第二介電層中形成多個第二重佈線，其中多個第二重佈線電連接至多個第二金屬支柱及第二記憶體晶粒。在一實施例中，第一記憶體晶粒及第二記憶體晶粒不含基底穿孔於其中。在一實施例中，第一記憶體晶粒經由第一黏著膜置放於下部介電層上，且第二記憶體晶粒經由第二黏著膜置放於第二重佈結構上。在一實施例中，方法更包含形成額外重佈結構，包括：在元件晶粒上方形成多個額外介電層，所述元件晶粒包括半導體基底及半導體基底中的多個穿孔，其中下部介電層包括於多個額外介電層中；以及在多個額外介電層中形成多個額外重佈線，其中多個額外重佈線電連接至多個穿孔。在一實施例中，額外重佈結構形成於元件晶粒的前側上，且元件晶粒包括前側上的多個電連接器及密封多個電連接器於其中的第一聚合物層。在一實施例中，形成額外重佈結構包括使第一聚合物層薄化以顯露多個電連接器；以及將第二聚合物層安置在多個電連接器及第一聚合物層上方且使所述第二聚合物層與所述多個電連接器及所述第一聚合物層接觸，其中第二聚合物層包括於多個額外介電層中。在一實施例中，額外重佈結構形成於元件晶粒的背側上。在一實施例中，形成額外重佈結構包括使元件晶粒的半導體基底薄化以顯露多個穿孔；以及將聚合物層安置在多個穿孔及半導體基底兩者上方且使所述聚合物層與所述多個穿孔及所述半導體基底接觸，其中聚合物層包括於多個額外介電層中。在一實施例中，方法更包含將記憶體晶粒堆疊接合在元件晶粒上，其中多個第一金屬支柱電連接至元件晶粒的半導體基底中的多個穿孔。
根據本發明的一些實施例，方法包含使元件晶粒的半導體基底薄化以顯露延伸至半導體基底中的多個基底穿孔；形成第一重佈結構，包括在半導體基底上方形成多個第一介電層及在多個第一介電層中形成多個第一重佈線，其中多個第一重佈線電連接至多個基底穿孔；將第一記憶體晶粒置放在第一重佈結構上方；在第一重佈結構上方形成多個第一金屬支柱，其中多個第一金屬支柱電連接至多個第一重佈線；將第一記憶體晶粒密封在第一密封體中；以及形成多個第二重佈線，所述多個第二重佈線在多個第一金屬支柱及第一記憶體晶粒上方且電連接至所述多個第一金屬支柱及所述第一記憶體晶粒。在一實施例中，方法更包含形成第二重佈結構，包括在第一密封體上方形成多個第二介電層，其中多個第二重佈線位於多個第二介電層中。在一實施例中，多個第一介電層中的底部介電層與半導體基底及多個基底穿孔實體接觸。在一實施例中，多個基底穿孔由多個絕緣襯裡與半導體基底分隔開，且底部介電層進一步與多個絕緣襯裡接觸。在一實施例中，形成多個第一介電層包括形成多個聚合物層。在一實施例中，第一記憶體晶粒包括額外半導體基底，且第一記憶體晶粒在額外半導體基底中不含穿孔。
根據本發明的一些實施例，積體電路結構包含元件晶粒。元件晶粒包含：半導體基底；多個基底穿孔，穿透半導體基底；以及內連線結構，位於半導體基底的一側上；第一重佈結構，位於元件晶粒上方且包括多個第一介電層；以及多個第一重佈線，位於多個第一介電層中，其中多個第一重佈線電耦接至元件晶粒。積體電路結構更包含：第一記憶體晶粒，位於第一重佈結構上方；多個第一金屬支柱，位於第一重佈結構上方，其中多個第一金屬支柱電連接至多個第一重佈線；第一密封體，密封第一記憶體晶粒及多個第一金屬支柱於其中；以及多個第二重佈線，位於第一密封體上方且電連接至第一記憶體晶粒及多個第一金屬支柱。在一實施例中，第一記憶體晶粒包括額外半導體基底，且第一記憶體晶粒不含穿透額外半導體基底的穿孔。在一實施例中，積體電路結構更包含第二記憶體晶粒，所述第二記憶體晶粒位於多個第一金屬支柱上方且電連接至多個第一金屬支柱。在一實施例中，多個第一介電層包括與元件晶粒的半導體基底實體接觸的底部介電層。在一實施例中，內連線結構位於第一重佈結構與半導體基底之間。
前文概述若干實施例的特徵以使得本領域的技術人員可更佳地理解本發明的態樣。本領域的技術人員應理解，其可易於使用本發明作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。本領域的技術人員亦應認識到，這些等效構造並不脫離本發明的精神及範疇，且本領域的技術人員可在不脫離本發明的精神及範疇的情況下在本文中作出各種改變、替代及更改。
20:元件晶圓 20':邏輯晶粒 22、81、240:半導體基底 24、80、244:內連線結構 26、38A、38B、38C、38D、82:穿孔 28:隔離襯裡 30、60、70:載體 32、62、72:離型膜 33、248:金屬襯墊 34、34A、34B、46、53A、53B、76、224、232:介電層 36、59:重佈線 38:金屬支柱/穿孔 40、226:通孔 41、41'、41A、41B、41C、41D、41E、52、52':重佈結構 42、42'、42"、42A、42B、42C、42D:記憶體晶粒 44:晶粒附接膜 48、55、64、230:電連接器 50、58、86:密封體 54、66、88:重構晶圓 54'、88':封裝體 57、91、92:區域 66:記憶體晶粒堆疊 66':記憶體堆疊 74、90:焊料區 78:中介物晶圓 78':中介物晶粒 83:絕緣襯裡 84、84':底部填充物 92:封裝組件 220:主動電路 228:金屬線 242:積體電路 246:鈍化層 250:底部接觸金屬 252:頂部金屬接觸件 256:字元線 300:製程流程 302、304、306、308、310、312、314、316、318、320、322:製程 M1、M2、M3、M4:金屬層
當結合附圖閱讀時，自以下詳細描述最佳地理解本發明之態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。實際上，可出於論述清楚起見，任意地增加或減小各種特徵之尺寸。 圖1至圖8說明根據一些實施例的在形成附接至邏輯晶粒的前側的記憶體晶粒堆疊中的中間階段的橫截面圖。 圖9、圖10、圖11A以及圖11B說明根據一些實施例的晶粒堆疊的橫截面圖。 圖12至圖18說明根據一些實施例的在形成附接至邏輯晶粒的背側的記憶體晶粒堆疊中的中間階段的橫截面圖。 圖19至圖25說明根據一些實施例的在形成附接至邏輯晶粒的背側的記憶體晶粒堆疊中的中間階段的橫截面圖。 圖26及圖27說明根據一些實施例的在形成與矽穿孔（TSV）的連接之前及之後的實例邏輯晶粒的橫截面圖。 圖28說明根據一些實施例的實例記憶體晶粒的橫截面圖。 圖29至圖32說明根據一些實施例的圖8中的結構的部分的一些細節。 圖33說明根據一些實施例的用於形成晶粒堆疊的製程流程。
300:製程流程
302、304、306、308、310、312、314、316、318、320、322:製程

Claims (20)

  1. 一種形成積體電路結構的方法，包括： 形成記憶體晶粒堆疊，包括： 將第一記憶體晶粒置放在下部介電層上； 在所述下部介電層上方形成多個第一金屬支柱； 將所述第一記憶體晶粒密封在第一密封體中； 形成第一重佈結構，包括： 在所述第一密封體上方形成多個第一介電層；以及 在所述多個第一介電層中形成多個第一重佈線，其中所述多個第一重佈線電連接至所述多個第一金屬支柱及所述第一記憶體晶粒； 將第二記憶體晶粒置放在所述第一重佈結構上方； 在所述第一重佈結構上方形成多個第二金屬支柱，其中所述多個第二金屬支柱電連接至所述多個第一金屬支柱； 將所述第二記憶體晶粒密封在第二密封體中； 形成第二重佈結構，包括： 在所述第二密封體上方形成多個第二介電層；以及 在所述多個第二介電層中形成多個第二重佈線，其中所述多個第二重佈線電連接至所述多個第二金屬支柱及所述第二記憶體晶粒。
  2. 如申請專利範圍第1項所述的方法，其中所述第一記憶體晶粒及所述第二記憶體晶粒不含基底穿孔於其中。
  3. 如申請專利範圍第1項所述的方法，其中所述第一記憶體晶粒經由第一黏著膜置放於所述下部介電層上，且所述第二記憶體晶粒經由第二黏著膜置放於所述第二重佈結構上。
  4. 如申請專利範圍第1項所述的方法，更包括： 形成額外重佈結構，包括： 在元件晶粒上方形成多個額外介電層，所述元件晶粒包括半導體基底及所述半導體基底中的多個穿孔，其中所述下部介電層包括於所述多個額外介電層中；以及 在所述多個額外介電層中形成多個額外重佈線，其中所述多個額外重佈線電連接至所述多個穿孔。
  5. 如申請專利範圍第4項所述的方法，其中所述額外重佈結構形成於所述元件晶粒的前側上，且所述元件晶粒包括所述前側上的多個電連接器及密封所述多個電連接器於其中的第一聚合物層。
  6. 如申請專利範圍第5項所述的方法，其中所述形成所述額外重佈結構包括： 使所述第一聚合物層薄化以顯露所述多個電連接器；以及 將第二聚合物層安置在所述多個電連接器及所述第一聚合物層上方且使所述第二聚合物層與所述多個電連接器及所述第一聚合物層接觸，其中所述第二聚合物層包括於所述多個額外介電層中。
  7. 如申請專利範圍第4項所述的方法，其中所述額外重佈結構形成於所述元件晶粒的背側上。
  8. 如申請專利範圍第7項所述的方法，其中所述形成所述額外重佈結構包括： 使所述元件晶粒的所述半導體基底薄化以顯露所述多個穿孔；以及 將聚合物層安置在所述多個穿孔及所述半導體基底兩者上方且接觸所述多個穿孔及所述半導體基底兩者，其中所述聚合物層包括於所述多個額外介電層中。
  9. 如申請專利範圍第1項所述的方法，更包括： 將所述記憶體晶粒堆疊接合在元件晶粒上，其中所述多個第一金屬支柱電連接至所述元件晶粒的半導體基底中的多個穿孔。
  10. 一種形成積體電路結構的方法，包括： 使元件晶粒的半導體基底薄化以顯露多個基底穿孔，所述多個基底穿孔延伸至所述半導體基底中； 形成第一重佈結構，包括： 在所述半導體基底上方形成多個第一介電層；以及 在所述多個第一介電層中形成多個第一重佈線，其中所述多個第一重佈線電連接至所述多個基底穿孔； 將第一記憶體晶粒置放在所述第一重佈結構上方； 在所述第一重佈結構上方形成多個第一金屬支柱，其中所述多個第一金屬支柱電連接至所述多個第一重佈線； 將所述第一記憶體晶粒密封在第一密封體中；以及 形成多個第二重佈線，所述多個第二重佈線在所述多個第一金屬支柱及所述第一記憶體晶粒上方且電連接至所述多個第一金屬支柱及所述第一記憶體晶粒。
  11. 如申請專利範圍第10項所述的方法，更包括形成第二重佈結構，包括： 在所述第一密封體上方形成多個第二介電層，其中所述多個第二重佈線位於所述多個第二介電層中。
  12. 如申請專利範圍第10項所述的方法，其中所述多個第一介電層中的底部介電層與所述半導體基底及所述多個基底穿孔實體接觸。
  13. 如申請專利範圍第12項所述的方法，其中所述多個基底穿孔由多個絕緣襯裡與所述半導體基底分隔開，且所述底部介電層進一步與所述多個絕緣襯裡接觸。
  14. 如申請專利範圍第10項所述的方法，其中所述形成所述多個第一介電層包括形成多個聚合物層。
  15. 如申請專利範圍第10項所述的方法，其中所述第一記憶體晶粒包括額外半導體基底，且所述第一記憶體晶粒在所述額外半導體基底中不含穿孔。
  16. 一種積體電路結構，包括： 元件晶粒，包括： 半導體基底； 多個基底穿孔，穿透所述半導體基底；以及 內連線結構，位於所述半導體基底的一側上； 第一重佈結構，位於所述元件晶粒上方且包括： 多個第一介電層；以及 多個第一重佈線，位於所述多個第一介電層中，其中所述多個第一重佈線電耦接至所述元件晶粒； 第一記憶體晶粒，位於所述第一重佈結構上方； 多個第一金屬支柱，位於所述第一重佈結構上方，其中所述多個第一金屬支柱電連接至所述多個第一重佈線； 第一密封體，密封所述第一記憶體晶粒及所述多個第一金屬支柱於其中；以及 多個第二重佈線，位於所述第一密封體上方且電連接至所述多個第一金屬支柱。
  17. 如申請專利範圍第16項所述的積體電路結構，其中所述第一記憶體晶粒包括額外半導體基底，且所述第一記憶體晶粒不含穿透所述額外半導體基底的穿孔。
  18. 如申請專利範圍第16項所述的積體電路結構，更包括在所述多個第一金屬支柱上方且電連接至所述多個第一金屬支柱的第二記憶體晶粒。
  19. 如申請專利範圍第16項所述的積體電路結構，其中所述多個第一介電層包括底部介電層，所述底部介電層與所述元件晶粒的所述半導體基底實體接觸。
  20. 如申請專利範圍第16項所述的積體電路結構，其中所述內連線結構位於所述第一重佈結構與所述半導體基底之間。
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