TW201924294A - Baseband processing apparatus and baseband processing method based on orthogonal frequency-division multiplexing - Google Patents

Abstract

Embodiments relate to a baseband processing apparatus and a baseband processing method based on orthogonal frequency-division multiplexing (OFDM). In order to solve the problem of high PAPR in OFDM systems, the baseband processing apparatus and method generate a plurality of data with different peak to average power ratios (PAPRs) by modifying bit representations of the frozen bits used by a polar encoder, and then select the one of the plurality of data with the smallest PAPR as an OFDM signal.

Description

Fundamental frequency processing device and fundamental frequency processing method based on orthogonal frequency division multiplexing

Embodiments of the present invention are directed to a baseband processing apparatus and a baseband processing method. More specifically, embodiments of the present invention relate to a baseband processing apparatus and a baseband processing method based on orthogonal frequency division multiplexing.

Orthogonal frequency-division multiplexing (OFDM) is a technique for modulating and demodulating digital data over multiple carrier frequencies. In summary, the core of orthogonal frequency division multiplexing is to divide an entire frequency band into a plurality of mutually orthogonal sub-carriers, and let the data be transmitted in parallel on these sub-carriers, thereby improving Data transfer rate and bandwidth usage efficiency.

In the conventional orthogonal frequency division multiplexing system, since the orthogonal frequency division multiplexing signal is a linear sum of a plurality of subcarrier signals, the amplitude of the orthogonal frequency division multiplexing signal greatly changes, which makes Cross-frequency multiplexed signals typically have a Peak to Average Power Ratio (PAPR). Once the peak-to-average power ratio of the orthogonal frequency division multiplexing signal is too high, the operation of the conventional orthogonal frequency division multiplexing system will be affected. For example, the orthogonal frequency division multiplexing signal of the peak-to-average power ratio can seriously affect the amplification efficiency and digital position of the power amplifier. The conversion quality of a digital to analog converter (DAC) or an analog to digital converter (ADC).

In view of this, in the technical field to which the present invention pertains, how to improve the peak-to-average power ratio of the orthogonal frequency division multiplexing signal will be an urgent problem to be solved.

In order to solve at least the above problems, an embodiment of the present invention provides a baseband processing apparatus based on orthogonal frequency division multiplexing, and the baseband processing apparatus may include a polarization code encoder, a modulator, and a reverse A discrete Fourier transform converter with a controller. The modulator can be electrically connected to the polarization code encoder, the inverse discrete Fourier converter can be electrically connected to the modulator, and the controller can be electrically connected to the inverse discrete Fourier converter connection. The polarization code encoder may be configured to encode the plurality of first data into a plurality of second data, each of the plurality of first data comprising an information byte and a frozen byte, the complex information byte having the same The bit length and the same bit indicate that the complex frozen byte has the same bit length, each of the complex frozen bytes includes a specific frozen byte, and the complex specific frozen bit Groups have the same bit length but different bit representations. The modulator can be used to convert the plural second data into a plurality of third data. The inverse discrete Fourier transform converter can be used to convert the complex third data into a plurality of fourth data. The controller may be configured to calculate a peak-to-average power ratio of each of the plurality of fourth materials, and select a fourth data candidate from the fourth plurality of data, the fourth data candidate corresponding to the complex peak The smallest of the power ratios.

In order to solve at least the above problems, an embodiment of the present invention further provides a method for processing a base frequency based on orthogonal frequency division multiplexing, and the method may include the following steps: using a polarization code encoder to convert the first number The data is encoded as a plurality of second data, wherein the plural Each of the first data includes an information byte and a frozen byte, the complex information byte having the same bit length and the same bit representation, the complex frozen byte having the same bit Length, each of the plurality of frozen byte groups includes a specific frozen byte, and the complex specific frozen byte has the same bit length but has a different bit representation; by a modulator, Converting the plurality of second data into a plurality of third data; converting the complex third data into a plurality of fourth data by an inverse discrete Fourier transform converter; and calculating, by a controller, the fourth data in the plurality A peak-to-peak power ratio of each of the four data candidates is selected from the fourth plurality of data, wherein the fourth data candidate corresponds to the smallest of the complex peak-to-average power ratios.

In an embodiment of the present invention, a plurality of bits corresponding to different peak-to-average power ratios may be generated by changing a bit representation of a frozen bit used by a polarization code encoder, and a peak-to-average power ratio is selected from the minimum. The data is used as an orthogonal frequency division multiplexing signal. Compared with the conventional orthogonal frequency division multiplexing system, the peak-to-average power ratio of the orthogonal frequency division multiplexing signal cannot be adjusted. In the embodiment of the present invention, the peak of the orthogonal frequency division multiplexing signal is averaged. The power ratio can be adjusted. Therefore, the embodiment of the present invention can effectively solve the problem that the orthogonal frequency division multiplexing signal has a peak-average power ratio.

The Summary of the Invention is not intended to be an overview of all embodiments of the present invention, but merely to exemplarily describe the core concepts of the present invention, the problems that can be solved by the present invention, the means that can be employed, and the achievable efficiencies. A general understanding of the invention is generally provided by the skilled person.

As follows:

1‧‧‧ fundamental frequency processing device

11‧‧‧Polarization code encoder

13‧‧‧Transformer

15‧‧‧Inverse Discrete Fourier Transform Converter

17‧‧‧ Controller

19‧‧‧Interlacer

D1‧‧‧First Information

D2‧‧‧Second information

D3‧‧‧ Third Information

D4‧‧‧ Fourth Information

FRZ‧‧‧ frozen bit

IN‧‧‧ digital input signal

OUT‧‧‧ digital output signal

X1~X8‧‧‧ bit of the first data

Y1~Y8‧‧‧ bits of the second data

4‧‧‧Base frequency processing method based on orthogonal frequency division multiplexing

401~407‧‧‧Steps

FIG. 1A illustrates a baseband processing apparatus based on orthogonal frequency division multiplexing in one or more embodiments of the present invention.

FIG. 1B illustrates another baseband processing apparatus based on orthogonal frequency division multiplexing in one or more embodiments of the present invention.

2A-2B is a schematic diagram of the operation of a polarization code encoder in one or more embodiments of the present invention.

Figure 3 is a schematic illustration of the operation of another polarization code encoder in one or more embodiments of the present invention.

Figure 4 illustrates a method of processing a baseband based on orthogonal frequency division multiplexing in one or more embodiments of the present invention.

The various embodiments described below are not intended to limit the scope of the invention, which can be implemented in the environments, applications, structures, procedures or steps described. In the drawings, elements that are not directly related to the present invention have been omitted. In the drawings, the dimensions of the various components and the ratios between the components are merely exemplary and are not intended to limit the invention. Unless otherwise stated, the same (or similar) element symbols may correspond to the same (or similar) elements in the following.

FIG. 1A illustrates a baseband processing apparatus 1A based on orthogonal frequency division multiplexing in one or more embodiments of the present invention, and FIG. 1B illustrates another example in one or more embodiments of the present invention. A baseband processing apparatus 1B based on orthogonal frequency division multiplexing. 1A and 1B are merely illustrative of the embodiments of the present invention and are not intended to limit the present invention. The baseband processing device 1A and the baseband processing device 1B are each applicable to an orthogonal frequency division multiplexing transmitter and are used for performing various digital signal processing, such as, but not limited to, coding, modulation, and Reverse Inverse Discrete Fourier Transform (IDFT) and the like. The baseband processing device 1A and the baseband processing device 1B can each be integrated into a system on chip (SoC), but not limited thereto.

Referring to FIGS. 1A and 1B, the baseband processing device 1A and the baseband processing device 1B can each basically include a polarization code encoder 11, a modulator 13, an inverse discrete Fourier transform converter 15, and a first The controller 17 is coupled to an interleaver 19. The polarization code encoder 11 is electrically connected to the modulator 13, the modulator 13 is electrically connected to the inverse discrete Fourier transform converter 15, and the inverse discrete Fourier transform converter 15 is electrically connected to the controller 17. . In the fundamental frequency processing device 1A, the interleaver 19 is electrically connected to the polarization code encoder 11. In the fundamental frequency processing device 1B, the interleaver 19 is electrically connected to the polarization code encoder 11 and the controller 17.

In some embodiments, the baseband processing device 1A and the baseband processing device 1B may each include other components/modules to perform other digital signal processing required by the orthogonal frequency division multiplexing transmitter. The connections between the respective blocks shown in FIG. 1A and FIG. 1B may be direct connections (ie, not connected to each other via elements of a specific function), or may be indirect connections (ie, via specific functional elements to each other). connection).

The Polar Code Encoder 11 is an encoder using a polarization code. The polarization code is a type of forward error correction code and is a code that can theoretically reach the Shannon Limit. Polarization codes can achieve Channel Polarization, and channel polarization can make each channel exhibit different reliability. As the code length of the polarization code increases, the channel capacity of some channels will approach one (no noise channel), and the channel capacity of some channels will approach zero (pure noise channel). The message transmitted on the perfect channel will theoretically reach the Shannon limit. Polarization code encoder 11 It is realized by an integrated circuit (IC), but is not limited thereto.

The modulator 13 is a digital modulator. According to different modulation requirements, the modulator 13 can have different structures, such as but not limited to: Amplitude Shift Keying (ASK) structure, Frequency Shift Keying (FSK) structure, phase position. Phase Shift Keying (PSK) structure and Quadrature Amplitude Modulation (QAM) structure. The modulator 13 can be implemented via an integrated circuit, but is not limited thereto.

The inverse discrete Fourier transform converter 15 is a converter capable of implementing inverse discrete Fourier transform. The inverse discrete Fourier transform converter 15 may have different structures according to different conversion requirements, such as but not limited to: a general inverse discrete Fourier transform structure and an inverse fast Fourier transform that is easily implemented on a hardware (Inverse Fast Fourier Transform) , IFFT) structure. The inverse discrete Fourier transform converter 15 can be implemented by an integrated circuit, but is not limited thereto.

The controller 17 is a microprocessor and a microcontroller. A microprocessor or microcontroller is a programmable special integrated circuit that has functions of operation, storage, output/input, etc., and can accept and process various coding instructions, thereby performing various logic operations and arithmetic operations, and outputting The corresponding operation result.

Interleaver 19 is a device for interleaving and/or rearranging a plurality of input bits to produce interleaved and/or rearranged output bits.

Referring to FIGS. 1A and 1B, the baseband processing device 1A and the baseband processing device 1B each can receive a digital input signal IN and output a digital output signal OUT. Polarization code encoding The device 11 can be used to encode the plurality of first data D1 into the second data D2. Each first data D1 is represented by a string of binary bits, and may include an information byte (ie, an information bit entrained by the digital input signal IN) and a frozen byte (ie, by a pole) The frozen bit FRZ) determined and/or generated by the code encoder 11 or the controller 17. The complex information byte is derived from the information bits carried by the same digit input signal IN, and thus has the same bit length and the same bit representation. The complex frozen byte has the same bit length but has a different bit representation. In the baseband processing apparatus 1A, the interleaver 19 can be used to interleave the information bits entrained by the digital input signal IN and each set of frozen bits FRZ determined and/or generated by the polarization code encoder 11 and/or Or rearrange) to generate a plurality of first data D1. In the baseband processing device 1B, the interleaver 19 can be used to interleave and/or rearrange the information bits entrained by the digital input signal IN and each group of frozen bits FRZ determined/generated by the controller 17. To generate a plurality of first data D1. The interleaver 19 can interleave the information bits carried by the digital input signal IN and each group of frozen bits determined/generated by the polarization code encoder 11 or the controller 17 according to the bit reliability. Rearrange to generate the first data D1.

The same bit length of the complex number of the complex frozen byte may depend on a coding rate employed by the polarization code encoder 11. The coding rate can be defined as the ratio of the bit length of the information byte included in the first data D1 to the bit length of the first data D1. For example, if the coding rate used by the polarization code encoder 11 is 1/2, and the information byte of the first data D1 (ie, the information bit data carried by the digital input signal IN) is located, The length of the element is four (ie, four bits), and the polarization code encoder 11 will form the frozen byte included in the first data D1 with four frozen bits, so that the bits of the information byte The ratio of the length to the bit length of the first data D1 is equal to 1/2.

Each of the plurality of frozen byte groups can include a particular frozen byte group, and the particular frozen byte groups have the same bit length but different bit representations. In some embodiments, the bit length of a particular frozen byte may be equal to the bit length of the frozen byte, ie, all bits of the frozen byte may be selected to form a particular frozen byte. In some embodiments, the bit length of a particular frozen byte may be less than the bit length of the frozen byte, that is, only a portion of the bits of the frozen byte may be selected to form a particular frozen byte. For example, if the bit length of the frozen byte is four (ie, four bits), the bit length of the specific frozen byte included therein may be one, two, three, or four, that is, One, two, three or four of the four bits can be selected to form a particular frozen byte.

The complex specific frozen byte has a different bit representation. For example, since each bit can be represented as zero or one, if the bit length of the frozen byte is four (ie, four bits), it depends on the bit length of the specific frozen byte. (may be one, two, three or four bits), a specific frozen byte can have up to two fourth powers (ie 16) different bit representations. The number of first data D1 encoded by the polarization code encoder 11 may depend on the number of specific frozen byte groups having different bit representations, and thus may be expressed as the rth power of two, where r is a positive integer and is equivalent The length of the bit in a particular frozen byte. For example, if the bit length of a specific frozen byte is three, the number of specific frozen bytes having different bit representations and the number of first data D1 encoded by the polarization code encoder 11 are both eight. (that is, the third party of the second).

Under the architecture of the polarization code, once the bit length of the frozen byte is determined, the bit reliability of each bit contained in the frozen byte is determined. Thus, in some embodiments, the polarization code encoder 11 can determine the complex particular frozen byte from the complex frozen byte, respectively, based on the bit reliability of the frozen bit. For example, if the bit is frozen The bit length of the group is four (ie, four bits), and the bit length of the specific frozen byte is determined to be two (ie, two bits), then the polarization code encoder 11 can be from the four Two of the most reliable bits are selected from the bits to form a specific frozen byte.

Under the architecture of the polarization code, once the bit length of the frozen byte is determined, the bit position of each bit contained in the frozen byte is also determined. Thus, in some embodiments, the polarization code encoder 11 may determine the complex particular frozen byte from the complex frozen byte, respectively, based on the bit position of the frozen bit. For example, if the frozen byte has a bit length of four (ie, four bits) and the bit length of the specific frozen byte is determined to be two (ie, two bits), then the polarization The code encoder 11 can select two bits at the preset bit positions (for example, the first and second bit positions) to form a specific frozen byte according to the bit positions of the four bits.

In some embodiments, the polarization code encoder 11 may also determine the complex specific frozen byte from the complex frozen byte, respectively, based on a manner of randomly selecting the bit. For example, if the frozen byte has a bit length of four (ie, four bits) and the bit length of the specific frozen byte is determined to be two (ie, two bits), then the polarization The code encoder 11 can randomly select two bits from the four bits to form a specific frozen byte.

2A-2B is a schematic diagram of the operation of a polarization code encoder in one or more embodiments of the present invention. The contents of the 2A-2B diagram are only for the purpose of illustrating the embodiments of the present invention and are not intended to limit the invention. Figure 2A-2B shows two first data D1 with different bit representations and their corresponding two second data D2. Referring to FIG. 2A-2B, it is assumed that the information bits of the two first data D1 (ie, the information bit data carried by the digital input signal IN) have a bit length of four (ie, four information). Bit) and because of the encoding used by the polarization code encoder 11 The rate is 1/2, so the bit lengths of the frozen bytes included in the two first data D1 are also four (ie, four frozen bits). Therefore, the bit lengths of the two first data D1 are all eight (ie, eight bits), and are represented by bit X1, bit X2, ..., bit X8, respectively. The bit length of the second data D2 is also eight (ie, eight bits), and is represented by the bit Y1, the bit Y2, ..., the bit Y8, respectively. In addition, the four information bits of the information byte (ie, the information bit data carried by the digital input signal IN) included in the two first data D1 are respectively the bit X4, the bit X6, and the bit X7. And the bit X8 is represented, and the four frozen bits of the frozen byte included in the two first data D1 are represented by the bit X1, the bit X2, the bit X3, and the bit X5.

The polarization code encoder 11 may be based on the bit reliability of the above four frozen bits (ie, bit X1, bit X2, bit X3, and bit X5), bit position, or based on a randomly selected bit. In the meta mode, one or more specific frozen bits are selected from the above four frozen bits. For convenience of explanation, in FIG. 2A-2B, it is assumed that the bit length of a specific frozen byte is one (ie, one specific frozen bit), and the specific frozen bit is represented by bit X5.

In the two first data D1, the values of the bit X4, the bit X6, the bit X7, and the bit X8 (ie, the information bit) are all "1", and the bit X1, the bit X2 The value of bit X3 (ie, the above-mentioned frozen bit) is "0". Further, in Fig. 2A, the value of the bit X5 (i.e., the specific frozen bit) is "0", and in the second block BB, the value of the bit X5 (i.e., the specific frozen bit) is " 1". In this case, as shown in FIG. 2A, the bits of the eight bits X1-X8 included in the first data D1 can be represented as “0 0 0 0 0 1 1 1”, and the second data D2 is included. The bits of the eight bits Y1-Y8 can be represented as "0 0 0 1 0 0 0 1". In addition, as shown in FIG. 2B, the bits of the eight bits X1-X8 included in the first data D1 can be represented as “0 0 0 0 1 1 1 1”, and the eight bits included in the second data D2 are included. The bit of the bit Y1-Y8 can be expressed as "1 0 0 1 1 0 0 1". Therefore, it is only necessary to change the value of a single bit (e.g., bit X5) to generate two second data D2 having different bit representations.

Figure 3 is a schematic illustration of the operation of another polarization code encoder in one or more embodiments of the present invention. The illustrations in Figure 3 are for illustrative purposes only and are not intended to limit the invention. Referring to Fig. 3, the polarization code encoder 11 is a systematic polarization code encoder which performs the same encoding procedure twice, and in the second encoding procedure, the value of the frozen bit is heavy. Set (eg, reset to zero), such that the bit representation of the information bits (eg, bit X4, bit X6, bit X7, and bit X8) in the first data D1 and the second data D2 The bit representation of the information bit (eg, bit Y4, bit Y6, bit Y7, and bit Y8) is the same. Therefore, regardless of how the bit representation of the frozen bit (eg, bit X1, bit X2, bit X3, and bit X5) in the first data D1 changes, the information bit in the second data D2 (eg, The bit representation of bit Y4, bit Y6, bit Y7, and bit Y8) is still the same as the information bit in the first data D1 (for example, bit X4, bit X6, bit X7, and The bits of bit X8) represent the same. In other words, in FIG. 3, if the bit representation of the frozen bit (ie, bit X1, bit X2, bit X3, and bit X5) in the first data D1 changes, the second data D2 At most, only four bits (ie, bit Y1, bit Y2, bit Y3, and bit Y5) will change in value.

Returning to FIGS. 1A and 1B, the modulator 13 can be used every time the polarization code encoder 11 encodes a first data D1 into a second data D2 (ie, a code word). The second data D2 is converted into the third data D3. The constellation point of the modulator is M=2 ^m , which means that every m bits of the second data D2 will be converted into a symbol of the third data D3.

After the modulator 13 adjusts the second data D2 to the third data D3, the inverse discrete Fourier transform converter 15 can be used to convert the third data D3 (frequency domain data) into the fourth data D4 (time domain data). Taking the inverse fast Fourier transform as an example, the inverse discrete Fourier transform converter 15 can convert the third data D3 into the fourth data D4 according to the following equation: Where d _k is the third data D3, x _n is the fourth data D4, n represents a discrete time point, and N represents the length of the fourth data D4.

In some embodiments, each time the modulator 13 converts a second data D2 into a third data D3, the inverse discrete Fourier transform converter 15 converts the third data D3 to the fourth according to equation (1). Information D4. In some embodiments, in order to reduce the amount of computation of the inverse discrete Fourier transform, the inverse discrete Fourier transform converter 15 may be based on a one-bit conversion lookup table (Lookup Table, in addition to the first third data D3). LUT) to convert the other pen third data D3 into the fourth data D4.

Specifically, since a group of specific frozen byte groups has a total of r bits, if a group of specific frozen bytes of the first data D1 is b bits (b is a positive integer less than or equal to r) The bit representation changes (e.g., from zero to one), which may result in a corresponding change in the p bits of the second data D2 and the q symbols of the third data D3. In the process of pre-establishing the bit conversion lookup table, each of the p bits in the second data D2 may be changed to establish a set of bit conversion lookup table inputs, and then passed through the modulator 13 and the inverse discrete The Fourier transform converter 15 can obtain a corresponding set of bit conversion lookup table outputs, all bit conversion lookup table inputs and all corresponding bit conversion lookup table outputs to form a bit conversion lookup table. For example, if the second data D2 has p bits, it will be changed by the b bits of the first data D1, and the p bits of the second data D2 fall at the j _i position (i is from All positive integers between 1 and p, including 1 and p). For each i, j _i will be the first bit position of the second data D2 is set to indicate "1" and other bits represent the position are set to "0" can be obtained by the above-mentioned set of conversion bit input look-up table, Then, the p group bit conversion lookup table input is respectively passed through the modulator 13 and the inverse discrete Fourier transform converter 15 to obtain the corresponding p group bit conversion lookup table output, and the bit conversion lookup table is established. . Alternatively, the bit conversion lookup table may be pre-established by any external computer device or processor and stored in the baseband processing device 1A or the baseband processing device 1B.

After the bit length of the first data D1 is determined, the coding structure of the polarization code encoder 11 is also determined, and once the coding structure of the polarization code encoder 11 is determined, the fundamental frequency processing device 1A and the fundamental frequency processing are determined. Each of the devices 1B can know in advance which value of the bit in the first data D1 changes, which one or which of the second data D2 will be changed. Taking the 2A-2B diagram as an example, as the value of the bit X5 (ie, the specific frozen bit) changes, the values of the bit Y1 and the bit Y5 in the second data D2 will change, but The other bits in the second data D2 will not change. Therefore, based on the linear characteristic of the inverse discrete Fourier transform, in addition to the first fourth data D4 having to pass the inverse discrete Fourier transform, the inverse discrete Fourier transform converter 15 only needs to have the first fourth data D4 with the current The other fourth data D4 can be obtained by adding one or more bits of the fourth data D4 to be calculated to be changed in the bit conversion lookup table.

Each time the inverse discrete Fourier transform converter 15 converts the third data D3 into the fourth data D4, the controller 17 can calculate a peak-to-average power ratio of the fourth data D4 according to the following equation: Where PAPR is the peak-to-average power ratio, x _n is the fourth data D4, max(| x _n | ² ) is the maximum power of the fourth data D4, and E (| x _n | ² ) is the fourth data D4 Average power.

After calculating the peak-to-average power ratio of all the fourth data D4, the controller 17 may select a fourth data candidate as the digital output signal OUT from the fourth data, wherein the fourth data candidate corresponds to all peaks. The smallest of the power ratios.

The subsequent processing for the digital output signal OUT selected by the controller 17 is the same as that for the general orthogonal frequency division multiplexing transmitter. For example, the digital output signal OUT can be converted into an analog signal, and then the analog signal is subjected to intermediate frequency conversion and radio frequency conversion, and then an orthogonal frequency division multiplexing signal is transmitted to an orthogonal frequency division multiplexing receiver.

The orthogonal frequency division multiplexing signal transmitted by the orthogonal frequency division multiplexing transmitter including the baseband processing device 1A or the baseband processing device 1B can be received and processed using a conventional orthogonal frequency division multiplexing receiver without A specially designed orthogonal frequency division multiplexing receiver is required for reception and processing. For example, a conventional orthogonal frequency division multiplexing receiver first converts the received orthogonal frequency division multiplexing signal into a digital fundamental frequency signal, and then performs Fourier Transform on the digital base frequency signal, and then Demodulation is performed, and finally decoding (Decoding). Corresponding to the polarization code encoder 11 using a polarization code, in the decoding stage, a Successive Cancellation (SC) decoder or a SC-List decoder can be used. The basic core of the splicing elimination decoder and the splicing elimination list decoder is to reserve one or several decoding paths with the highest probability during the decoding process as the output of the decoder.

It should be noted that, in the embodiment of the present invention, the orthogonal frequency division multiplexing receiver combined with the orthogonal frequency division multiplexing transmitter including the baseband processing device 1A or the baseband processing device 1B does not need auxiliary information. (Side Information), for example, information such as a bit position and a bit representation of a specific frozen byte in the first data D1, and the above-mentioned digital baseband signal can be decoded. Therefore, different The orthogonal frequency division multiplexing transmitter using Selected Mapping (SLM) must additionally transmit r bits (ie, auxiliary information), including orthogonal frequency division of the baseband processing device 1A or the baseband processing device 1B. The multiplex transmitter does not need to transmit the auxiliary information. It should be noted that, in the first data D1, the frozen bit included in the frozen byte is not the information bit data carried by the digital input signal IN, so the frozen bit included in the frozen byte is changed. The bit representation basically does not affect the operation and effect of the connection elimination decoder and the connection elimination list decoder.

Figure 4 illustrates a method of processing a baseband based on orthogonal frequency division multiplexing in one or more embodiments of the present invention. The contents shown in Figure 4 are for illustrative purposes only and are not intended to limit the invention. Referring to FIG. 4, the basic frequency processing method 4 based on orthogonal frequency division multiplexing may include the following steps: encoding, by a polarization code encoder, a plurality of first data into a plurality of second data, wherein the plurality of first data Each of the plurality of information bytes includes a same bit length and the same bit representation, the complex frozen byte having the same bit length, the complex number Each of the frozen bytes includes a particular frozen byte, and the complex specific frozen byte has the same bit length but has a different bit representation (labeled as step 401); Translating the plurality of second data into a plurality of third data (labeled as step 403); converting the complex third data into a plurality of fourth data (indicated as step 405) by an inverse discrete Fourier transform converter; And calculating, by a controller, a peak-to-average power ratio of each of the plurality of fourth materials, and selecting a fourth data candidate from the fourth plurality of data, wherein the fourth data candidate corresponds to the The smallest of the complex peak-to-average power ratios (labeled as step 407).

In some embodiments, the orthogonal frequency division multiplexing based baseband processing method 4 may further comprise the step of: from the polarization code encoder, respectively, from the complex freeze bit according to the bit reliability of the freeze bit The plural specific freeze byte is determined in the tuple.

In some embodiments, the orthogonal frequency division multiplexing based baseband processing method 4 may further include the step of: by the polarization code encoder, respectively, freeze the bit from the complex bit according to the bit position of the frozen bit The group determines the plural specific frozen byte.

In some embodiments, the orthogonal frequency division multiplexing based baseband processing method 4 may further include the step of: by the polarization code encoder, respectively, freeze the bit from the complex number based on a randomly selected bit manner The group determines the plural specific frozen byte.

In some embodiments, step 405 can include converting, by the inverse discrete Fourier transform converter, the complex third data to the complex fourth data based on a one-bit conversion lookup table.

In some embodiments, step 405 can include converting, by the inverse discrete Fourier transform converter, the complex third data to the complex fourth data based on a one-bit conversion lookup table. Additionally, in these embodiments, the polarization code encoder is a systematic polarization code encoder.

In some embodiments, with respect to the orthogonal frequency division multiplexing based fundamental frequency processing method 4, wherein the number of the plurality of first data is 2 r-th power, and r is a positive integer.

In some embodiments, with respect to the orthogonal frequency division multiplexing based fundamental frequency processing method 4, wherein the complex bit length of the complex frozen byte group depends on a coding rate.

In some embodiments, the fundamental frequency processing method 4 based on orthogonal frequency division multiplexing may be implemented on the baseband processing device 1A or the baseband processing device 1B. Due to the technical field of the invention Those skilled in the art can clearly understand all the corresponding steps of the fundamental frequency processing method 4 based on the orthogonal frequency division multiplexing according to the above description of the baseband processing apparatus 1A and the baseband processing apparatus 1B, so that details are relevant. This will not be repeated here.

The embodiments disclosed above are not intended to limit the invention. Arrangements for changes or equivalences that can be easily accomplished by those of ordinary skill in the art to which the invention pertains are within the scope of the invention. The scope of the invention is defined by the scope of the claims.

Claims (16)

A fundamental frequency processing device based on orthogonal frequency division multiplexing includes: a polarization code encoder for encoding a plurality of first data into a plurality of second data, each of the plurality of first data comprising a information bit a tuple and a frozen byte, the complex information byte having the same bit length and the same bit representation, the complex frozen byte having the same bit length, each of the complex frozen bytes A set includes a specific frozen byte, and the complex specific frozen byte has the same bit length but has a different bit representation; a modulator is electrically connected to the polarization code encoder and used to Transforming the plurality of second data into a plurality of third data; an inverse discrete Fourier transform converter electrically connected to the modulator and configured to convert the complex third data into a plurality of fourth data; and a control And electrically coupled to the inverse discrete Fourier transform converter, and configured to calculate a peak-to-average power ratio of each of the plurality of fourth data, and select a fourth data candidate from the fourth plurality of data, The fourth candidate information corresponds to the plurality of peak to average power ratio of the smallest. The baseband processing device of claim 1, wherein the polarization code encoder is further configured to determine the complex specific frozen byte from the plurality of frozen byte groups according to bit reliability of the frozen bit. The baseband processing device of claim 1, wherein the polarization code encoder is further configured to determine the complex specific frozen byte from the plurality of frozen byte groups according to the bit position of the frozen bit. The baseband processing device of claim 1, wherein the polarization code encoder is further configured to determine the complex specific frozen byte from the plurality of frozen byte groups based on a randomly selected bit. The baseband processing device of claim 1, wherein the inverse discrete Fourier transform converter converts the complex third data into the complex fourth data based on a one-bit conversion lookup table. The baseband processing device of claim 1, wherein the polarization code encoder is a systematic polarization code encoder. The baseband processing device according to claim 1, wherein the number of the plurality of first materials is 2 r-th power, and r is a positive integer. The baseband processing device of claim 1, wherein the complex bit length of the complex frozen byte group depends on a coding rate. A method for processing a fundamental frequency based on orthogonal frequency division multiplexing includes the following steps: encoding, by a polarization code encoder, a plurality of first data into a plurality of second data, wherein each of the plurality of first data includes one An information byte and a frozen byte, the complex information byte having the same bit length and the same bit representation, the complex frozen byte having the same bit length, the complex frozen byte Each group includes a specific frozen byte, and the complex specific frozen byte has the same bit length but has a different bit representation; the second data is converted into a complex number by a modulator a third data; converting the complex third data into a plurality of fourth data by an inverse discrete Fourier transform converter; and calculating, by a controller, a peak-to-average power ratio of each of the plurality of fourth data, and A fourth data candidate is selected from the fourth plurality of data, wherein the fourth data candidate corresponds to the smallest one of the complex peak-to-average power ratios. The method for processing a baseband according to claim 9, further comprising the step of: determining, by the polarization code encoder, the plurality of specific freeze bits from the plurality of frozen byte groups according to bit reliability of the freeze bit Tuple. The method for processing a baseband according to claim 9, further comprising the step of: determining, by the polarization code encoder, the plurality of specific freeze bits from the plurality of frozen byte groups according to the bit position of the freeze bit group. The method for processing a baseband according to claim 9, further comprising the step of: determining, by the polarization code encoder, the plurality of specific freeze bits from the plurality of frozen byte groups based on a manner of randomly selecting bits group. The baseband processing method of claim 9, wherein the step of converting the complex third data into the complex fourth data comprises: using the inverse discrete Fourier transform converter, based on a one-bit conversion lookup table The plural third data is converted into the fourth data. The method of processing a baseband according to claim 9, wherein the polarization code encoder is a systematic polarization code encoder. The method of processing a baseband according to claim 9, wherein the number of the plurality of first data is 2 r-th power, and r is a positive integer. The baseband processing method of claim 9, wherein the complex bit length of the complex frozen byte group depends on a coding rate.