TW201807417A - Sensor circuit - Google Patents

Abstract

Provided is a sensor circuit that has little possibility of being accidentally put into a test mode in response to an external input of noise or the like. The sensor circuit includes a clock generation circuit configured to output a control signal that is used to control intermittent operation to a physical quantity detection unit, and to output a sampling signal in a sleep period, a potential detection circuit configured to detect a potential at an output terminal and to output a detection signal, and a clock control circuit configured to output a mode switching signal that is a command to switch the clock generation circuit to a test mode, when a given signal pattern is detected in data that is obtained by sampling the detection signal based on the sampling signal.

Description

Sensing circuit

The present invention relates to a sensor circuit, and more particularly, to a sensor circuit with a test circuit.

Conventionally, a sensing circuit that detects various physical quantities is mounted in an electronic device and is effectively used. The sensing circuit is sometimes mounted in a three-terminal package including a power terminal, a ground terminal, and an output terminal. In this way, many sensing circuits mounted in packages with a small number of terminals cannot be provided with dedicated terminals for switching to a test mode. Therefore, in a sensing circuit with a small number of terminals, the output terminal is also used as a test terminal.

A conventional sensing circuit includes a first inversion unit that outputs a potential level of an output signal of a detection unit, and a second inversion unit that inverts a potential level of an output signal of the detection unit and outputs the output level to an output. A terminal; and a mode switching circuit that switches to a test mode according to a potential level of the first inversion portion and a potential level of the second inversion portion. In addition, by forcibly inputting a voltage from the output terminal, the mode switching circuit detects a potential state (same potential) that would not normally occur and switches to a test mode (for example, refer to Patent Document 1).

Prior Art Literature Patent Literature Patent Literature 1: Japanese Patent Laid-Open No. 2009-31225

[Problems to be Solved by the Invention] However, the magnetic sensing circuit of Patent Document 1 may accidentally switch to a test mode for an unexpected external input such as noise overlapping from an output terminal. Moreover, when the load capacity of the output terminal is large, there may be a delay in the change in the potential level of the conventional output terminal corresponding to the detection result, and it may be unexpectedly switched to the test mode.

[Means for Solving the Problem] The sensing circuit of the present invention includes: a clock generating circuit that outputs a control signal for controlling an intermittent operation to a physical quantity detecting section and outputs a sampling signal during a rest period; a potential detecting circuit that detects an output terminal And a clock control circuit that outputs a mode that switches the clock generation circuit to a test mode when a predetermined signal pattern (Pattern) is detected in the data obtained by sampling the detection signal based on the sampling signal. Switch signals.

[Effects of the Invention] According to the sensing circuit of the present invention, the possibility of erroneous switching to the test mode is low, and stable operation can be realized.

In the following, the sensing circuit of the present invention is described by taking a magnetic switch having a binary output as a result of comparing the output voltage of a Hall element with a reference voltage as an example.

<First Embodiment>

FIG. 1 is a block diagram of a sensing circuit 100 according to the first embodiment.

The sensing circuit 100 according to the first embodiment includes a physical quantity detection unit 10, a clock generation circuit 20, an output driver 30, and a potential detection circuit 40 and a clock control circuit 50.

The physical quantity detection unit 10 outputs physical quantity detection signals 12 at two different potential levels according to the applied physical quantity.

The input of the output driver 30 is connected to the output of the physical quantity detection unit 10, and the output is connected to the output terminal 31. The output driver 30 inverts the potential level of the physical quantity detection signal 12 of the physical quantity detection unit 10 and outputs an output logic signal 32 of the sensing circuit 100 to the output terminal 31.

An input of the potential detection circuit 40 is connected to the output terminal 31, and a binary potential detection signal 41 is output based on the potential of the output terminal 31.

The clock generation circuit 20 outputs a control signal 21 for controlling the detection operation to the physical quantity detection unit 10, and outputs a sampling signal 22 to the clock control circuit 50 during the rest period.

The clock control circuit 50 inputs a potential detection signal 41, a sampling signal 22 and a physical quantity detection signal 12, and outputs a mode switching signal 51 to the clock generation circuit 20.

The physical quantity detection unit 10 is a magnetic switch that detects the magnetic field of the S pole or the N pole, and switches the potential level of the physical quantity detection signal 12 in accordance with the magnitude of the magnetic flux density applied from the outside. In addition, the physical quantity detection unit 10 performs an intermittent operation including an operation period in which a physical quantity is detected or canceled based on a control signal 21, and an inactivity period during which the operation current of the internal circuit is increased. Partially blocked period.

The clock control circuit 50 samples the potential detection signal 41 in synchronization with the sampling signal 22 and holds the data in a shift register or the like. When the clock control circuit 50 obtains a predetermined signal pattern (here, LHHL, HLLH) from the potential detection signal 41, it switches the mode switching signal 51 to a level corresponding to the test mode. The clock control circuit 50 switches the mode switching signal 51 to a level corresponding to the normal mode when the physical quantity detection signal 12 changes.

The physical quantity detection unit 10 is configured to perform, for example, the operations described below.

The physical quantity detection unit 10 compares the output voltage of the Hall element with the reference voltage when the control signal 21 is at the H level and becomes a rest period. When the control signal 21 is at the L level, it becomes a rest period. If the value is, the physical quantity detection signal 12 at the L level is output, and if it is larger than a predetermined value, the physical quantity detection signal 12 at the H level is output.

The output driver 30 is, for example, a complementary metal-oxide semiconductor (Complementary Metal-Oxide-Semiconductor, CMOS) driver. When the applied physical quantity is small, for example, when the input physical quantity detection signal 12 is at the L level, the Nch driver is turned off and the Pch driver is turned on, and the output logic signal 32 at the H level is output to the output terminal 31. When the applied physical quantity is large, for example, when the input physical quantity detection signal 12 is at the H level, the Nch driver is turned on and the Pch driver is turned off, and the output logic signal 32 at the L level is output to the output terminal 31.

The potential detection circuit 40 includes, for example, a Schmitt trigger circuit, a comparator including a differential pair and a reference voltage circuit, and the like. The potential detection circuit 40 outputs an H-level potential detection signal 41 when the potential of the output terminal 31 is H level, and outputs an L-level potential detection signal 41 when the potential of the output terminal 31 is L level.

Next, an operation of the sensing circuit 100 according to the first embodiment will be described.

FIG. 2 is a timing chart showing the operation of the sensing circuit 100 according to the first embodiment.

In FIG. 2, the magnetic flux density applied to the sensing circuit 100 is Bin, the voltage of the physical quantity detection signal 12 is V12, the voltage of the output terminal 31 is V31, and the voltage of the potential detection signal 41 is V41. The voltage of the control signal 21 is V21, the voltage of the sampling signal 22 is V22, and the voltage of the mode switching signal 51 is V51. The threshold value of the physical quantity detected by the physical quantity detection unit 10 is set to BOP, and the threshold value of the release detection is set to BRP.

For the sensing circuit 100, a magnetic flux density Bin shown in a timing chart is applied. The magnetic flux density Bin is lower than the threshold BRP before time t0. Therefore, the physical quantity detection signal 12 is at the L level, and the voltages at the output terminal 31 and the potential detection signal 41 are at the H level.

Before the sensing circuit 100 is in the rest period during the normal operation before time t1, the mode switching signal 51 maintains the L level, and the sampling signal 22 is output from the clock generating circuit 20. In the sampling signal 22 before time t1, the clock control circuit 50 continuously maintains the H level of the potential detection signal 41, and thus maintains the normal operation (the mode switching signal 51 is at the L level). Here, the clock control circuit 50 reads the potential of the potential detection signal 41 on the rising edge of the sampling signal 22.

The period from time t1 to time t2 of the sensing circuit 100 is an operation period during normal operation. The clock generation circuit 20 sets the control signal 21 to the H level. The physical quantity detection unit 10 detects that the magnetic flux density Bin is higher than the threshold BOP during the operation period and performs signal processing. When the control signal 21 becomes the L level, the physical quantity detection signal 12 is set to the H level. In response to this, the voltages of the output terminal 31 and the potential detection signal 41 become the L level. In addition, when the sensing circuit 100 is in the rest period during the normal operation again, the mode switching signal 51 maintains the L level, and the sampling signal 22 is output from the clock generation circuit 20.

The clock control circuit 50 reads the L level of the potential detection signal 41 based on the sampling signal 22 at time t3.

Here, when the H level is forcibly input to the output terminal 31 externally from time t4 to time t7, the clock control circuit 50 reads the H position of the potential detection signal 41 based on the sampling signal 22 at time t5 and t6. At the time t8, the L level of the potential detection signal 41 is read based on the sampling signal 22.

Therefore, since the input signal pattern is at the level of LHHL, the clock control circuit 50 determines that it is a test mode input signal during the period from time t8 to time t9, switches from the normal operation to the test mode, and outputs the H level mode Switching signal 51.

The sensing circuit 100 maintains the test mode until time t10, and when the physical quantity detection unit 10 detects that the magnetic flux density Bin is less than or equal to the release threshold BRP, the physical quantity detection signal 12 changes to the L level. The clock control circuit 50 receives a change in the physical quantity detection signal 12 to the L level, switches from the test mode to a normal operation, and outputs a mode switching signal 51 at the L level.

As described above, the sensing circuit 100 according to the present embodiment has a structure in which a voltage having a predetermined signal pattern is forcibly input to the output terminal 31 from the outside during a rest period during normal operation, and the voltage is detected by detecting the voltage. The normal operation is switched to the test mode, and the level of the physical quantity detection signal 12 is changed, and the test mode is switched to the normal operation. Therefore, the probability that the sensing circuit 100 according to the present embodiment is switched to the test mode by mistake is low, and stable operation can be realized.

In addition, in the timing chart of FIG. 2, the description is switched from the state where the magnetic flux density Bin is higher than the detection threshold BOP to the test mode, and when the magnetic flux density Bin is lower than the release threshold BRP, the switching is started The same goes for the test mode. At this time, the output terminal 31 can be forcibly set to the L level potential and the signal pattern is set to HLLH, whereby the clock control circuit 50 determines that it is a test mode input signal and switches from the normal operation to the test mode.

In addition, although the signal pattern is described as LHHL or HLLH, it is not limited to this, and it may be a more complex signal pattern or a shorter signal pattern.

<Second Embodiment>

FIG. 3 is a block diagram of a sensing circuit 200 according to the second embodiment. In the sensing circuit 200 according to the second embodiment, a counter 60 is added to the sensing circuit 100 of FIG. 1, and the counter 60 counts time-out times. In addition, the clock control circuit 50 in the second embodiment adopts a configuration in which the timeout signal 61 output from the counter 60 is received. Other structures are the same as those of the sensing circuit 100 of FIG. 1, and therefore the same components are denoted by the same reference numerals, and descriptions thereof are omitted.

The counter 60 receives a potential detection signal 41 output from the potential detection circuit 40 and outputs a time-out signal 61 to the clock control circuit 50. When the clock control circuit 50 receives the H-level time-out signal 61, it masks the sampling signal 22.

Next, an operation of the sensing circuit 200 according to the second embodiment will be described.

FIG. 4 is a timing chart showing the operation of the sensing circuit 200 according to the second embodiment.

In FIG. 4, the voltage of the time-out signal 61 is V61. The same operations as those in the timing chart of FIG. 2 will be omitted.

At time t1, the physical quantity detection signal 12 becomes the H level, and the voltage of the output terminal 31 becomes the L level.

At time t2, when noise from the outside is superimposed on the output terminal 31, as shown in the figure, the voltage V31 changes, and a potential detection signal 41 of the H level is output. Therefore, the clock control circuit 50 reads the H level of the potential detection signal 41 based on the sampling signal 22.

The counter 60 starts counting after receiving the change in the potential detection signal 41, and when the time-out time is reached at time t3, the time-out signal 61 is set from the L level to the H level. When the clock control circuit 50 receives the H-level time-out signal 61, it shields the sampling signal 22, and therefore does not read the H-level of the potential detection signal 41 caused by external noise at time 4.

Therefore, the clock control circuit 50 does not recognize the signal pattern after time t2 as HLLH, so even if there is noise as shown in FIG. 4, it will not switch to the test mode by mistake.

As described above, since the sensing circuit according to the second embodiment includes the counter 60 that outputs the timeout signal 61, it is possible to more reliably prevent a malfunction caused by erroneous switching to the test mode.

In addition, the counter 60 may include a digital circuit using a flip-flop-based logic circuit, and may include an analog timing circuit based on a constant current source and a capacitive element. The timeout signal 61 may be reset from the H level to the L level based on the control signal 21 at time t5 or t6, for example.

<Third Embodiment>

FIG. 5 is a block diagram of a sensing circuit 300 according to the third embodiment. The sensing circuit 300 according to the third embodiment is provided with a dead time control circuit 70 in addition to the sensing circuit 100 of FIG. 1. The dead time control circuit 70 receives a control signal 21 and outputs a dead time signal. 71. The clock control circuit 50 in the third embodiment adopts a configuration that receives the dead time signal 71 output from the dead time control circuit 70. Other structures are the same as those of the sensing circuit 100 of FIG. 1, and therefore the same components are denoted by the same reference numerals, and descriptions thereof are omitted.

The dead time control circuit 70 inputs a potential detection signal 41 and outputs a dead time signal 71 to the clock control circuit 50. The clock control circuit 50 masks the sampling signal 22 when receiving the dead time signal 71 at the H level.

Next, an operation of the sensing circuit 300 according to the third embodiment will be described.

FIG. 6 is a timing chart showing the operation of the sensing circuit 300 according to the third embodiment.

In FIG. 6, the voltage of the dead time signal 71 is set to V71. The same operations as those in the timing chart of FIG. 2 will be omitted.

At time t1, the physical quantity detection signal 12 becomes the H level, and the output driver 30 sets the output to the L level. Here, when the capacitive load of the output terminal 31 is large, the voltage V31 of the output terminal 31 is stable in accordance with the time constant determined by the capacitive load of the output terminal 31 and the on-resistance of the output driver 30, which takes a relatively long time. .

When the dead-time control circuit 70 receives the control signal 21 at the H level, that is, the dead-time signal 71 at the H level is output in a predetermined period after the transition to the rest period. The clock control circuit 50 masks the sampling signal 22 without performing a sampling operation until the time t3 at which the dead-time signal 71 maintains the H level. Therefore, the clock control circuit 50 does not read the H level of the potential detection signal 41 from time t1 to time t3.

At time t2, since the voltage V31 of the output terminal 31 is lower than the determination threshold Vth of the potential detection circuit 40, the potential detection signal 41 becomes the L level. Therefore, the time for which the dead time signal 71 maintains the H level may be longer than the time when the voltage V31 is lower than the determination threshold Vth.

Therefore, even if noise overlaps the output terminal 31 at time t4, the clock control circuit 50 does not recognize the signal pattern after time t1 as HLLH, so it does not switch to the test mode by mistake.

As described above, since the sensing circuit 300 according to the third embodiment includes the dead-time control circuit 70 that outputs the dead-time signal 71 to the clock control circuit 50, it is possible to more reliably prevent a malfunction caused by an erroneous switching to the test mode.

In addition, the dead time control circuit 70 may include a logic circuit based on a flip-flop, and may also include a timing circuit based on a constant current source, a capacitive element, and a threshold circuit.

Furthermore, the case where the dead time signal 71 receives the control signal 21 and becomes the H level has been described, but any signal may be used as a starting point as long as it conforms to the gist of the invention.

<Fourth Embodiment>

FIG. 7 is a block diagram of a sensing circuit 400 according to the fourth embodiment. In the sensing circuit 400 according to the fourth embodiment, a reset circuit 80 is additionally added to the sensing circuit 100 of FIG. 1, and the reset circuit 80 outputs a reset signal 81. In addition, the clock control circuit 50 in the fourth embodiment is configured to receive a reset signal 81 output from the reset circuit 80. Other structures are the same as those of the sensing circuit 100 of FIG. 1, and therefore the same components are denoted by the same reference numerals, and descriptions thereof are omitted.

The reset circuit 80 receives a potential detection signal 41 and outputs a reset signal 81 to the clock control circuit 50. When the clock control circuit 50 receives the H-level reset signal 81, it resets the shift register holding the signal pattern.

Next, an operation of the sensing circuit 400 according to the fourth embodiment will be described.

FIG. 8 is a timing chart showing the operation of the sensing circuit 400 according to the fourth embodiment.

In FIG. 8, the voltage of the reset signal 81 is V81. The same operations as those in the timing chart of FIG. 2 will be omitted.

At time t1, the physical quantity detection signal 12 becomes the H level, and the output driver 30 sets the output to the L level. When the reset signal 81 is in a rest period, it is reset to the L level.

At time t2, when noise from the outside is superimposed on the output terminal 31, as shown in the figure, the voltage V31 changes, and a potential detection signal 41 of the H level is output. Therefore, the clock control circuit 50 reads the H level of the potential detection signal 41 based on the sampling signal 22.

Here, the reset circuit 80 has a function of detecting the width of the signal of the potential detection signal 41. For example, when it is detected that the width is small as shown at time t2 in FIG. 8, for example, at time t3, the reset signal 81 of the H level is output to the clock control circuit 50. When the clock control circuit 50 receives the H-level reset signal 81, it resets the shift register holding the signal pattern. That is, the H level read into the shift register at time t2 is reset.

Therefore, at time t4, the clock control circuit 50 does not mistakenly recognize the pattern of the potential detection signal 41 as HLLH even if noise from the outside overlaps the output terminal 31.

As described above, since the sensing circuit 400 according to the fourth embodiment includes the reset circuit 80 that outputs a reset signal 81 to the clock control circuit 50, it is possible to more reliably prevent a malfunction caused by an erroneous switching to the test mode.

In addition, the reset signal 81 is set to the L level when the reception control signal 21 is set to the H level in FIG. 8. However, the reset signal 81 may be set to, for example, one shot pulse.

As described above, the sensing circuit of the present invention includes the clock control circuit 50 that samples the potential detection signal 41 in synchronization with the sampling signal 22 and the clock generation circuit 20 that outputs the sampling signal 22 during the rest period. Reliably prevent malfunction caused by erroneous switching to test mode.

In the embodiment, the physical quantity detection unit 10 has been described as a magnetic sensing circuit. However, the configuration is not limited to this as long as the detection result of the physical quantity is output from the output terminal 31 as a binary signal. For example, the physical quantity detection unit 10 may be a temperature sensing circuit or a light sensing circuit.

Furthermore, the sensing circuit of the present invention is not necessarily limited to the structure or the sensor element, and various changes or combinations can be made without departing from the spirit of the invention. For example, the circuits of the respective embodiments may be appropriately combined. Furthermore, it is also possible to adopt a configuration including a combination of a plurality of sets of the physical quantity detection unit 10, the output terminal 31, and the clock control circuit 50, forcibly applying a voltage to each output terminal, and using this combination to switch to the test mode.

10‧‧‧Physical quantity detection department
20‧‧‧ clock generation circuit
30‧‧‧ output driver
31‧‧‧output terminal
40‧‧‧Potential detection circuit
50‧‧‧clock control circuit
60‧‧‧Counter
70‧‧‧Dead time control circuit
80‧‧‧ reset circuit
100, 200, 300, 400‧‧‧ sensing circuits

FIG. 1 is a block diagram of a sensing circuit according to the first embodiment. FIG. 2 is a timing chart showing the operation of the sensing circuit according to the first embodiment. FIG. 3 is a block diagram of a sensing circuit according to a second embodiment. FIG. 4 is a timing chart showing the operation of the sensing circuit according to the second embodiment. 5 is a block diagram of a sensing circuit according to a third embodiment. FIG. 6 is a timing chart showing the operation of the sensing circuit according to the third embodiment. FIG. 7 is a block diagram of a sensing circuit according to a fourth embodiment. FIG. 8 is a timing chart showing the operation of the sensing circuit according to the fourth embodiment.

10‧‧‧Physical quantity detection department

12‧‧‧ physical quantity detection signal

20‧‧‧ clock generation circuit

21‧‧‧Control signal

22‧‧‧Sampling signal

30‧‧‧ output driver

31‧‧‧output terminal

32‧‧‧ output logic signal

40‧‧‧Potential detection circuit

41‧‧‧Potential detection signal

50‧‧‧clock control circuit

51‧‧‧mode switching signal

100‧‧‧sensing circuit

Claims (5)

A sensing circuit performs an intermittent operation including an operation period and a rest period. The sensing circuit includes: a physical quantity detection unit that outputs two physical quantity detection signals of different potential levels according to an applied physical quantity; an output driver Receiving the physical quantity detection signal and outputting a logic signal to an output terminal; a clock generation circuit that outputs a control signal for controlling the intermittent operation to the physical quantity detection unit, and outputs a sampling signal during the rest period; a potential A detection circuit that detects a potential of the output terminal and outputs a detection signal; and a clock control circuit that inputs the sampling signal and the detection signal, and outputs a mode switching signal to the clock generation circuit, the clock control When the circuit detects a predetermined signal pattern in the data obtained by sampling the detection signal based on the sampling signal, it outputs a mode switching signal that switches the clock generation circuit to a test mode. The sensing circuit according to item 1 of the patent application range, wherein the clock control circuit further inputs the physical quantity detection signal output by the physical quantity detection unit, and when in the test mode, the physical quantity detection signal When a change occurs, a mode switching signal to switch to the normal mode is output. The sensing circuit according to item 1 or item 2 of the scope of patent application, further comprising: a counter that starts to count after receiving a change in the detection signal, and once the timeout period is reached, the clock control is performed. The circuit outputs a timeout signal, and the clock control circuit shields the sampling signal by the timeout signal. The sensing circuit according to item 1 or item 2 of the patent application scope further includes: a dead-time control circuit, wherein the dead-time control circuit controls the time during a predetermined period after the transition to the rest period. The pulse control circuit outputs a dead time signal, and the clock control circuit shields the sampling signal by the dead time signal. The sensing circuit according to item 1 or item 2 of the scope of patent application, further comprising: a reset circuit, wherein when the width of the detection signal is detected to be small, the reset circuit outputs a heavy signal to the clock control circuit. Setting signal, the clock control circuit shields the sampling signal by the reset signal.