TW201806037A - Systems and methods for achieving uniformity across a redistribution layer - Google Patents

Abstract

Systems and methods for achieving uniformity across a redistribution layer are described. One of the methods includes patterning a photoresist layer over a substrate. The patterning defines a region for a conductive line and a via disposed below the region for the conductive line. The method further includes depositing a conductive material in between the patterned photoresist layer, such that the conductive material fills the via and the region for the conductive line. The depositing causes an overgrowth of conductive material of the conductive line to form a bump of the conductive material over the via. The method also includes planarizing a top surface of the conductive line while maintaining the patterned photoresist layer present over the substrate. The planarizing is facilitated by exerting a horizontal shear force over the conductive line and the bump. The planarizing is performed to flatten the bump.

Description

System and method for achieving uniformity of entire redistribution layer

The present invention relates to a system and method for achieving uniformity throughout a redistribution layer.

Electrochemical deposition processes are commonly used in modern integrated circuit manufacturing. Metal wire interconnect structures drive the need for increasingly complex electrodeposition processes and plating tools. Many complexities have evolved in response to the need for smaller current carrying lines in the device metallization layer. These lines are formed by electroplating metal into very thin, high aspect ratio trenches and through holes.

Electrochemical deposition is now ready to meet commercial demand for complex packaging and multi-chip interconnect technologies (commonly referred to as wafer level packaging (WLP) and electrical connection technologies). These technologies present their very significant challenges in part due to the generally smaller feature sizes and low aspect ratios.

It is important that with smaller feature sizes and finer pitches, the amount of conductivity provided by the features is not compromised. This is the context in which the embodiments described in this disclosure arise.

Embodiments of the present disclosure provide systems and methods to achieve uniformity throughout the redistribution layer. It should be understood that embodiments of the present invention may be implemented in a variety of ways, such as a process, a device, a system, an apparatus, or a method on a computer-readable medium. Some embodiments are described below.

High-density fan-out (HDFO) wafer-level packaging (WLP) is a plating technology designed to improve package performance, reduce form factors, and drive related costs. The HDFO WLP series is seen as a replacement for significantly more expensive TSV technology. HDFO offers some interesting electroplating applications, such as fine-pitch redistribution layers (RDL) and stacked RDL.

Fan-out (FO) technology includes a semi-additive process (SAP), in which RDL lines are formed, copper systems are plated in a patterned area, photoresist systems are stripped, and barrier and seed layers are etched from the substrate . In addition, FO technology includes electrodeposited single-layer copper RDL, whose line thickness varies from 10 μm to 100 μm, and the spacing between two adjacent lines varies from 10 μm to 100 μm, while HDFO technology includes more subtle sections. Copper electrodeposited in RDL. For example, in HDFO technology, the thickness of RDL lines is 2 micrometers, and the spacing between two adjacent RDL lines is 2 micrometers. As another example, in HDFO technology, the thickness of an RDL line ranges from 2 to 10 microns, and the interval between two adjacent RDL lines ranges from 2 to 10 microns.

During the stacked RDL process, significant topography is created on the wafer surface during the generation of each RDL layer. Changes in this terrain limit the depth of the focal point of the lithography, which in turn causes line size changes across the wafer surface and resolution issues with finer line scaling. This article describes a method to overcome the problem of terrain changes, which uses a two-step process: (1) conformally electroplating RDL and superfilling vias simultaneously, making conductive materials such as copper or invariant steel (FeNi ₃₆ ) Cobalt overgrowth is generated on the through holes, and then (2) electropolishing or electrically etching the conductive material, so that a flat through hole-RDL surface system is formed.

In some embodiments, the system and method for achieving uniformity of the entire RDL layer includes overfilling the via with an RDL structure (such as a bump) so that an overgrowth on the via is formed. In addition, these systems and methods include performing an electro-polishing or electro-etching process to planarize the RDL structure of the RDL layer and / or other RDL regions of the RDL layer to minimize any topographic changes caused by electroplating of conductive materials. In various embodiments, the super-filling and electro-polishing or electro-etching processes for RDL structures and / or other RDL regions are sequentially performed in the same plating bath to minimize wafer transfer and maximize tool productivity. In some embodiments, the super-filling and electro-polishing or electro-etching processes for the RDL structure and / or other RDL regions are sequentially performed in different electroplating baths or different electroplating baths but within the same electroplating tool platform. Implemented to simplify wafer process flow and maximize wafer yield.

In various embodiments, a method for processing a substrate to improve the uniformity of the terrain of a redistribution layer when the redistribution layer interfaces with a via is described. The method includes patterning a photoresist layer over the substrate. The patterning step defines a region for a conductive line, and the through-hole disposed under the conductive line area. The wire is at a level of the redistribution layer. The method further includes depositing a conductive material between the patterned photoresist layers so that the conductive material fills the area of the through hole and the wire. The deposition step is further controlled to cause the conductive material of the wire to overgrow to form a bump of the conductive material directly above the through hole. The conductive material of the wires and the bumps are maintained below the fill level below the top surface of the patterned photoresist layer. The method also includes planarizing the top surface of the wire while maintaining the patterned photoresist layer present on the substrate. The planarization step is assisted by a liquid chemical that applies a horizontal shear force on the wire and the bump. This planarization step is performed to smooth the bumps. The method includes stripping the photoresist after performing the planarization step.

In some embodiments, a method for achieving uniformity of a redistribution layer is described. The method includes: depositing an organic dielectric layer on top of a pad disposed on a substrate, generating a plurality of through holes in the dielectric layer to generate a plurality of intermediate portions of the dielectric layer; A barrier and seed layer is deposited on top of the dielectric layer to form a film on top of the dielectric layer. The film is formed within the through holes and on top of the intermediate portions. The method further includes depositing a photoresist on top of the film of the seed layer to fill the through holes and form a layer over the intermediate portions of the dielectric layer. The method includes patterning a plurality of discontinuous areas of the photoresist by removing the plurality of portions of the photoresist to expose the plurality of portions of the film deposited within the through holes and the plurality of portions of the dielectric layer. A plurality of additional portions of the film are deposited on fragments of the middle portion. The method includes depositing the redistribution layer on top of the portions of the film deposited within the through holes and on top of the additional portions of the film such that the height of the redistribution layer is less than the height The height of the layer formed by the photoresist. The height of the redistribution layer and the height of the layer formed by the photoresist are measured from the substrate. The operation of depositing the redistribution layer is performed to overfill the through holes. Overfilling is performed to produce bumps of the redistribution layer. The bumps are created between the discontinuous areas of the photoresist. The method includes removing the bumps between the discontinuous regions of the photoresist to achieve uniformity.

Some advantages of the system and method for achieving uniformity of the entire RDL layer, such as reducing the non-uniformity of the entire RDL layer, removing the non-uniformity of the entire RDL layer, etc. Electro-etching or polishing of the RDL layer present between two adjacent areas of the layer. The area of the patterned photoresist layer defines the layout of the RDL layer. In addition, the high and uniform transverse shear flow of the catholyte from the electroplating reactor promotes the uniform electrodeposition of copper in the RDL layer over the entire substrate surface. Similarly, the uniform shear flow of the catholyte improves the uniformity and overall efficiency of the electrodeposition or etching process.

Additional advantages of the systems and methods described herein include the use of cobalt or constant steel or a combination thereof to make RDL layers. Cobalt and invariant steels have a low coefficient of thermal expansion and therefore a low probability of cracking at high temperatures.

Further advantages of the systems and methods described herein include the use of a combination of two or more of copper, cobalt, and constant steel to fabricate an RDL layer. This combination has a low probability of cracking at high temperatures.

Other implementation aspects will be described in detail below, especially in conjunction with the accompanying drawings.

The following examples describe systems and methods for achieving uniformity throughout the redistribution layer. It should be understood that embodiments of the present invention may be implemented without some or all of these specific details. In other cases, in order not to unnecessarily obscure the embodiments of the present invention, well-known process operations are not described in detail.

FIG. 1A is a diagram illustrating an embodiment of a method 100 of manufacturing a redistribution layer (RDL) 104 (FIG. 1B) on a substrate 102. FIG. The substrate 102 is a thin material such as silicon or an alloy of silicon and germanium. The method 100 includes operation 150: depositing a dielectric layer 124 material, such as an organic dielectric material (such as polyimide (PI)), on top of the gasket 122 to form a film of the dielectric material overlying the gasket 122 . An example of operation 150 is a spin coating process. Operation 150 is performed using system 800 described below with reference to FIG. The gasket 122 is made of a metal such as copper, or aluminum, or tungsten, or a combination thereof. The pad 122 covers the top of the substrate 102. In some embodiments, the liner 122 is deposited on the substrate 102 using the system 800. The spacer 122 is interposed between the dielectric layer 124 and the substrate 102. It should be noted that in some embodiments, there is no pad 122 between the substrate 102 and the dielectric layer 124. More specifically, the dielectric layer 124 is adjacent to the substrate 102.

In operation 152 of method 100, after depositing a dielectric layer 124 on top of the liner 122, the dielectric layer 124 is patterned to be between intermediate portions of the dielectric layer 124, such as intermediate portions 124A and 124B. A plurality of through holes is created, such as through holes 154. Operation 152 is performed using the wafer stepper 900 illustrated in FIG. 9 and the immersion container 1000 illustrated in FIG. 10. The immersive container 1000 is sometimes referred to herein as a wet bench. A through-hole system is formed between the middle portions of the dielectric layer 124 to expose a portion, such as a portion 156, of the pad 122.

In addition, after the patterning operation 152, a thin film of a barrier layer (such as a titanium layer, a tungsten layer, or a tantalum layer, or a layer of a combination of two or more of titanium, tungsten, and tantalum) is placed on the dielectric layer. Deposited on top of 124. A thin film of the barrier layer is deposited in operation 158 of method 100 to cover the middle portions 124A and 124B of the dielectric layer 124, and a portion 156 of the liner 122 with the vias 154 patterned on top thereof cover. Operation 158 is performed using physical vapor deposition (PVD). The PVD process is described below using system 1100.

In addition, in operation 158, a copper seed layer is deposited on top of the barrier layer to form a thin film of the copper seed layer on top of the barrier layer. For example, after depositing the barrier layer, the PVD process is repeated again in operation 158 to deposit a copper seed layer. A copper seed layer is deposited to cover the portion of the barrier layer covering the middle portions 124A and 124B of the dielectric layer 124, and the portion of the barrier layer covering the top of the portion 156 of the liner 122. cover. The copper seed layer and the barrier layer are referred to herein as the barrier and seed layer 123. When the barrier and seed layer 123 is deposited on top of the middle portions 124A and 124B of the dielectric layer 124 and on top of portions of the pad 122, such as portion 156, vias (such as via 106) It is formed between the middle portions 124A and 124B of the dielectric layer 124. When the through hole 154 is coated with the barrier and seed layer 123, the through hole 106 is formed on top of a part of the barrier and the seed layer 123. A portion of the barrier and seed layer 123 is covered within the through hole 106. The entire through hole 154 is not filled with the barrier and seed layer 123, but a thin film of the barrier and seed layer 123 is formed within the through hole 154 to generate the through hole 106.

After performing the operation 158 of depositing the barrier and seed layer 123, in operation 160 of the method 100, a photoresist layer 108 is deposited on top of the barrier and seed layer 123. The photoresist layer 108 is deposited by performing a spin coating process. For example, the system 800 is used to cover the photoresist layer 108 on top of the barrier and seed layer 123. A photoresist layer 108 is deposited to fill the vias 106 and form a thick layer on top of the barrier and seed layer 123 (eg, over the middle portions 124A and 124B of the dielectric layer 124). Photoresist layer 108 includes portions such as portion 128, which is described further below. The portion 128 extends above a portion of the middle portion 124A, above a portion of the middle portion 124B, and above the through hole 106.

It should be noted that the combination of the substrate 102, the pad 122 on top of the substrate 102, and the dielectric layer 124 on top of the pad 122 is referred to herein as a substrate package 103. In addition, a combination of the substrate 102, the pad 122 on the top of the substrate 102, and the middle portions 124A and 124B of the dielectric layer 124 on the top of the pad 122, and the through hole 154 on the top of the pad 122 It is sometimes referred to herein as a substrate package 105. In addition, the combination of the substrate 102 and the pad 122 is sometimes referred to herein as a substrate package 107. The combination of the substrate 102, the gasket 122, the middle portions 124A and 124B, and the barrier and seed layer 123 is sometimes referred to herein as a substrate package 109.

FIG. 1B is a diagram illustrating an embodiment of a method 100 of manufacturing the RDL layer 104. FIG. 1B is a continuation of the method 100 illustrated in FIG. 1A. After performing operation 160 of FIG. 1A, operation 162 of method 100 is performed. In operation 162, the photoresist layer 108 (FIG. 1A) is patterned such that adjacent regions (eg, adjacent regions A1 and A2) of the photoresist layer 108 are formed to form a plurality of regions between the adjacent regions. , Such as area 110. The region 110 is a space between the regions A1 and A2. The patterning of the photoresist layer 108 is performed using a wafer stepper 900 (FIG. 9) and an immersion container 1000 (FIG. 10). The region 110 is formed between two adjacent regions A1 and A2 and on the top of the through hole 106. The distance between the two adjacent areas A1 and A2 is denoted as d. The distance d is the width of the region 110 and is greater than the maximum width w (for example, the diameter) of the through hole 106. The maximum width w of the through-hole 106 is larger than all remaining widths of the through-hole 106. Region 110 is created by removing a portion of photoresist layer 108, such as portion 128 (FIG. 1A). Portions 128 are removed to expose portions 132A and 132B of the barrier and seed layer 123. A portion 132A is deposited on the segment 134A of the dielectric layer 124, and a portion 132B is deposited on the segment 134B of the dielectric layer 124. In addition, the portion 128 is removed to expose the barrier and the additional portion 130 of the seed layer 123 below the maximum width w of the through hole 106.

After operation 162 is performed, a descum operation 164 of the method 100 is performed. The deslagging operation 164 is performed to remove any remaining photoresist in the trench of the through hole 106 and improve the wettability of the photoresist regions A1 and A2. The deslagging operation 164 makes the photoresist less hydrophobic. The deslagging operation 164 is performed using the system 1200 illustrated in FIG. 12.

After the deslagging operation 164 is performed, the preprocessing operation 166 of the method 100 is performed. An example of a pre-processing operation 166 is described in US Patent No. 8,962,085, the entire contents of which are incorporated herein by reference. As another example, the pre-treatment operation is a pre-wetting operation performed using the system 1300 of FIG. 13A or the system 1320 of FIG. 13B.

In operation 168 of method 100, a conductive material 112 (such as copper, or cobalt, or constant steel, or nickel, or an alloy of nickel and cobalt and iron, or copper, cobalt, constant steel, nickel, nickel, and cobalt, and A combination of two or more of the iron alloys) is deposited in the through holes (such as the through holes 106) and in the areas such as the area 110 between the adjacent areas A1 and A2 of the photoresist layer 108. One example of an alloy of nickel, cobalt, and iron is the F15 ^™ material with a matching alpha to borosilicate glass. Operation 168 is performed after preprocessing operation 166. It should be noted that in some embodiments, cobalt is impermeable to copper seed etch chemicals (such as the etchant used to etch the copper seed layer) and has a Young's ratio approximately two times higher than copper Modulus to improve the electrical and mechanical performance of the RDL layer 104. The higher Young's modulus strengthens the RDL layer 104. In addition, the thermal expansion coefficient of cobalt is 17 parts per million (ppm / ^o C) and the thermal expansion coefficient of copper is 13 ppm / ^o C. As a result, high-density fan-out (HDFO) packages with cobalt as the RDL layer have a lower (such as 30%) likelihood of cracking during HDFO packaging applications including high temperatures. Similarly, invariant steel has a thermal expansion coefficient of less than 1 ppm / ° C.

The table below provides the characteristics of copper and cobalt. Table I

In addition, the following table provides characteristics of constant steel. Table II

The electrodeposition operation 168 is performed using the system 1400 illustrated in FIG. 14A. In some embodiments, operation 168 is performed using the apparatus described in US Patent No. 9,523,155, the entire contents of which are incorporated herein by reference. In operation 168, a through hole (such as the through hole 106) is overfilled with the conductive material 112 to generate a plurality of bumps (such as the bump 114) and a plurality of flush layers (such as the flush layer LL1). And flush layer LL2). As an example, the diameter of the bump 114 ranges between 180 microns and 220 microns. For illustration, the diameter of the bump 114 is 200 micrometers. The conductive material 112 is deposited on top of the portions 132A and 132B of the barrier and seed layer 123 and on top of the portion 130 of the barrier and seed layer 123. Each of the flush layers LL1 and LL2 is tied at level 117. The bump 114 is generated above the through hole 106 (for example, directly above the through hole 106). For example, the width (eg, diameter, perimeter, etc.) of the bump 114 is smaller than the maximum width w of the through hole 106. As another example, the bump 114 is concentric with the through hole 106. As yet another example, the width of the bump 114 is smaller than the maximum width w of the through hole 106, and the bump 114 is concentric with the through hole 106. As another example, the width of the bump 114 is smaller than the maximum width w of the through hole 106, and the bump 114 is located within a boundary defined by a line extending vertically from the maximum width w. In some embodiments, the width of the bump 114 is greater than the maximum width w of the through hole 106. In addition, the through hole 106 and a portion of the RDL layer 104 directly above the through hole 106 are filled up to a fill level 116 which is lower than the level 118 of the top surface of the photoresist layer 108. In addition, the level 117 is lower than the fill level 116 and the level 118 of the top surface of the photoresist layer 108. The flush layer LL1 is grown between the bump 114 and the adjacent area A1 of the photoresist layer 108, and the flush layer LL2 is grown between the bump 114 and the adjacent area A2 of the photoresist layer 108. In some embodiments, a part of the flush layer LL1 is generated above the through hole 106 (for example, directly above the through hole 106), and a part of the flush layer LL2 is above the through hole 106 (for example, directly above the through hole 106). (Above), the bump 114 is also generated directly above the through hole 106. It should be noted that the height h2 of the regions A1 and A2 of the photoresist layer 108 is greater than the height h1 of the bump 114. The heights h1 and h2 are measured from the bottom surface of the substrate 102. Similarly, the levels 116 to 118 are measured from the bottom surface of the substrate 102. The bump 114 is generated between the adjacent areas A1 and A2 of the photoresist layer 108.

Once operation 168 is performed, in operation 170 of method 100, the bumps (eg, bumps 114) of the conductive material 112 are removed in an electropolishing operation 170, which is sometimes referred to herein as It is an electric etching operation. Electropolishing operation 170 is performed using system 1401 of FIG. 14B. However, instead of using the conductive material 112 as the catholyte, during the electropolishing operation 170, an acid (such as phosphoric acid or sulfuric acid) is used to polish the bumps. In some embodiments, the conductive material 112 is used to etch the bumps. The bumps of the conductive material 112 are polished to planarize the top surface 120 of the RDL layer 104. The planarization of the top surface 120 is performed to form a flush region, such as a flush region LL3, between the flush layers LL1 and LL2.

In various embodiments, the planarization of the top surface 120 is performed to remove or reduce unevenness in the region of the RDL layer 104 between the bump 114 and the region A1 or A2 of the photoresist layer 108. In these embodiments, some non-uniformities may remain after operation 168.

In some embodiments, the level of the flush region (eg, flush region LL3) matches the height of the flush layers LL1 and LL2 measured from the lower surface of the substrate 102 such that the flush layer is between adjacent regions A1 and A2 To form. For example, each of the flush layers LL1, LL2, and LL3 is at level 117.

After operation 170, operation 172 of photoresist stripping of method 100 is performed. Operation 172 is performed using the system 1200 of FIG. In some embodiments, operation 172 is performed using the device described in US Patent No. 7,605,063, the entire contents of which are incorporated herein by reference. In various embodiments, the dip tank is used to perform a photoresist stripping operation 172. The photoresist layer 108 having adjacent areas A1 and A2 is immersed in a photoresist solvent to remove the areas A1 and A2. The photoresist layer 108 (eg, adjacent areas A1 and A2) is removed or etched during operation 172. Adjacent areas of the photoresist layer 108 (such as the adjacent areas A1 and A2) are removed to expose portions such as portions 136A and 136B or the barrier and seed layer 123 surrounding the RDL layer 104.

Once operation 172 is performed, operation 174 of method 100 is performed. Operation 174 is performed using the system 1200 of FIG. To illustrate, the copper seed layer is first etched away during operation 174 to expose the barrier layer. The copper seed layer is etched away using an etchant (such as acid, corrosive chemicals, copper etchant, etc.). The barrier layer below the copper seed layer is then etched away to expose portions of the dielectric layer 124, such as portions 138A and 138B. The barrier layer is etched away using an etchant (such as acid, corrosive chemicals, etc.). During operation 174, a portion of the barrier and seed layer 123, such as portions 136A and 136B, is etched away to expose that portion of the dielectric layer 124. After performing operation 174, the wires of the RDL layer 104 remain on top of the through-hole 106. Each wire has a flush top surface. For example, the wires of the RDL layer 104 have a flat top surface located in a horizontal plane. To illustrate, after performing the operation 170 of electropolishing, there is no unevenness in the flat top surface of the RDL layer 104. As another example, after performing the electro-polishing operation 170, the uniform amount within the RDL layer 104 is less than a predetermined threshold. As yet another example, there is no or only a non-uniform area that traps residues or residues and reduces the conductivity of the RDL layer 104, such as rough portions, grooves, and the like.

In some embodiments, operations 172 and 174 are both performed in the same chamber, such as a single plasma chamber 1202, which is described below with reference to FIG. It should be noted that a portion 138A of the dielectric layer 124 is a segment 134A adjacent to the dielectric layer 124, and a portion 138B of the dielectric layer 124 is a segment 134B adjacent to the dielectric layer 124. Segments 134A of the dielectric layer 124 are adjacent to the vias 106 and segments 134B of the dielectric layer 124 are adjacent to the vias 106. Compared to the segment 134A of the dielectric layer 124, the segment 134B of the dielectric layer 124 is located on the opposite side of the through hole 106. Similarly, compared to the portion 138B of the dielectric layer 124, the portion 138A of the dielectric layer 124 is located on the opposite side of the through hole 106.

In operation 176 performed after operation 174, the spin, wash, and dry (SRD) process is performed on the RDL layer 104 and the portions 138A and 138B of the dielectric layer 124. The SRD process takes place in a spin washer dryer. During the SRD operation, the substrate 102 is rotated on a support to perform a rotation operation. In addition, the cleaning operation is performed by allowing deionized water to flow on top of the portions 138A and 138B of the RDL layer 104 and the dielectric layer 124 for a set period of time (eg, one minute, two minutes, etc.). Deionized water is then blown out of the SRD. During the drying operation, the space within the SRD is heated using a heater to vaporize droplets of deionized water from the RDL layer 104 and portions 138A and 138B from the dielectric layer 124.

It should be noted that the combination of the substrate 102, the gasket 122, the patterned dielectric layer 124, the portions 130, 132A, and 132B of the barrier and seed layer 123, and the patterned photoresist layer 108 are sometimes referred to herein as Substrate package 135. In addition, it should be noted that the combination of the substrate 102, the spacer 122, the patterned dielectric layer 124, the regions A1 and A2 of the patterned photoresist layer 108, and the RDL layer 104 with bumps is sometimes referred to herein as a substrate Package 141. In addition, it should be noted that the combination of the substrate 102, the pad 122, the patterned dielectric layer 124, the through hole 106, the RDL layer 104, and the patterned photoresist layer 108 is sometimes referred to herein as a substrate package 137. In addition, it should be noted that the combination of portions 136A and 136B of the substrate 102, the pad 122, the patterned dielectric layer 124, the through hole 106, the RDL layer 104, and the barrier and seed layer 123 is sometimes referred to herein as Substrate package 139.

In some embodiments, the adjacent regions described herein are sometimes referred to herein as adjacent regions.

FIG. 2 is a diagram illustrating an embodiment of a method 200 of manufacturing an RDL layer 104 on a substrate 102. In the method 200, operation 160 is performed: a photoresist layer 108 is deposited on top of the barrier and seed layer 123. It should be noted that as shown in FIG. 2, no dielectric layer 124 and no pad 122 are located between the substrate 102 and the photoresist layer 108. In addition, after operation 160, operation 162 of patterning photoresist layer 108, slag removal operation 164, and pre-processing operation 166 are performed in method 200. The operation 162 of patterning the photoresist layer 108 is performed to fabricate adjacent areas A1, A2, and more adjacent areas A3, A4, and A5. Once operation 166 is performed, in method 200, operation 168 of electrodeposition of conductive material 112 is performed. For example, another bump 114 of the RDL layer 104 is generated between adjacent regions A3 and A1, another bump 114 of the RDL layer 104 is generated between adjacent regions A2 and A4, and the RDL layer Another bump 114 of 104 is created between adjacent areas A4 and A5. Further, after operation 168 is performed, operation 170 of electro-polishing each bump 114 is performed. Each bump 114 is electro-polished to form the top surface 120 of the RDL layer 104 to form the patterns P1, P2, P3, and P4 of the RDL layer 104. For example, another top surface 120 is formed between adjacent areas A3 and A1, another top surface 120 is formed between adjacent areas A2 and A4, and another top surface 120 is formed between adjacent areas A4 And A5.

After operation 170, operation 172 of method 200 is performed. Operation 172 includes performing a pattern of stripping the photoresist layer 108, such as the adjacent areas A1 to A5. The operation 172 of peeling the adjacent areas A1 to A5 of the photoresist layer 108 is performed until the portions 136A and 136B of the barrier and seed layer 123 are exposed. In addition, during operation 172, a portion 136C of the barrier and seed layer 123 is exposed. It should be noted that part 136A is located between two adjacent patterns P1 and P2 of the RDL layer 104, part 136B is located between two adjacent patterns P2 and P3 of the RDL layer 104, and part 136C is located between two adjacent patterns of the RDL layer 104 Adjacent patterns P3 and P4.

Once operation 172 is performed, operation 174 of method 200 is performed. During operation 174, portions of the barrier and seed layer 123, such as portions 136A, 136B, and 136C, are etched. When portions of the barrier and seed layer 123 are etched, portions of the substrate 102 (such as 182A, 182B, 182C, and 182D) are exposed. Part 182B is between the patterns P1 and P2 of the RDL layer 104, part 182C is between the patterns P2 and P3 of the RDL layer 104, and part 182D is between the patterns P3 and P4 of the RDL layer 104.

FIG. 3 is a diagram of an embodiment of a substrate package 300 to illustrate an RDL layer 104 including a bump, such as a bump 114. The substrate package 300 includes a substrate 102 as a bottom layer thereof. The substrate 102 is covered with a gasket 122 on the top thereof. The dielectric layer 124 is deposited on the pad 122 and is patterned to form the middle portions 124A and 124B of the dielectric layer 124. The electrodeposition operation is performed to overfill the vias 106 with a conductive material 112 to form an RDL layer 104 having bumps 114. For example, the diameter of the bump 114 is smaller than the maximum width w of the through hole 106, and the height of the bump 114 measured from the lower surface 302 of the substrate 102 is greater than the height of the through hole 106 from the lower surface 302. In addition, the height of the flush layer LL1 from the lower surface 302 of the substrate 102 is greater than the height of the through hole 106, and the height of the flush layer LL2 from the lower surface 302 of the substrate 102 is greater than the height of the through hole 106.

FIG. 4 is a diagram of an embodiment of a substrate package 400 to explain the unevenness in the RDL layer 2 caused by the unevenness in the RDL layer 1. The substrate package 400 includes a substrate. A pad is placed over the substrate. A dielectric layer 1 is tied on top of the pad. Above the dielectric layer 1 is an RDL layer 1. There is unevenness 402 in the RDL layer 1. For example, the unevenness 402 has a plurality of surfaces 404A, 404B, and 404C that are inclined relative to each other. To illustrate, the angle between the surfaces 404A and 404B is greater than 0 degrees or greater than 0.1 degrees. As another example, the angle between the surfaces 404B and 404C is greater than 0 degrees or greater than 0.1 degrees. As another example, the unevenness 402 has a curvature and is not straight. In contrast, in some embodiments, a uniform RDL layer lacks curvature and is straight, such as flush. As yet another example, the levels of the surfaces 404A, 404B, and 404C are offset from the horizontal LVL1 of the top surface 403 of the RDL layer 1.

Due to the non-uniformity of the RDL layer 1, the dielectric layer 2 on top of the RDL layer 1 is non-uniform. In addition, due to the non-uniformity of the dielectric layer 2, another RDL layer 2 above the dielectric layer 2 is non-uniform. For example, there is unevenness 406 within RDL layer 2. The unevenness 406 has a curvature. As another example, the unevenness 406 deviates from the horizontal LVL2 of the RDL layer 2. The unevenness 406 reduces the effectiveness of the RDL layer 2. For example, the conductivity of RDL layer 2 is reduced. In addition, there may be residual materials from the processes described herein (eg, SRD processes, etc.) that are deposited within the heterogeneity 406 to reduce performance.

FIG. 5 is a diagram of an embodiment of a substrate package 500 to illustrate an RDL layer 506 with a minimum (eg, within a predetermined threshold, etc.) or no unevenness on the top surface of the RDL layer 506. The substrate package 500 includes a substrate 102 and a pad 122 deposited over the substrate 102. In some embodiments, there is a layer, such as a dielectric layer, between the pad 122 and the substrate 102.

The substrate package 500 further includes a dielectric layer 124 deposited on top of the pad 122 and an RDL layer 104 deposited over the dielectric layer 124. Another dielectric layer 502 of the substrate package 500 is deposited on top of the RDL layer 104. For example, the operation 150 (FIG. 1A) of depositing a dielectric material on the RDL layer 104 is repeated to deposit a dielectric layer 502. In addition, the dielectric layer 502 is patterned by repeating operation 152 to generate through holes (such as through holes 504) within the dielectric layer 502. In addition, operation 158 (FIG. 1A) is repeated to deposit a thin film of barrier and seed layers on top of the dielectric layer 502. In addition, a photoresist layer is deposited on the barrier and seed layers deposited on top of the dielectric layer 502 by repeating operation 160 of FIG. 1A. The photoresist layer deposited on the barrier and seed layers is then patterned by repeating operation 162 of FIG. 1B. Patterns are created to create additional adjacent areas of the photoresist layer, such as adjacent areas A1 and A2 (FIG. 1B), deposited over the dielectric layer 502. In addition, the distance between the additional adjacent areas of the photoresist layer deposited over the dielectric layer 502 is greater than the maximum width of the through hole 504.

In addition, operations 164 and 166 of FIG. 1B are repeated to be performed on the patterned photoresist layer. Next, the electrodeposition operation 168 (FIG. 1B) of the conductive material 112 is performed on the barrier and seed layer deposited on the dielectric layer 502 and the additional adjacent area of the patterned photoresist layer deposited on the dielectric layer 502 This is performed to generate bumps (such as bumps 114 (FIG. 1B)) of conductive material 112 and flush layers (such as flush layers LL1 and LL2 (FIG. 1B)) of the RDL layer 506. Bumps are created directly above a through-hole, such as through-hole 504.

Thereafter, the electro-polishing operation 170 is performed to remove the bumps of the conductive material 112 to further produce a flush surface of the RDL layer 506, similar to the top surface 120 having the flush layers LL1, LL2, and LL3. For example, operation 170 applies a shear horizontal force to remove the bumps of the conductive material 112 (similar to the bumps 114 (FIG. 1B)) to further create a flat surface between the two of the additional adjacent areas. The horizontal shear force is parallel to the top surface 507 of the RDL layer 506 and is applied between the bump and two additional adjacent areas. After the bump system of the RDL layer 506 is removed, the patterned photoresist system is then stripped using operation 172 of FIG. 1B. In addition, the barrier and seed layer is etched using operation 174 of FIG. 1B to form an RDL layer 506. The RDL layer 506 is on top of the barrier and seed layer and above the dielectric layer 502. Next, operation 176 (FIG. 1B) of the SRD is performed on the substrate package 500.

It should be noted that the RDL layer 104 does not have any or only a minimal amount of non-uniformity. Therefore, the RDL layer 506 also does not have any or only a minimal amount of non-uniformity. It should be further noted that the combination of the pad 122 above the substrate 102, the dielectric layer 124 on top of the pad 122, the RDL 104 above the dielectric layer 124, and the dielectric layer 502 on top of the RDL 104 are This is sometimes referred to herein as a substrate package 503.

In various embodiments, the RDL layer 104 is made of copper, and the RDL layer 506 is made of cobalt or constant steel. This is because the etchant of the copper seed layer deposited on top of the patterned dielectric layer 502 has a smaller effect on the mechanical integrity of the RDL layer 506 made of constant steel or cobalt.

FIG. 6 is a diagram of an embodiment of a substrate package 600 to illustrate the deposition of multiple RDL layers. The substrate package 600 includes layers of the substrate package 500 (FIG. 5). In addition, on top of the RDL layer 506, a dielectric layer 602 of the substrate package 600 is deposited by using operation 150 of FIG. 1A. In addition, after the dielectric layer 602 is deposited, the dielectric layer 602 is patterned by performing operation 152 (FIG. 1A). After the dielectric layer 602 is patterned, a barrier and seed layer is deposited on top of the patterned dielectric layer 602 by performing operation 158 (FIG. 1A). Thereafter, a photoresist layer is deposited on the barrier and seed layers deposited on top of the patterned dielectric layer 602 by performing operation 160 (FIG. 1A). The photoresist layer is then patterned by performing operation 162 (FIG. 1B), followed by a slag removal operation 164 (FIG. 1B) and a pretreatment operation 166 (FIG. 1B). Next, the conductive material 112 is deposited between the patterned, dross-removed, and pre-processed photoresist layers to form bumps (such as bumps 114 (FIG. 1B)) of the conductive material 112 and to form a conductive material. The flush regions of 112 (such as flush layers LL1 and LL2 (Figure 1B)). For example, bumps and flush regions are created between two adjacent regions of a patterned, dross-free, and pre-treated photoresist layer. Operation 170 (FIG. 1B) of the electro-polished bump is then performed to produce a flush surface similar to the RDL layer 606 of the top surface 120, which is above the dielectric layer 602 and on top of the barrier and seed layers On it. For example, horizontal shear is applied to remove bumps between adjacent areas of the patterned, dross-removed, and pre-treated photoresist layer. Once the electro-polishing operation 170 is performed, the operation 172 (FIG. 1B) of peeling the patterned, dross-removed and pre-treated photoresist layer is performed. The portions of the barrier and seed layer on top of the dielectric layer 602 are etched by performing operation 174 (FIG. 1B). Next, operation 176 (FIG. 1B) of the SRD is performed on the substrate package 600.

It should be noted that the RDL layer 506 does not have any or only a minimal amount of non-uniformity. Therefore, the RDL layer 606 also does not have any or only a minimal amount of non-uniformity. It should be further noted that the combination of the substrate package 503, the RDL 506 on the dielectric layer 502, and the dielectric layer 602 on top of the RDL 506 is sometimes referred to herein as the substrate package 603.

In some embodiments, any number of RDL layers (eg, four, five, six, etc.) are deposited on the substrate 102 in a manner similar to the formation of RDL layers 506 and 606 over the substrate 102.

In various embodiments, the RDL layer 104 is made of cobalt, the RDL layer 506 is made of constant steel, and the RDL layer 606 is also made of constant steel. This is because the high conductivity of cobalt results in low resistance in the RDL layer 506, and the use of constant steel minimizes the effects of any coefficient of thermal expansion (CTE).

In some embodiments, the RDL layer 104 is made of copper, the RDL layer 506 is made of constant steel, and the RDL layer 606 is also made of constant steel. This is because the high conductivity of copper results in a low resistivity of the RDL layer 104, and the use of constant steel minimizes any effects of the coefficient of thermal expansion (CTE).

In various embodiments, the RDL layer 104 is made of any conductive material (such as the above-mentioned conductive material 112), the RDL layer 506 is made of any conductive material (such as the above-mentioned conductive material 112), and the RDL layer 606 is made of any conductive material Made of a material such as the conductive material 112 described above. For example, the RDL layer 104 is made of nickel, the RDL layer 506 is made of constant steel, and the RDL layer 606 is made of an alloy of nickel and cobalt and iron. As another example, the RDL layer 104 is made of an alloy of nickel and cobalt and iron, the RDL layer 506 is made of cobalt, and the RDL layer 606 is made of constant steel.

FIG. 7 is a diagram of an embodiment of an integrated circuit stack 700. The integrated circuit stack 700 is a high-density fan-out (HDFO) package with a multi-die system. In some embodiments, the thickness of the HDFO package ranges between 0.8 mm and 0.1 mm. For example: HDFO package height is 0.9 mm. The integrated circuit stack 700 has advantages such as the lower height of the TSV integrated circuit stack, the improved thermal performance of the TSV integrated circuit stack compared to the TSV integrated circuit stack, Low power consumption, higher bandwidth memory compared to TSV integrated circuit stack, and simplified supply chain compared to TSV integrated circuit stack.

The integrated circuit stack 700 includes a top integrated circuit (IC) package 702 (such as a memory circuit package) and a bottom IC package 704 (such as a logic circuit package). In some embodiments, both the top and bottom IC packages are memory circuit packages or logic circuit packages.

The top IC package 702 contains a system-on-a-chip (SoC) 706A, which is placed on top of another SoC 706B. In some embodiments, the top IC package 702 has a single SoC or multiple SoCs stacked on top of each other. The bottom IC package 704 has a SoC 708. In some embodiments, the bottom IC package 704 has multiple SoCs stacked on top of each other.

The substrate package 710 of the bottom IC package 704 is coupled to the SoC 708 by one or more under bump metal layers (UBM) (such as UBM 712) and one or more pillars (such as pillars 714). Sometimes pillars are referred to herein as micro-bumps. The substrate package 500 (FIG. 5) is an example of the substrate package 710. In some embodiments, instead of the substrate package 500, the substrate package 600 (FIG. 6) or another substrate package having multiple RDLs is used in the integrated circuit stack 700.

In addition, SoC 708 is coupled to the top IC package 702 through RDL 716 and one or more megapillars (eg, megapillar 718). SoC 708 components (such as memory devices, memory controllers, processors, logic circuits, etc.) via RDL 716 and one or more pillars and another component of the top IC package 702 (such as memory devices, memory control Device, processor, logic circuit, etc.).

In some embodiments, one or more UBMs are made of copper, or nickel, or gold, or a combination of two or more of copper, nickel, and gold (eg, CuNiAu). Further, in various embodiments, the thickness (eg, diameter) of each UBM ranges from 3 microns to 5 microns. For example: UBM 712 has a thickness of 3 microns. As another example, UBM 712 has a thickness of 5 microns. In some embodiments, the critical dimension (CD) of each UBM ranges from 190 microns to 240 microns. For example: each UBM has a CD of 190 microns. As another example, each UBM has a CD of 210 microns. In various embodiments, each UBM has a non-uniformity between 8% and 12%. For example: each UBM has a non-uniformity of 10%.

In various embodiments, one or more pillars (such as micro-bumps) are made of copper, or nickel, or silver, or tin, or a combination of two or more of copper, nickel, tin, and silver (such as Cu (Ni ) SnAg). Further, in some embodiments, the thickness of each post ranges from 25 microns to 40 microns. For example: pillar 714 has a thickness of 25 microns. As another example, the pillar 714 has a thickness of 40 microns. In several embodiments, the CD of each column ranges from 25 microns to 90 microns. For example: each column has a 25 micron CD. As another example, each column has a CD of 90 microns. As yet another example, some columns have a CD of 25 microns and the remaining columns have a CD of 90 microns. In some embodiments, each column has a non-uniformity between 8% and 12%. Example: 10% non-uniformity per column.

In various embodiments, the RDL 716 is made of a conductive material 112. Further, in some embodiments, the thickness of RDL 716 ranges from 0.75 microns to 3 microns. For example: RDL 716 has a thickness of 1 micron. As another example, RDL 716 has a thickness of 2 microns. In several embodiments, the CD of RDL 716 ranges from 3 microns to 5 microns. For example: RDL 716 has a 3 micron CD. As another example, RDL 716 has a 5 micron CD. In some embodiments, the distance between two adjacent RDLs (eg, at the same level of RDL) ranges from 0.75 microns to 3 microns. For example: the distance or spacing between two adjacent RDLs at the same level is 2 microns. As another example, the distance or spacing between two adjacent RDLs at the same level is 1 micron. In various embodiments, RDL 716 has a non-uniformity between 4% and 12%. For example: RDL 716 has 4% non-uniformity. As another example, RDL 716 has 10% non-uniformity, for example, 10% of the top surface of RDL 716 has non-uniformity.

In some embodiments, one or more giant pillars are made of a conductive material 112. Further, in some embodiments, the thickness of the one or more giant pillars ranges from 150 microns to 200 microns. For example: the pillar 718 has a thickness of 150 microns. As another example, the giant pillar 718 has a thickness of 200 microns. In several embodiments, the CDs of the giant pillars 718 range from 100 microns to 200 microns. For example: Jumbo 718 has a 100 micron CD. As another example, the giant pillar 718 has a 200 micron CD. In various embodiments, the pillars 718 have a non-uniformity between 5% and 10%. For example: Jumbo 718 has 5% non-uniformity.

FIG. 8 is a diagram of an embodiment of a system 800 including a spinner 802. The system 800 includes a spinner 802, a host computer 804, a motor 806, a vacuum pump 808, and a liquid reservoir 810. The substrate 102 is placed on top of a support 816 (eg, a metal support, a plastic support, etc.) within the spinner 802. The support 816 is connected to the motor 806 by one or more connecting mechanisms (such as one or more rods, a combination of rods and gears, etc.).

The motor 806 is coupled to the host computer 804, which is coupled to the vacuum pump 808 and the valve 812. The host computer 804 controls the valve 812 to open or close the valve 812. For example, the host computer 804 sends a signal to a valve driver (eg, a conductor) to generate a current that generates an electric field to open or close the valve 812. The opening of the valve allows a liquid (such as a dielectric material deposited in operation 150 (FIG. 1A), a photoresist deposited in operation 160 (FIG. 1A), etc.) to pass through the rotator 802 to be on the substrate 102 of the substrate package 815 On the surface 814. For example, a liquid system is deposited at or near the center of surface 814. The substrate package 815 is an example of the substrate package 107 or the substrate package 109 (FIG. 1A). Surface 814 is an example of the top surface of pad 122 (FIG. 1A, operation 150) or the top surface of barrier and seed layer 123 (FIG. 1A, operation 160).

After the liquid is deposited on the surface 814, the host computer 804 controls the motor 806 to rotate the support 816. For example, the host computer 804 sends a control signal to a motor driver (such as more than one transistor) to generate a current signal. The current signal is sent to the rotor of the motor 806 to rotate the rotor relative to the stator of the motor to rotate the support 816 by the connection mechanism. The rotation of the support 816 rotates the surface 814 to evenly disperse the liquid on the surface 814 by centrifugal force, so that the liquid system is deposited on the surface 814.

The host computer 804 controls the vacuum pump 808 to operate to remove any excess liquid within the spinner 802. For example, the host computer 804 sends a signal to a vacuum driver (eg, more than one crystal body, etc.) to turn on the vacuum pump 808 to generate a partial vacuum within the spinner 802 to remove any excess liquid from the spinner 802. In some embodiments, the vacuum pump 808 is operated by the host computer 804 to remove any excess residual material from the spinner 802 before the liquid system is allowed to enter the spinner 802 from the liquid reservoir 810.

FIG. 9 is a diagram of an embodiment of a wafer stepper 900 for explaining forming a pattern on a dielectric layer or a photoresist layer. Examples of the dielectric layer include a dielectric layer 124 (FIG. 1A), a dielectric layer 502 (FIG. 5), and a dielectric layer 602 (FIG. 6). Examples of the photoresist layer include a photoresist layer 108 (FIG. 1A).

The wafer stepper 900 includes a light source 902 (for example, an ultraviolet (UV) light source, an X-ray light source, etc.), a lens 904, a light mask 906, and a projection lens 908. Examples of UV light sources include mercury vapor lamps. A substrate 102 (FIG. 1A) on which one or more layers (eg, a photoresist layer, a dielectric layer, etc.) are deposited is placed on a substrate holder 910 within a wafer stepper 900.

The light source 902 generates light, such as UV light, x-ray, and the like, which passes through the lens 904. The lens 904 directs (eg, focuses) light toward the light mask 906. The guided light passes through a region of the light mask 906 that allows the guided light to pass through, and is incident on the projection lens 908. The projection lens 908 directs incident light onto, for example, a portion of a layer of the dielectric layer described herein and a layer of the photoresist layer described herein, and a pattern is applied to this portion of the layer (eg, embossing, covering, etc.). The light directed onto the layer covers the pattern on the layer deposited on the substrate 102. The substrate holder 910 is moved in the x and y directions to repeatedly apply a pattern.

FIG. 10 is a diagram of an embodiment of an immersive container 1000 to illustrate the peeling of a patterned dielectric layer or photoresist layer. The immersion container 1000 is filled with a chemical solution (such as a developer, deionized water mixed with nitrogen, deionized water, etc.) to remove a region exposed to a dielectric layer or a photoresist layer exposed to light. If the photoresist of the photoresist layer is of a positive type, when immersed, the area exposed to the photoresist of the light becomes soluble in the developer. On the other hand, if the photoresist layer of the photoresist layer is of a negative type, when immersed, a region not exposed to the photoresist of light becomes soluble in the developer. An example of photolithography is described in US Patent Application Publication No. 2008/0171292, the entire contents of which are incorporated herein by reference.

FIG. 11 is a diagram illustrating an embodiment of a system 1100 for a PVD process. System 1100 includes a radio frequency generator (RFG) 1102, an impedance matching circuit (IMC) 1104, a plasma chamber 1106, a container 1108 for storing more than one processing gas, a host computer 804, another RFG 1112, another IMC 1114, and Vacuum pump 1116.

The IMC includes multiple electrical components, such as: one or more capacitors, or one or more resistors, or one or more inductors, or a combination of one or more capacitors and one or more resistors, or a combination of one or more capacitors and one or more inductors, or A combination of one or more resistors and one or more inductors, or a combination of one or more capacitors and one or more resistors and one or more inductors. Some of the one or more electrical components are coupled to each other in a series manner or a parallel manner.

The host computer 804 is a desktop computer, a laptop computer, or a smart phone. The host computer 804 includes one or more processors and one or more memory devices coupled to the one or more processors. As used herein, a processor is an application-specific IC, or a programmable logic device, or a microprocessor, or a central processing unit (CPU). In addition, as used herein, a memory device is a random access memory (RAM), or a read-only memory (ROM), or a combination of RAM and ROM. The host computer 804 is coupled to the RFG 1102 by a cable (such as a serial data transmission cable, a parallel data transmission cable, a universal serial bus (USB) cable, etc.). Similarly, the host computer 804 is coupled to the RFG 1112 by another cable (such as a serial data transmission cable, a parallel data transmission cable, a USB cable, etc.).

RFG 1102 is coupled to IMC 1104 via RF cable 1126, and IMC 1104 is coupled to top plate 1122 via RF transmission line 1128. In addition, RFG 1112 is coupled to IMC 1114 via RF cable 1130, and IMC 1114 is coupled to chuck 1120 via RF transmission line 1132.

The plasma chamber 1106 contains a chuck (such as an electrostatic chuck (ESC) on which the substrate package 1124 is placed), a top plate 1122, and other components (not shown), such as an upper dielectric ring surrounding the top plate 1122, An upper electrode extension of the dielectric ring, a lower dielectric ring surrounding the lower electrode of the chuck 1120, a lower electrode extension surrounding the lower dielectric ring, an upper plasma exclusion zone (PEZ) ring, a lower PEZ ring, and the like. Examples of the substrate package 1124 include a substrate package 105 (FIG. 1A), a substrate package 503 (FIG. 5), or a substrate package 603 (FIG. 6). The top plate 1122 is located on the opposite side of the chuck 1120, on the top of the chuck 1120, and facing the chuck 1120. Each of the top plate 1122 and the chuck 1120 is made of metal, such as aluminum, an aluminum alloy, copper, a combination of copper and aluminum, and the like. Examples of the processing gas stored in the container 1108 include a sputtering gas, argon, and the like.

The host computer 804 sends a signal to a valve driver (an example of which is provided above) to open the valve 1123. When the valve 1123 is opened, the processing gas flows from the container 1108 into the plasma chamber 1106 through the inlet of the plasma chamber 1106. In addition, when receiving a control signal from the host computer 804 via a cable, the RFG 1102 generates an RF signal provided to the IMC 1104. When receiving an RF signal from the RFG 1102, the IMC 1104 matches the impedance of the load coupled to the output of the IMC 1104 and the impedance of the source coupled to the input of the IMC 1104 to generate a modified RF signal. Examples of loads coupled to the IMC 1104 include a plasma chamber 1106 and an RF transmission line 1128. Examples of sources coupled to IMC 1104 include RFG 1102 and RF cable 1126. The modified RF signal is sent from the IMC 1104 to the top plate 1122 via the RF transmission line 1128.

Similarly, when receiving a control signal from the host computer 804 via a cable, the RFG 1112 generates an RF signal provided to the IMC 1114. When receiving an RF signal from RFG 1112, IMC 1114 matches the impedance of the load coupled to the output of IMC 1114 and the impedance of the source coupled to the input of IMC 1114 to generate a modified RF signal. Examples of loads coupled to IMC 1114 include a plasma chamber 1106 and an RF transmission line 1132. Examples of sources coupled to IMC 1114 include RFG 1112 and RF cable 1130. The modified RF signal is sent from the IMC 1114 to the chuck 1120 via the RF transmission line 1132.

The modified RF signal is provided to the top plate 1122, the modified RF signal is provided to the chuck 1120, and the processing gas is supplied to the plasma chamber 1106 through the inlet to generate a plasma within the plasma chamber 1106, such as igniting electricity Pulp. The plasma contains ions of the process gas, and the ions react with the target material layer attached to the top plate 1122. Examples of target materials include materials for the barrier layer described herein, and materials for the copper seed layer described herein. To illustrate, the target material is copper or titanium, tungsten or tantalum, or a combination of two or more of titanium, tungsten, and tantalum.

When the ions interact with the target material, the target material is sputtered from a target material layer to be deposited on top of the substrate package 1124. For example, a barrier layer or a copper seed layer is placed on top of the middle portions 124A and 124B (FIG. 1A) of the patterned dielectric layer and on top of the portion 156 (FIG. 1A) of the pad 122 form. The vacuum pump 1116 is operated to generate a partial vacuum within the plasma chamber 1106 to remove residual material from the plasma chamber 1106.

In some embodiments, instead of sputtering the target material, the PVD process includes thermal gasification. Thermal gasification source materials are heated to vaporize deposition techniques. The vaporized source material is deposited on a substrate package 1124.

FIG. 12 is a diagram of an embodiment of a system 1200 for performing a photoresist stripping operation 172, a slag removing operation 164, and a barrier and seed layer etching operation 174 (FIG. 1B). System 1200 includes RFG 1102, IMC 1104, RFG 1112, host computer 804, plasma chamber 1202, a container 1204 for storing more than one processing gas, and another container 1205 for storing more than one etchant.

The plasma chamber 1202 includes a shower head 1210 and a chuck 1120. The shower head 1210 faces the chuck 1120. The shower head 1210 includes a plurality of holes to allow more than one processing gas stored in the container 1204 to be applied to the substrate package 1208 placed on the chuck 1120. The shower head 1210 also includes an upper electrode plate. In some embodiments, the upper electrode plate of the shower head 1210 is made of aluminum, an aluminum alloy, or copper, or a combination of copper and aluminum.

To etch the copper seed layer, an etchant (eg, copper etchant, acid, etc.) is supplied from the container 1205 to the shower head 1210 via the valve 1207. As described above, the host computer 804 controls the valve 1207 via the valve driver to open the valve 1207. The etchant is supplied to the substrate package 1208 via the shower head 1210 to etch away the copper seed layer. Similarly, to etch the barrier layer, a barrier etchant (such as an acid, etc.) is supplied from the container 1205 to the shower head 1210 via the valve 1207. When a barrier etchant is applied to the substrate package 1208, the barrier etchant etches away the barrier layer.

During the photoresist stripping operation 172 (FIG. 1B) or the slag removing operation 164, the host computer 804 sends a signal to open the valve 1206 via the valve driver described above. When the valve 1206 is opened, more than one processing gas (such as carbon dioxide, oxygen, and etchant gas) stored in the container 1204 is supplied. In addition, the modified RF signal is supplied to the chuck 1120 via the RF transmission line 1132. Further, the modified RF signal is supplied to the upper electrode plate of the showerhead 1210 via the RF transmission line 1128.

When the modified signal is supplied to the shower head 1210 and the chuck 1120, one or more process gas systems supplied to the plasma chamber 1202 are burned to ignite the plasma within the plasma chamber 1202. The plasma performs a photoresist peeling operation 172 or a slag removing operation 164 on the substrate package 1208. To illustrate, when the one or more processing gases include carbon dioxide or an etchant gas, a photoresist stripping operation 172 is performed. As another example, when the one or more process gases include oxygen or an etchant gas, the slag removing operation 164 is performed.

It should be noted that in some embodiments, an RFG other than RFG 1102, an RF cable other than RF cable 1126, an IMC other than IMC 1104, an RF transmission line other than RF transmission line 1128, an RF transmission line other than RFG 1112, RFG, an RF cable other than the RF cable 1130, an IMC other than the IMC 1114, and an RF transmission line other than the RF transmission line 1132 are used in the system 1200.

It should be further noted that when the slag removal operation 164 is performed on the substrate package 1208, the substrate package 1208 is an example of the substrate package 135 (FIG. 1B). In addition, when the photoresist peeling operation 172 is performed on the substrate package 1208, the substrate package 1208 is an example of the substrate package 137 (FIG. 1B). Further, when the barrier and copper seed etching operations 174 are performed on the substrate package 1208, the substrate package 1208 is an example of the substrate package 139 (FIG. 1B).

In some embodiments, the photoresist stripping operation 172 and the barrier and seed layer etching operation 174 are often performed in the same processing tool (such as a processing tool other than the system 1200), and the slag removing operation 164 It is implemented using system 1200. In addition, a solvent-based wet chemical is applied within the processing tool using a single wafer spray system for performing a photoresist stripping operation 172. Similarly, a copper etchant (eg, a dilute piranha solution, etc.) is dispensed on the substrate 102 via a single wafer spray system to etch the copper seed layer as described herein.

FIG. 13A is a diagram illustrating an embodiment of a system 1300 of a pre-processing operation 166 (FIG. 1B). The system 1300 includes a chamber 1302, a motor 1304, and a container 1306. The motor 1304 is coupled to the wafer holder 1308 via one or more of the above-mentioned connecting mechanisms. The wafer holder 1308 holds the substrate package 1312. The substrate package 1312 is an example of the substrate package 135 (FIG. 1B), on which the slag removing operation 164 has been performed and the pre-processing operation 166 is to be performed.

As described above, the host computer 804 sends a signal to the valve driver to further open the valve 1310. When the valve 1310 is opened, the pre-wetting fluid (for example, water, water-miscible solvent, chemical solution, deionized water, combination of deionized water and chemical solution, etc.) from the container 1306 flows into the chamber 1302. In addition, as described above, the host computer 804 sends a signal to the motor driver to operate the motor 1304. The motor 1304 operates (eg, rotates, etc.) to lower the position of the wafer holder 1308 to allow the substrate package 1312 to be immersed in the pre-wetting fluid in the chamber 1302.

Once the substrate package 1312 is pre-wetted, the motor 1304 is operated to raise the wafer holder 1308 to remove the substrate package 1312 from the state of being immersed in the pre-wetting fluid. The motor 1304 is further operated to rotate the wafer holder 1308 to remove the pre-wetting fluid from the surface of the substrate package 1312. Before, during, or after the pre-processing operation 166, the vacuum pump 1116 is operated to remove any undesired residual materials (such as pre-wetting fluid) from the surface of the substrate package 1312 of the chamber 1302, and the like.

FIG. 13B is a diagram illustrating an embodiment of the system 1320 of the pre-processing operation 166 (FIG. 1B). The system 1320 includes a chamber 1322, a motor 1304, and a container 1306. The motor 1304 is coupled to the chuck 1324 via one or more of the above-mentioned connecting mechanisms. The chuck 1324 holds the substrate package 1312. For example, the chuck 1324 has arms that are oriented at equal angles (eg, 120 degrees) around the periphery of the substrate package 1312 to hold the substrate package 1312.

As described above, the host computer 804 sends a signal to the valve driver to open the valve 1310. When the valve 1310 is opened, a pre-wetting flow system from the container 1306 is dispensed or sprayed onto the top of the substrate package 1312 of the chamber 1322.

In addition, as described above, the host computer 804 sends a signal to the motor driver to operate the motor 1304. The motor 1304 operates (eg, rotates, etc.) to rotate the substrate package 1312, while the substrate package 1312 is held by the chuck 1324, and the pre-wetting flow system is applied to the substrate package 1312 at the same time. The substrate package 1312 is held to reduce the chance of the substrate package 1312 sliding or moving. In some embodiments, the motor 1304 is not operated while the pre-wetting flow system is applied to the substrate package 1312.

Once the substrate package 1312 is pre-wetted, the motor 1304 is operated to rotate the chuck 1324 to remove the pre-wetting fluid from the surface of the substrate package 1312 for collection at the bottom of the chamber 1322. Prior to, during, or after the pretreatment operation 166, the vacuum pump 1116 is operated to remove undesired residual material from the chamber 1322.

FIG. 14A is a diagram illustrating an embodiment of a system 1400 of an electrodeposition operation 168 (FIG. 1B). The system 1400 includes a host computer 804, a rotatable shaft 1418, a chamber 1420, a container 1422 for storing catholyte, and a pump 1424. Examples of the catholyte include a liquid made of a conductive material 112 such as copper, or cobalt, or copper sulfate, or constant steel, or a combination of two or more of cobalt, constant steel, copper sulfate, and copper. In some embodiments, the catholyte contains a liquid made of a conductive material, and further includes a combination of more than one accelerator and more than one leveler. In various embodiments, the catholyte contains a liquid made of a conductive material, and further includes a combination of more than one accelerator and more than one inhibitor. In several embodiments, the catholyte contains a liquid made of a conductive material, and further includes a combination of more than one accelerator and more than one inhibitor and more than one leveler. The accelerator accelerates the filling of the conductive material 112 in the through-holes (for example, the through-holes 106 (FIG. 1A), the through-holes 504 (FIG. 5), the through-holes 604 (FIG. 6), etc.), and overfills the through-holes to form protrusions. Block (eg, bump 114 (FIG. 1B)). The inhibitor inhibits (eg, reduces acceleration, deceleration, etc.) the filling of the conductive material 112 in a portion of the via (eg, via 106 (FIG. 1A), via 504 (FIG. 5), via 604 (FIG. 6), etc.) . For illustration, when the conductive material 112 is mainly filled on the bottom surface of the through hole (such as the through hole 106, the through hole 504, or the through hole 604, etc.), the inhibitor suppresses the conductive material at the side surface of the through hole. Fill of 112. The side surface is adjacent to the bottom surface and is at an angle with respect to the bottom surface, for example: tilt, positive tilt, negative tilt, etc. The leveler leveles the conductive material 112 to form a flush layer on top of another layer, such as a portion 132A of the barrier and seed layer 123, a portion 132B (FIG. 1B) of the barrier and seed layer 123, and the like The flush layer LL1, the flush layer LL2 (FIG. 1B), etc. of the material 112. In some embodiments, the catholyte is a liquid electroplating chemical comprising a conductive material, and further includes additives such as a combination of an accelerator, an inhibitor, and a leveler.

The substrate package 1404 is held, positioned, and rotated by the wafer holder 1406 of the chamber 1420. The chamber 1420 includes a plating tank 1408, which is a double chamber tank having an anode chamber having, for example, a counter electrode 1409 (such as a copper electrode) and an anolyte. The anode chamber and the cathode chamber are separated by, for example, a film 1410 (eg, a cationic film), which is used for electrodeposition and is supported by a support member 1412. The system 1400 further includes an ion channel type resistive plate (CIRP) 1414. A shunt 1416 is attached to the top of the CIRP 1414 and assists in generating a transverse shear flow of the catholyte. The catholyte is introduced from the container 1422 through a flow port 1433 above the cationic membrane 1410. From the flow port 1433, the catholyte passes through CIRP 1414 and is on top of the portions 132A and 132B of the surface of the substrate package 1404 (such as the barrier and seed layer 123 (FIG. 1B)) and on the barrier and seed layer 123 (FIG. 1B) on top of portion 130), an impulse flow is generated to overfill via 106 to produce bumps 114 and to deposit conductive material 112 on portions 132A and 132B to produce flush layers LL1 and LL2. In addition, the catholyte is introduced into the flow port 1430 located on the side surface 1402 of the chamber 1420 from the container 1422 via the pump 1424. For example, the inlet of the flow port 1430 is located below the anode. In this example, the flow port 1430 is a channel in the side wall 1432 of the plating tank 1408. The functional result is that the catholyte flow is directly introduced into the plating area formed between the CIRP 1414 and the substrate package 1404 to enhance the lateral shear flow of the entire substrate package 1404, as shown by the arrow direction 1407 in FIG. 14A. For example, the transverse shear flow is in a direction 1407 parallel to the top surfaces 120 of the flush layers LL1 and LL2. Transverse shear flow is applied between adjacent areas A1 and A2 to create bumps 114 between the flush layers LL1 and LL2.

In addition, when a catholyte having a combination of two or more of a conductive material 112 and an accelerator, an inhibitor, and a leveler is introduced into the chamber 1420 to the substrate package 1404, the host computer 804 controls the direct current (DC) of the system 1400. A power source 1434 to supply DC power to the counter electrode 1409 and the wafer holder 1406. The wafer holder 1406 is positively charged with DC power as a cathode, and the counter electrode 1409 is negatively charged with DC power as an anode to allow electrodeposition of catholyte ions on the substrate package 1404. In some embodiments, for the electrodeposition operation 168, the wafer holder 1406 and the substrate package 1404 serve as cathodes and include reduction of Cu ²⁺ -> Cu, and the anode is oxidized from Cu-> Cu ²⁺ . In these embodiments, the anode contains copper.

FIG. 14B is a diagram illustrating an embodiment of a system 1401 for an electropolishing operation 170 (FIG. 1B). The structure and components of the system 1401 are similar to the system 1400 (FIG. 14A), except that the system 1401 includes a chamber 1421 and a container 1423. The structure and components of the chamber 1421 are similar to the chamber 1420 (FIG. 14A), except that the chamber 1421 includes a counter electrode 1411. When acids (such as phosphoric acid, hydrochloric acid, sulfuric acid, etc.) are stored inside the container 1423 and used to replace the catholyte and are introduced into the chamber 1421 to the substrate package 1404, the host computer 804 controls the DC power source 1434 of the system 1401 To supply DC power to the counter electrode 1411 and the wafer holder 1406. The wafer holder 1406 is negatively charged with DC power as the anode, and the counter electrode 1411 is positively charged with DC power as the cathode to allow the polishing of the bumps (such as bumps 114) of the substrate package 1404. The anode reaction is Cu-> Cu ²⁺ , while the cathode reaction includes 2H ⁺ -> H ₂ . The cathode is made of an inert material such as titanium, or platinum, or iridium, or a combination of two or more thereof.

A splitter 1416 is on top of the CIRP 1414 and assists in generating a transverse shear flow of the acid. The acid is introduced from the container 1423 through a flow port 1433 above the membrane 1410. From the flow port 1433, the acid passes through the CIRP 1414 and generates a shock flow over the surface of the substrate package 1404 (eg, on top of the bump 114) to remove the bump 114 to generate the top surface 120 of the RDL layer 104 (FIG. 1B) ). The acid is introduced into the flow port 1430 from the container 1423 via the pump 1424. The functional result is that the acid flow system directly introduces the area formed between the CIRP 1414 and the substrate package 1404 to enhance the lateral shear flow of the entire substrate package 1404, as shown by the arrow direction 1407 in FIG. 14B. The transverse shear flow is applied between the adjacent areas A1 and A2 to the bumps 114 between the flush layers LL1 and LL2 to remove the bumps 114 to further generate the flush layer LL3.

It should be noted that when the electrodeposition operation 168 (FIG. 1B) is performed on the substrate package 1404, the substrate package 1404 is an example of the substrate package 135. In addition, it should be noted that when the electro-polishing operation 170 (FIG. 1B) is performed on the substrate package 1404, the substrate package 1404 is an example of the substrate package 141 (FIG. 1B).

The embodiments described herein can be implemented using a variety of computer system configurations including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, mini computers, mainframe computers Wait. The embodiments may also be implemented in a decentralized computing environment where tasks are performed by remote processing hardware units linked via a network.

In some embodiments, the controller is part of the system, which may be part of the example described above. These systems include semiconductor processing equipment that includes more than one processing tool, more than one chamber, more than one platform for processing, and / or specific processing elements (wafer pedestals, airflow systems, etc.). These systems are integrated with electronic equipment that is used to control the operation of these systems before, during, and after the processing of semiconductor wafers or substrates. Electronic devices are called "controllers" and they can control various elements or sub-parts of the system. Depending on the processing needs and / or type of system, the controller is programmed to control any process disclosed herein, including: process gas delivery, temperature settings (such as heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, access to a tool and other transfer tools, and / or wafer transfer of a load lock section connected or interfacing with the system .

Broadly speaking, in various embodiments, the controller is defined as an electronic device with various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, and enables terminals. Point measurement and so on. An integrated circuit includes a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an ASIC, a PLD, and / or one or more microprocessors or microcontrollers that execute program instructions (such as software) Device. These program instructions are instructions that communicate with the controller in the form of various individual settings (or program files). These settings define operating parameters for the semiconductor wafer or system to perform a specific process. In some embodiments, the operating parameters are part of a recipe defined by a process engineer to one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafers More than one processing step is completed during the fabrication of the die.

In some embodiments, the controller is part of or coupled to a computer, the computer is integrated with the system, coupled to the system, networked to the system in other ways, or a combination of the above. For example, the controller is in the "cloud" or the whole or part of the fab host computer system, allowing remote access to wafer processing. The computer allows remote access to the system to monitor the current progress of manufacturing operations, check the history of past manufacturing operations, check trends or performance metrics from multiple manufacturing operations, change the parameters currently being processed, and set the Process steps, or start a new process.

In some embodiments, a remote computer (eg, a server) provides the process recipe to the system via a network, which includes a local area network or the Internet. The remote computer includes a user interface that allows input or programming of parameters and / or settings that are then passed from the remote computer to the system. In some examples, the controller receives instructions in the form of data specifying parameters for various processing steps to be performed during one or more operations. It should be understood that these parameters are specific to the type of process to be performed and the type of tool that the controller is configured to interface or control. Therefore, as described above, the controllers are decentralized, such as by including more than one decentralized controller, which are connected together by a network and operate toward a common purpose, such as the processes and controls described herein. An example of a decentralized controller for these purposes includes more than one integrated circuit on a chamber that communicates with more than one integrated circuit at a remote location, such as at the platform level or as part of a remote computer, which combines Control the process in the chamber.

In various embodiments, without limitation, the example system includes a plasma etching chamber or module, a deposition chamber or module, a spin-rinsing chamber or module, a metal plating chamber or module, a cleaning chamber Chamber or module, beveled etch chamber or module, physical vapor deposition (PVD) chamber or module, chemical vapor deposition (CVD) chamber or module, atomic layer deposition (ALD) chamber or mold Groups, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, orbital chambers or modules, and any other semiconductor processing associated with or used in the manufacture and / or production of semiconductor wafers system.

It is further noted that in some embodiments, the above operations can be applied to some types of plasma chambers, for example: including inductively coupled plasma (ICP) reactors, transformer coupled plasma reactors, capacitively coupled plasma reactors, conductor tools , Plasma chambers for dielectric tools; plasma chambers containing electron cyclotron resonance (ECR) reactors, etc. For example, more than one RF generator is coupled to an inductor within the ICP reactor. Examples of the shape of the inductor include a spiral, a dome-shaped coil, a flat coil, and the like.

As mentioned above, based on more than one process step to be performed by the tool, the controller communicates with one or more other tool circuits or modules, other tool components, group tools, other tool interfaces, adjacent tools, adjacent tools, , A host computer, another controller, or a tool for material transfer. These tools for material transfer carry a wafer container into and out of a tool location and / or load end within a semiconductor manufacturing plant.

After considering the above embodiments, it should be understood that some embodiments use various computer-implementable operations including data stored in a computer system. These operations are physical quantities that are physically manipulated. Any operations described herein that form part of these embodiments are useful mechanical operations.

Some embodiments are also related to a hardware unit or device for performing these operations. This device is specially constructed for special purpose computers. When defined as a special-purpose computer, the computer performs other processes, program execution, or common programs that are not part of the special-purpose computer, but can still operate for the special purpose.

In some embodiments, these operations may be processed by a computer that is selectively activated or configured by one or more computer programs stored in computer memory, cache memory, or obtained through a computer network . When data is obtained through a computer network, the data can be processed by other computers on the computer network, such as cloud computing resources.

One or more embodiments may also be made as computer-readable codes on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit (such as a memory device, etc.) that stores data, and the data is then read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc ROM (CD-ROM), recordable discs (CD-R), and read-write discs (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium includes computer-readable physical media dispersed in a network coupled computer system, so that the computer-readable codes are stored and executed in a decentralized manner.

Although the above method operations are described in a specific order, it should be understood that in various embodiments, other housekeeping tasks are performed between operations, or the method operations are adjusted such that the operations occur at slightly different times The points are either dispersed in a system that allows such method operations to occur over various time intervals, or performed in a different order than described above.

It should be further noted that in one embodiment, more than one feature from any of the above embodiments may be combined with more than one feature of any other embodiment without departing from the scope of the various embodiments described in this disclosure.

Although the above embodiments have been described in some details for the purpose of clear understanding, it is obvious that certain changes and modifications can be implemented within the scope of the accompanying patent application. Accordingly, the embodiments of the present invention are to be considered as illustrative and not restrictive, and the embodiments are not limited to the details given herein, but may be included within the scope and equivalents of the scope of the accompanying patent application modify.

A1‧‧‧Area
A2‧‧‧ area
A3‧‧‧ area
A4‧‧‧ area
A5‧‧‧Area
LL1‧‧‧Flat floor
LL2‧‧‧Flat floor
LL3‧‧‧Flat area (Flat floor)
LVL1‧‧‧level
LVL2‧‧‧level
P1‧‧‧Pattern
P2‧‧‧ pattern
P3‧‧‧ pattern
P4‧‧‧ pattern
100‧‧‧ Method
102‧‧‧ substrate
103‧‧‧ Substrate Package
104‧‧‧ Redistribution Layer (RDL)
105‧‧‧ substrate package
106‧‧‧through hole
107‧‧‧ Substrate package
108‧‧‧Photoresistive layer
109‧‧‧ substrate package
110‧‧‧area
112‧‧‧Conductive materials
114‧‧‧ bump
116‧‧‧level
117‧‧‧level
118‧‧‧level
120‧‧‧ top surface
122‧‧‧ cushion
123‧‧‧Barrier and seed layer
124‧‧‧ Dielectric layer
124A‧‧‧ middle section
124B‧‧‧ Middle Section
128‧‧‧part
130‧‧‧part
132A‧‧‧part
132B‧‧‧part
134A‧‧‧ fragment
134B‧‧‧ fragment
135‧‧‧ substrate package
136A‧‧‧part
136B‧‧‧part
136C‧‧‧Part
137‧‧‧Substrate package
138A‧‧‧part
138B‧‧‧part
139‧‧‧ substrate package
141‧‧‧Substrate package
150‧‧‧ operation
152‧‧‧Operation
154‧‧‧Through Hole
156‧‧‧part
158‧‧‧operation
160‧‧‧ Operation
162‧‧‧Operation
164‧‧‧Slag removal operation
166‧‧‧Pre-processing operation
168‧‧‧electrodeposition operation
170‧‧‧operation
172‧‧‧Operation
174‧‧‧Barrier and seed layer etching operations
176‧‧‧operation
182A‧‧‧Part
182B‧‧‧part
182C‧‧‧Part
182D‧‧‧part
200‧‧‧ Method
300‧‧‧ Substrate Package
302‧‧‧ lower surface
400‧‧‧ substrate package
402‧‧‧ uneven
403‧‧‧top surface
404A‧‧‧ surface
404B‧‧‧ surface
404C‧‧‧ surface
406‧‧‧ uneven
500‧‧‧ substrate package
502‧‧‧ Dielectric layer
503‧‧‧ substrate package
504‧‧‧through hole
506‧‧‧RDL layer
507‧‧‧Top surface
600‧‧‧ substrate package
602‧‧‧ Dielectric layer
603‧‧‧ substrate package
604‧‧‧Through Hole
606‧‧‧RDL layer
700‧‧‧Integrated Circuit Stack
702‧‧‧Top Integrated Circuit (IC) Package
704‧‧‧Bottom IC Package
706A‧‧‧Chip System (SoC)
706B‧‧‧SoC
708‧‧‧SoC
710‧‧‧Substrate package
712‧‧‧UBM
714‧‧‧columns
716‧‧‧RDL
718‧‧‧Big Pillar
800‧‧‧ system
802‧‧‧rotator
804‧‧‧Host computer
806‧‧‧Motor
808‧‧‧Vacuum pump
810‧‧‧Liquid reservoir
812‧‧‧valve
814‧‧‧ surface
815‧‧‧substrate package
816‧‧‧Support
900‧‧‧ Wafer Stepper
902‧‧‧light source
904‧‧‧Lens
906‧‧‧light mask
908‧‧‧ projection lens
910‧‧‧ substrate holder
1000‧‧‧ immersed container
1100‧‧‧ system
1102‧‧‧Radio Frequency Generator (RFG)
1104‧‧‧Impedance Matching Circuit (IMC)
1106‧‧‧ Plasma Chamber
1108‧‧‧container
1112‧‧‧RFG
1114‧‧‧IMC
1116‧‧‧Vacuum Pump
1120‧‧‧chuck
1122‧‧‧Top plate
1123‧‧‧ Valve
1124‧‧‧Substrate Package
1126‧‧‧RF cable
1128‧‧‧RF transmission line
1130‧‧‧RF cable
1132‧‧‧RF transmission line
1200‧‧‧System
1202‧‧‧ Plasma Chamber
1204‧‧‧container
1205‧‧‧container
1206‧‧‧ Valve
1207‧‧‧valve
1208‧‧‧Substrate Package
1210‧‧‧Sprinkler
1300‧‧‧ system
1302‧‧‧ Chamber
1304‧‧‧ Motor
1306‧‧‧container
1308‧‧‧Wafer Holder
1310‧‧‧ Valve
1312‧‧‧Board Package
1320‧‧‧System
1322‧‧‧ Chamber
1324‧‧‧Chuck
1400‧‧‧system
1401‧‧‧System
1402‧‧‧ side
1404‧‧‧Substrate Package
1406‧‧‧Wafer Holder
1407‧‧‧direction
1408‧‧‧plating tank
1409‧‧‧ Counter electrode
1410‧‧‧ film
1411‧‧‧ Counter electrode
1412‧‧‧Support members
1414‧‧‧Ion Channel Type Resistor Plate (CIRP)
1416‧‧‧ Shunt
1418‧‧‧Rotatable shaft
1420‧‧‧ Chamber
1421‧‧‧ Chamber
1422‧‧‧container
1423‧‧‧container
1424‧‧‧Pump
1430‧‧‧Mobile port
1432‧‧‧ sidewall
1433‧‧‧Mobile port
1434‧‧‧DC Power Supply

These embodiments can be best understood by referring to the following description in conjunction with the accompanying drawings.

FIG. 1A is a diagram illustrating an embodiment of a method of manufacturing a redistribution layer (RDL) on a substrate.

FIG. 1B is a diagram illustrating an embodiment of a method of continuously manufacturing an RDL layer.

FIG. 2 is a diagram illustrating an embodiment of a method of manufacturing an RDL layer on a substrate.

FIG. 3 is a diagram of an embodiment of a substrate package to illustrate an RDL layer including bumps.

FIG. 4 is a diagram of an embodiment of a substrate package to illustrate the unevenness in the top RDL layer caused by the unevenness in the bottom RDL layer.

5 is a diagram of an embodiment of a substrate package to illustrate an RDL layer with minimal or no unevenness on the top surface of the RDL layer.

FIG. 6 is a diagram of an embodiment of a substrate package to illustrate the deposition of multiple RDL layers on a substrate.

FIG. 7 is a diagram of an embodiment of an integrated circuit stack to illustrate the use of the RDL layer.

FIG. 8 is a diagram of an embodiment of a system including a rotator for depositing a dielectric layer or a photoresist layer on a substrate.

FIG. 9 is a diagram of an embodiment of a wafer stepper for explaining the formation of a pattern on a dielectric layer or a photoresist layer.

FIG. 10 is a diagram of an embodiment of an immersion container to illustrate peeling of a portion of a dielectric layer or a portion of a photoresist layer having a pattern applied thereto.

FIG. 11 is a diagram illustrating an embodiment of a system for a physical vapor deposition (PVD) process.

FIG. 12 is a diagram of an embodiment of a system for performing a photoresist stripping operation, or a slag removing operation, or an operation of barrier and seed layer etching.

FIG. 13A is a diagram of an embodiment of a system for performing a pre-processing operation.

FIG. 13B is a diagram of an embodiment of another system for performing a pre-processing operation.

FIG. 14A is a diagram for explaining an embodiment of a system of an electrodeposition operation.

FIG. 14B is a diagram for explaining an embodiment of a system for an electropolishing operation.

A1‧‧‧Area

A2‧‧‧ area

LL1‧‧‧Flat floor

LL2‧‧‧Flat floor

LL3‧‧‧Flat area (Flat floor)

102‧‧‧ substrate

104‧‧‧ Redistribution Layer (RDL)

106‧‧‧through hole

108‧‧‧Photoresistive layer

110‧‧‧area

112‧‧‧Conductive materials

114‧‧‧ bump

116‧‧‧level

117‧‧‧level

118‧‧‧level

120‧‧‧ top surface

122‧‧‧ cushion

123‧‧‧Barrier and seed layer

124‧‧‧ Dielectric layer

130‧‧‧part

132A‧‧‧part

132B‧‧‧part

134A‧‧‧ fragment

134B‧‧‧ fragment

135‧‧‧ substrate package

136A‧‧‧part

136B‧‧‧part

137‧‧‧Substrate package

138A‧‧‧part

138B‧‧‧part

139‧‧‧ substrate package

141‧‧‧Substrate package

160‧‧‧ Operation

162‧‧‧Operation

164‧‧‧Slag removal operation

166‧‧‧Pre-processing operation

168‧‧‧electrodeposition operation

170‧‧‧Electric polishing operation

172‧‧‧Photoresistive stripping operation

174‧‧‧Barrier and seed layer etching operations

176‧‧‧operation

Claims (20)

A method for processing a substrate to improve the topographic uniformity of a redistribution layer over a through hole, comprising: patterning a photoresist layer over the substrate, the patterning step defining a region for a wire, the wire It is a layer of the redistribution layer; a conductive material is deposited so that the conductive material fills the area of the through hole and the wire, and the deposition step is further controlled to cause the conductive material of the wire to overgrow in the through hole A bump of the conductive material is formed directly above; the wires and the bumps are planarized, and at the same time the patterned photoresist layer existing on the substrate is maintained, and the step of planarizing is performed on the wires and A liquid chemical is applied to the bump to assist in the horizontal shearing force; and the photoresist is peeled off after performing the planarization step. For example, the method for processing a substrate to improve the topographic uniformity of a redistribution layer over a through hole in the scope of patent application, further comprising: depositing a dielectric material on top of the planarized top surface of the wire Layer; patterning the dielectric material layer to form additional through holes in the dielectric material layer; depositing a barrier and seed layer on top of the patterned dielectric material layer to form the dielectric material layer Forming a barrier and seed film layer on top of the substrate; depositing an additional photoresist layer on top of the barrier and seed film layer including the additional through holes to form a thick layer; and patterning the additional layer The photoresist layer is such that the distance between two adjacent areas of the residual photoresist material of the additional photoresist layer is greater than the maximum width of each additional through hole. For example, the method for processing a substrate to improve the topographic uniformity of a redistribution layer over a through hole in the second patent application scope further includes: depositing an additional conductive layer between the two adjacent areas of the residual photoresist layer Material, wherein the step of depositing the additional conductive material comprises: filling the additional through holes; generating an additional bump between the two adjacent regions of the additional photoresist layer, wherein the additional bump is on the additional A through hole is generated directly above one of the through holes; a flush layer is formed between the additional bump and one of the two adjacent regions of the residual photoresist material; and an additional bump is formed between the additional bump and the two adjacent regions. A flush layer is formed between the other one. For example, the method for processing a substrate to improve the uniformity of the topography of a redistribution layer over a through hole in the third patent application scope further includes: electropolishing the additional bumps generated between the two adjacent regions, To form a flush layer of the additional conductive material between the two adjacent regions. For example, the method for processing a substrate to improve the uniformity of the topography of a redistribution layer above a through-hole, in the scope of the patent application, wherein the step of electropolishing is performed by applying a shear force in a horizontal direction, The horizontal direction is parallel to a layer between the additional bump and the one of the two adjacent areas. For example, the method for processing a substrate to improve the topographic uniformity of a redistribution layer over a through hole in the patent application item 4 further includes stripping the additional photoresist layer after the step of electropolishing the additional bump. . A method for achieving uniformity of a redistribution layer (RDL) includes: depositing a dielectric layer on top of a pad disposed on a substrate; and generating a plurality of through holes in the dielectric layer to Generating a plurality of intermediate portions of the dielectric layer; depositing a barrier and seed layer on top of the dielectric layer to form a film on top of the dielectric layer, wherein the film is on the through holes Formed on and on top of the intermediate portions; depositing a photoresist on top of the film of the seed layer to form a layer over the intermediate portions of the dielectric layer; by removing the light Patterning the plurality of discontinuous areas of the photoresist to expose the plurality of portions of the film deposited within the through holes and the film deposited on fragments of the intermediate portions of the dielectric layer The redistribution layer is deposited on top of the portions of the film deposited within the through holes and on top of the extra portions of the film such that the height of the redistribution layer is Less than the height of the layer formed by the photoresist, wherein the And the height of the layer formed by the photoresist are measured from the substrate, wherein the step of depositing the redistribution layer is performed to overfill the through holes, and overfilling is performed to generate the redistribution layer Bumps, wherein the bumps are generated between the discontinuous areas of the photoresist; and the bumps between the discontinuous areas of the photoresist are removed to achieve uniformity. For example, the method for achieving uniformity of a redistribution layer (RDL) according to item 7 of the patent application scope further includes peeling the photoresist to expose a plurality of portions of the barrier and the seed layer. For example, the method for achieving uniformity of a redistribution layer (RDL) according to item 8 of the patent application scope further includes: etching the portions of the seed layer to expose a barrier layer on top of the dielectric layer The plurality of portions of the barrier layer are etched to expose the plurality of portions of the dielectric layer. For example, the method for achieving uniformity of a redistribution layer (RDL) according to item 7 of the patent application scope, wherein the redistribution layer is made of copper. For example, the method for achieving uniformity of a redistribution layer (RDL) according to item 7 of the patent application scope, wherein the redistribution layer is made of cobalt, or constant steel, or nickel, or an alloy of nickel and cobalt and iron, or It is made by a combination of two or more of them. For example, the method for achieving uniformity of a redistribution layer (RDL) according to item 7 of the application, wherein the step of depositing the redistribution layer includes: the portions of the film deposited within the through holes and the The catholyte is deposited on one side of a chamber by promoting the lateral flow of the catholyte on top of the extra portions of the membrane. For example, the method for achieving uniformity of a redistribution layer (RDL) according to item 12 of the patent application, wherein the catholyte contains an accelerator to overfill the through holes to generate the bumps. For example, the method for achieving uniformity of a redistribution layer (RDL) according to item 12 of the patent application, wherein the catholyte contains a leveling agent to generate a plurality of flush portions of the redistribution layer, wherein the flush portions are One of them is between one of the bumps and one of the discontinuous areas of the photoresist. A method for achieving uniformity of a redistribution layer (RDL), comprising: depositing a photoresist on top of one of a barrier and seed layer film to fill a plurality of through holes and a patterned dielectric layer A layer is formed on top of the plurality of middle portions; the plurality of intermittent portions of the photoresist are patterned by removing the plurality of portions of the photoresist to expose the plurality of portions of the film deposited within the through holes and the A plurality of additional portions of the film deposited on fragments of the intermediate portions of the patterned dielectric layer; depositing the redistribution layer on top of the portions of the film deposited within the through holes and on the On top of the extra portions of the film, the height of the redistribution layer is less than the height of the layer formed by the photoresist, where the height of the redistribution layer and the height of the layer formed by the photoresist are from a substrate It is measured, wherein the step of depositing the redistribution layer is performed to overfill the through holes, wherein the overfilling is performed to generate bumps of the redistribution layer, wherein the bumps are in the photoresist Interstitial areas And removing the region between such intermittent photoresist of the bumps to achieve uniformity. For example, the method for achieving uniformity of a redistribution layer (RDL) according to item 15 of the patent application scope, wherein the redistribution layer is made of copper. For example, a method for achieving uniformity of a redistribution layer (RDL) according to item 15 of the application, wherein the redistribution layer is made of cobalt, or constant steel, or nickel, or an alloy of nickel and cobalt and iron, or It is made by a combination of two or more of them. For example, the method for achieving uniformity of a redistribution layer (RDL) according to item 15 of the application, wherein the step of depositing the redistribution layer includes: the portions of the film deposited within the through holes and the The catholyte is deposited on the top of the additional portion via a side of a chamber by promoting lateral flow of the catholyte. For example, the method for achieving uniformity of a redistribution layer (RDL) according to item 18 of the application, wherein the catholyte contains an accelerator to overfill the through holes to generate the bumps. For example, the method for achieving uniformity of a redistribution layer (RDL) according to item 18 of the application, wherein the catholyte contains a leveling agent to generate a plurality of flush portions of the redistribution layer, wherein the flush portions are One of them is between one of the bumps and one of the discontinuous areas of the photoresist.