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TW201804589A - 封裝結構及其形成方法 - Google Patents

封裝結構及其形成方法 Download PDF

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Publication number
TW201804589A
TW201804589A TW105137441A TW105137441A TW201804589A TW 201804589 A TW201804589 A TW 201804589A TW 105137441 A TW105137441 A TW 105137441A TW 105137441 A TW105137441 A TW 105137441A TW 201804589 A TW201804589 A TW 201804589A
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Taiwan
Prior art keywords
die
package
forming
redistribution structure
layer
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TW105137441A
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English (en)
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TWI610412B (zh
Inventor
余振華
蘇安治
吳集錫
葉德強
陳憲偉
曾華偉
黃立賢
Original Assignee
台灣積體電路製造股份有限公司
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Publication of TWI610412B publication Critical patent/TWI610412B/zh
Publication of TW201804589A publication Critical patent/TW201804589A/zh

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Abstract

一實施例為一種結構,包含:第一晶粒;模製化合物,至少側向地密封第一晶粒;第一重佈線結構,包含在第一晶粒及模製化合物上方延伸的金屬化圖案;第一導電連接件,包括耦接至第一重佈線結構的焊球及凸塊下金屬化物;以及積體被動元件,藉由微型凸塊接合接頭接合至第一重佈線結構中的第一金屬化圖案,積體被動元件鄰近第一導電連接件。

Description

封裝結構及其形成方法
本發明實施例是有關於一種半導體結構及其形成方法,且特別是有關於一種封裝結構及其形成方法。
歸因於進行中的多種電子組件(例如,電晶體、二極體、電阻器、電容器等)的整合密度改良,半導體行業經歷了快速發展。整合密度的改良主要源自於最小特徵大小的反覆縮減,其允許更多組件整合至給定區域中。隨著對於縮小的電子元件的需求增長,對於更小且更具創造性的半導體晶粒的封裝技術的需要已出現。此等封裝系統的一實例為疊層封裝(Package-on-Package;PoP)技術。在PoP元件中,頂部半導體封裝堆疊於底部半導體封裝的頂部上,以提供高位準的整合及組件密度。PoP技術大體上使得能夠生產具有增強的功能性及印刷電路板(printed circuit board;PCB)上的小佔據面積的半導體元件。
一種封裝結構,所述結構包含:第一晶粒;模製化合物,其至少側向地密封所述第一晶粒;第一重佈線結構,其包含在所述第一晶粒及所述模製化合物上方延伸的金屬化圖案;第一導電連接件,其包括耦接至所述第一重佈線結構的焊球及凸塊下金屬化物;以及積體被動元件,其藉由微型凸塊接合接頭接合至所述第一重佈線結構中的第一金屬化圖案,所述積體被動元件鄰近所述第一導電連接件。
一種封裝結構的形成方法,所述方法包含:形成第一封裝,其包含:在載體基底上方形成電連接件;將第一晶粒附接至所述載體基底,所述電連接件自所述第一晶粒的第二側延伸至所述第一晶粒的第一側,所述第二側與所述第一側對置,所述電連接件鄰近所述第一晶粒;運用模製化合物密封所述第一晶粒及所述電連接件;形成上覆於所述第一晶粒的所述第一側及所述模製化合物的重佈線結構,所述重佈線結構包括金屬化圖案;將包括凸塊下金屬化物的第一導電連接件耦接至所述重佈線結構的第一金屬化圖案;以及藉由接合接頭將積體被動元件接合至所述重佈線結構的第二金屬化圖案。
一種封裝結構的形成方法,所述方法包含:形成鄰近第一晶粒的第一穿孔,所述第一穿孔自所述第一晶粒的第二側延伸至所述第一晶粒的第一側,所述第二側與所述第一側對置;運用模製材料密封所述第一穿孔及所述第一晶粒;在所述第一晶粒的所述第一側、所述第一穿孔以及所述模製材料上方形成第一重佈線結構,所述第一重佈線結構包括多個金屬化圖案及多個介電層;在所述第一重佈線結構的第一介電層上方且穿過所述第一介電層形成第一凸塊下金屬化物,以接觸所述第一重佈線結構的第一金屬化圖案;以及藉由接合接頭將積體被動元件接合至所述第一重佈線結構的第二金屬化圖案,所述接合接頭延伸穿過所述第一重佈線結構的所述第一介電層。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。下文描述組件以及配置的特定實例以簡化本發明。當然,此等組件以及配置僅為實例且不意欲為限制性的。舉例而言,在以下描述中,第一特徵在第二特徵上方或上的形成可包含第一特徵與第二特徵直接接觸地形成的實施例,且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外,本發明可在各種實例中重複參考數字及/或字母。此重複是出於簡化以及清楚的目的,且本身並不指示所論述各種實施例及/或組態之間的關係。
此外,諸如,「在……下」、「在……之下」、「下部」、「在……上方」、「上部」以及其類似者的空間相對術語在本文中為了易於描述而用以描述如圖式中所說明的一個元件或特徵與另一元件或特徵的關係。除圖式中所描繪的定向以外,空間相對術語意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向),且本文中所使用的空間相對描述詞同樣可相應地進行解釋。
本文中所論述的實施例可在特定內容背景中加以論述,亦即,包含增加系統效能且放大製程裕度(process window)以改良封裝結構的可靠性及產率的積體被動元件(integrated passive device;IPD)設計的封裝結構。封裝結構可包含扇出型或扇入型封裝,且可包含一或多個重佈線層(redistribution layer;RDL)。IPD組件可接合至封裝結構的一或多個RDL。IPD組件可接合至鄰近將兩個封裝/基底耦接且接合在一起的導電接頭的一或多個RDL。鄰近導電接頭可包含在一或多個RDL上的凸塊下金屬化物(under bump metallization;UBM)及耦接至UBM的焊接接頭。IPD組件可在無任何UBM的情況下接合至一或多個RDL。IPD組件可藉由包含焊料層的微型凸塊接頭接合且電耦接至RDL的導電層中的一者。在一些實施例中,IPD組件可包括電容器、電阻器、電感器、其類似者,或其組合。
在一些實施例中,IPD組件包含額外後段製程(extra back-end-of-line;BEOL)金屬佈線以進一步提高系統效能。然而,在具有額外金屬佈線的情況下,IPD組件的高度可變為關於板級聯合產率(board level joint yield)的問題。因此,藉由移除IPD組件接頭區域下方的UBM,縮減了IPD組件的總高度且放大了製程裕度。
可利用雷射鑽孔或微影製程以在鈍化或聚合物層中形成開口,來曝光IPD組件將接合至的RDL的導電層。另外,可利用IPD組件的底填充料的完全填充、部分填充以及無填充以防止污染且改良可靠性。
此外,本發明的教示適用於包含IPD組件的任何封裝結構。其他實施例預期其他應用,諸如,一般熟習此項技術者在閱讀本發明後即將顯而易見的不同封裝類型或不同組態。應注意,本文中所論述的實施例可不必說明可呈現於結構中的每一組件或特徵。舉例而言,諸如,當對組件中的一者的論述可充分傳達實施例的態樣時,可自圖式省略多個組件。此外,可將本文中所論述的方法實施例論述為以特定次序予以執行;然而,其他方法實施例可以任何邏輯次序予以執行。
圖1至圖18、圖20以及圖23至圖26說明根據一些實施例的在用於形成封裝結構的製程期間的中間步驟的橫截面圖。圖1說明載體基底100及形成於載體基底100上的釋放層102。說明分別用於形成第一封裝及第二封裝的第一封裝區600以及第二封裝區602。
載體基底100可為玻璃載體基底、陶瓷載體基底或其類似者。載體基底100可為晶圓,使得多個封裝可在載體基底100上同時形成。釋放層102可由聚合物類材料形成,可將其連同載體基底100一起自將在後續步驟中形成的上覆結構移除。在一些實施例中,釋放層102為在加熱時損失其黏著特性的環氧樹脂類熱釋放材料,諸如,光-熱轉換(light-to-heat-conversion;LTHC)釋放塗層。在其他實施例中,釋放層102可為在曝光於紫外線(ultra-violet;UV)光時損失其黏著特性的UV黏膠。釋放層102可配製為液體並經固化,釋放層102可為疊層至載體基底100上的疊層膜,或可為其類似者。釋放層102的頂部表面可經水平化,且可具有高度共面性。
在圖2中,形成介電層104及金屬化圖案106。如在圖2中所說明,介電層104形成於釋放層102上。介電層104的底部表面可與釋放層102的頂部表面接觸。在一些實施例中,介電層104由聚合物形成,諸如,聚苯并噁唑(polybenzoxazole;PBO)、聚醯亞胺、苯環丁烷(benzocyclobutene;BCB),或其類似者。在其他實施例中,介電層104由以下各者形成:氮化物,諸如,氮化矽;氧化物,諸如,氧化矽、磷矽酸鹽玻璃(phosphosilicate glass;PSG)、硼矽酸鹽玻璃(borosilicate glass;BSG)、硼摻磷矽酸鹽玻璃(boron-doped phosphosilicate glass;BPSG)或其類似者;或其類似者。介電層104可藉由任何可接受沈積製程形成,諸如,旋轉塗佈、化學氣相沈積(chemical vapor deposition;CVD)、疊層、其類似者,或其組合。
金屬化圖案106形成於介電層104上。作為形成金屬化圖案106的一實例,晶種層(未圖示)形成於介電層104上方。在一些實施例中,晶種層為金屬層,金屬層可為包括由不同材料形成的多個子層的單層或複合層。在一些實施例中,晶種層包括鈦層及在鈦層上方的銅層。可使用(例如)PVD或其類似者形成晶種層。接著在晶種層上形成並圖案化光阻劑。光阻劑可藉由旋轉塗佈或其類似者形成且可曝光於光以用於圖案化。光阻劑的圖案對應於金屬化圖案106。圖案化形成穿過光阻劑的開口以曝光晶種層。導電材料形成於光阻劑的開口中且形成於晶種層的經曝光部分上。導電材料可藉由鍍覆形成,諸如,電鍍或化學鍍敷,或其類似者。導電材料可包括金屬,類似銅、鈦、鎢、鋁,或其類似者。接著,移除上方未形成導電材料的光阻劑以及晶種層的部分。可藉由可接受灰化或剝離製程移除光阻劑,諸如,使用氧電漿或其類似者。一旦移除光阻劑,則(諸如)藉由使用可接受蝕刻製程(諸如,藉由濕式或乾式蝕刻)移除晶種層的經曝光部分。晶種層以及導電材料的剩餘部分形成金屬化圖案106。
在圖3中,介電層108形成於金屬化圖案106以及介電層104上。在一些實施例中,介電層108由聚合物形成,聚合物可為可使用微影罩幕予以圖案化的感光性材料,諸如,PBO、聚醯亞胺、BCB,或類似者。在其他實施例中,介電層108由以下各者形成:氮化物,諸如,氮化矽;氧化物,諸如,氧化矽、PSG、BSG、BPSG;或其類似者。介電層108可藉由旋轉塗佈、疊層、CVD、其類似者或其組合形成。接著圖案化介電層108以形成開口來曝光金屬化圖案106的部分。圖案化可藉由可接受製程,諸如,藉由在介電層為感光性材料時將介電層108曝光於光或藉由使用(例如)各向異性蝕刻進行蝕刻。
介電層104及108以及金屬化圖案106可被稱作背側重佈線結構110。如所說明,背側重佈線結構110包含兩個介電層104及108以及一個金屬化圖案106。在其他實施例中,背側重佈線結構110可包含任何數目個介電層、金屬化圖案以及通孔。一或多個額外金屬化圖案及介電層可藉由重複用於形成金屬化圖案106及介電層108的製程而在背側重佈線結構110中形成。可在形成金屬化圖案期間藉由在下伏介電層的開口中形成金屬化圖案的晶種層及導電材料而形成通孔。通孔可因此互連且電耦接各種金屬化圖案。
此外,在圖3中,形成穿孔112。作為形成穿孔112的一實例,晶種層形成於背側重佈線結構110(例如,如所說明的介電層108及金屬化圖案106的經曝光部分)上方。在一些實施例中,晶種層為金屬層,金屬層可為包括由不同材料形成的多個子層的單層或複合層。在一些實施例中,晶種層包括鈦層及在鈦層上方的銅層。可使用(例如)PVD或其類似者形成晶種層。光阻劑在晶種層上形成且經圖案化。光阻劑可藉由旋轉塗佈或其類似者形成且可曝光於光以用於圖案化。光阻劑的圖案對應於穿孔。圖案化形成穿過光阻劑的開口以曝光晶種層。導電材料形成於光阻劑的開口中且形成於晶種層的經曝光部分上。導電材料可藉由鍍覆形成,諸如,電鍍或化學鍍敷,或其類似者。導電材料可包括金屬,類似銅、鈦、鎢、鋁,或其類似者。移除上方未形成導電材料的光阻劑及晶種層的部分。可藉由可接受灰化或剝離製程移除光阻劑,諸如,使用氧電漿或其類似者。一旦移除光阻劑,則(諸如)藉由使用可接受蝕刻製程(諸如,藉由濕式或乾式蝕刻)移除晶種層的經曝光部分。晶種層及導電材料的剩餘部分形成穿孔112。
在圖4中,積體電路晶粒114藉由黏著劑116黏附至介電層108。如在圖4中所說明,兩個積體電路晶粒114黏附於第一封裝區600以及第二封裝區602中的每一者中,且在其他實施例中,更多或更少積體電路晶粒114可黏附於各區域中。積體電路晶粒114可為邏輯晶粒(例如,中央處理單元、微控制器等)、記憶體晶粒(例如,動態隨機存取記憶體(dynamic random access memory;DRAM)晶粒、靜態隨機存取記憶體(static random access memory;SRAM)晶粒等)、功率管理晶粒(例如,功率管理積體電路(power management integrated circuit;PMIC)晶粒)、射頻(radio frequency;RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system;MEMS)晶粒、信號處理晶粒(例如,數位信號處理(digital signal processing;DSP)晶粒)、前端晶粒(例如,類比前端(analog front-end;AFE)晶粒)、其類似者,或其組合。又,在一些實施例中,積體電路晶粒114可為不同大小(例如,不同高度及/或表面積),且在其他實施例中,積體電路晶粒114可為相同大小(例如,相同高度及/或表面積)。
在黏附至介電層108之前,可根據適用製造製程處理積體電路晶粒114,以在積體電路晶粒114中形成積體電路。舉例而言,積體電路晶粒114各自包含半導體基底118,諸如,經摻雜或未經摻雜矽或絕緣層上半導體(semiconductor-on-insulator;SOI)基底的主動層。半導體基底可包含其他半導體材料,諸如,鍺;化合物半導體,其包含碳化矽、鎵化砷、磷化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP;或其組合。亦可使用其他基底,諸如多層或梯度基底。諸如電晶體、二極體、電容器、電阻器等的元件可形成於半導體基底118中及/或形成於半導體基底118上,且可藉由由(例如)半導體基底118上的一或多個介電層中的金屬化圖案形成的互連結構120互連,以形成積體電路。
積體電路晶粒114進一步包括墊122(諸如,鋁墊),對墊122進行外部連接。墊122在可被稱作積體電路晶粒114的各別主動側的物件上。鈍化膜124在積體電路晶粒114上且在墊122的部分上。開口穿過鈍化膜124至墊122。晶粒連接件126(諸如,(例如,包括諸如銅的金屬的)導電柱)在穿過鈍化膜124的開口中,且機械地且電耦接至各別墊122。晶粒連接件126可藉由(例如)鍍敷或其類似者形成。晶粒連接件126電耦接積體電路晶粒114的各別積體電路。
介電材料128在積體電路晶粒114的主動側上,諸如,在鈍化膜124及晶粒連接件126上。介電材料128側向地密封晶粒連接件126,且介電材料128與各別積體電路晶粒114側向地相連。介電材料128可為聚合物,諸如,PBO、聚醯亞胺、BCB或其類似者;氮化物,諸如,氮化矽或其類似者;氧化物,諸如,氧化矽、PSG、BSG、BPSG或其類似者;其類似者;或其組合,且可(例如)藉由旋轉塗佈、疊層、CVD或其類似者形成。
黏著劑116在積體電路晶粒114的背側上,且將積體電路晶粒114黏附至背側重佈線結構110,諸如,說明中的介電層108。黏著劑116可為任何適合的黏著劑、環氧樹脂、晶粒貼合膜(die attach film;DAF),或其類似者。黏著劑116可經塗覆至積體電路晶粒114的背側(諸如,經塗覆至各別半導體晶圓的背側),或可於載體基底100的表面上方塗覆。可(諸如)藉由切割(sawing or dicing)而使積體電路晶粒114單一化,且使用(例如)拾放工具藉由黏著劑116將積體電路晶粒114黏附至介電層108。
在圖5中,密封體130形成於各種組件上。密封體130可為模製化合物、環氧樹脂或其類似者,且可藉由壓縮模製、轉移模製或其類似者予以塗覆。在固化之後,密封體130可經歷研磨製程以曝光穿孔112以及晶粒連接件126。在研磨製程之後,穿孔112的頂部表面、晶粒連接件126的頂部表面與密封體130的頂部表面共面。在一些實施例中,可(例如)在穿孔112以及晶粒連接件126已曝光的情況下省略研磨。
在圖6至圖16中,形成前側重佈線結構160。如將在圖16中所說明,前側重佈線結構160包含介電層132、140、148以及156,及金屬化圖案138、146以及154。
在圖6中,介電層132沈積於密封體130、穿孔112以及晶粒連接件126上。在一些實施例中,介電層132由聚合物形成,聚合物可為可使用微影罩幕予以圖案化的感光性材料,諸如,PBO、聚醯亞胺、BCB,或其類似者。在其他實施例中,介電層132由以下各者形成:氮化物,諸如,氮化矽;氧化物,諸如,氧化矽、PSG、BSG、BPSG;或其類似者。介電層132可藉由旋轉塗佈、疊層、CVD、其類似者或其組合形成。
在圖7中,接著圖案化介電層132。圖案化形成開口以曝光穿孔112及晶粒連接件126的部分。圖案化可藉由可接受製程,諸如,藉由在介電層132為感光性材料時將介電層132曝光於光或藉由使用(例如)各向異性蝕刻進行蝕刻。若介電層132為感光性材料,則介電層132可在曝光之後顯影。
在圖8中,具有通孔的金屬化圖案138形成於介電層132上。作為形成金屬化圖案138的一實例,晶種層(未圖示)形成於介電層132上方,且形成於穿過介電層132的開口中。在一些實施例中,晶種層為金屬層,金屬層可為包括由不同材料形成的多個子層的單層或複合層。在一些實施例中,晶種層包括鈦層及在鈦層上方的銅層。可使用(例如)PVD或其類似者形成晶種層。接著在晶種層上形成並圖案化光阻劑。光阻劑可藉由旋轉塗佈或其類似者形成且可曝光於光以用於圖案化。光阻劑的圖案對應於金屬化圖案138。圖案化形成穿過光阻劑的開口以曝光晶種層。導電材料形成於光阻劑的開口中且形成於晶種層的經曝光部分上。導電材料可藉由鍍覆形成,諸如,電鍍或化學鍍敷,或其類似者。導電材料可包括金屬,類似銅、鈦、鎢、鋁,或其類似者。接著,移除上方未形成導電材料的光阻劑及晶種層的部分。可藉由可接受灰化或剝離製程移除光阻劑,諸如,使用氧電漿或其類似者。一旦移除光阻劑,則(諸如)藉由使用可接受蝕刻製程(諸如,藉由濕式或乾式蝕刻)移除晶種層的經曝光部分。晶種層及導電材料的剩餘部分形成金屬化圖案138及通孔。通孔形成於穿過介電層132至(例如)穿孔112及/或晶粒連接件126的開口中。
在圖9中,介電層140沈積於金屬化圖案138及介電層132上。在一些實施例中,介電層140由聚合物形成,聚合物可為可使用微影罩幕予以圖案化的感光性材料,諸如,PBO、聚醯亞胺、BCB,或其類似者。在其他實施例中,介電層140由以下各者形成:氮化物,諸如,氮化矽;氧化物,諸如,氧化矽、PSG、BSG、BPSG;或其類似者。介電層140可藉由旋轉塗佈、疊層、CVD、其類似者或其組合形成。
在圖10中,接著圖案化介電層140。圖案化形成開口以曝光金屬化圖案138的部分。圖案化可藉由可接受製程,諸如,藉由在介電層為感光性材料時將介電層140曝光於光或藉由使用(例如)各向異性蝕刻進行蝕刻。若介電層140為感光性材料,則介電層140可在曝光之後顯影。
在圖11中,具有通孔的金屬化圖案146形成於介電層140上。作為形成金屬化圖案146的一實例,晶種層(未圖示)形成於介電層140上方,且形成於穿過介電層140的開口中。在一些實施例中,晶種層為金屬層,金屬層可為包括由不同材料形成的多個子層的單層或複合層。在一些實施例中,晶種層包括鈦層及在鈦層上方的銅層。可使用(例如)PVD或其類似者形成晶種層。光阻劑接著在晶種層上形成並經圖案化。光阻劑可藉由旋轉塗佈或其類似者形成且可曝光於光以用於圖案化。光阻劑的圖案對應於金屬化圖案146。圖案化形成穿過光阻劑的開口以曝光晶種層。導電材料形成於光阻劑的開口中且形成於晶種層的經曝光部分上。導電材料可藉由鍍覆形成,諸如,電鍍或化學鍍敷,或其類似者。導電材料可包括金屬,類似銅、鈦、鎢、鋁,或其類似者。接著,移除上方未形成導電材料的光阻劑及晶種層的部分。可藉由可接受灰化或剝離製程移除光阻劑,諸如,使用氧電漿或其類似者。一旦移除光阻劑,則(諸如)藉由使用可接受蝕刻製程(諸如,藉由濕式或乾式蝕刻)移除晶種層的經曝光部分。晶種層及導電材料的剩餘部分形成金屬化圖案146及通孔。通孔形成於穿過介電層140至(例如)金屬化圖案138的部分的開口中。
在圖12中,介電層148沈積於金屬化圖案146及介電層140上。在一些實施例中,介電層148由聚合物形成,聚合物可為可使用微影罩幕予以圖案化的感光性材料,諸如,PBO、聚醯亞胺、BCB,或其類似者。在其他實施例中,介電層148由以下各者形成:氮化物,諸如,氮化矽;氧化物,諸如,氧化矽、PSG、BSG、BPSG;或其類似者。介電層148可藉由旋轉塗佈、疊層、CVD、其類似者或其組合形成。
在圖13中,接著圖案化介電層148。圖案化形成開口以曝光金屬化圖案146的部分。圖案化可藉由可接受製程,諸如,藉由在介電層為感光性材料時將介電層148曝光於光或藉由使用(例如)各向異性蝕刻進行蝕刻。若介電層148為感光性材料,則介電層148可在曝光之後顯影。
在圖14中,具有通孔的金屬化圖案154形成於介電層148上。作為形成金屬化圖案154的一實例,晶種層(未圖示)形成於介電層148上方,且形成於穿過介電層148的開口中。在一些實施例中,晶種層為金屬層,金屬層可為包括由不同材料形成的多個子層的單層或複合層。在一些實施例中,晶種層包括鈦層及在鈦層上方的銅層。可使用(例如)PVD或其類似者形成晶種層。光阻劑接著在晶種層上形成並經圖案化。光阻劑可藉由旋轉塗佈或其類似者形成且可曝光於光以用於圖案化。光阻劑的圖案對應於金屬化圖案154。圖案化形成穿過光阻劑的開口以曝光晶種層。導電材料形成於光阻劑的開口中且形成於晶種層的經曝光部分上。導電材料可藉由鍍覆形成,諸如,電鍍或化學鍍敷,或其類似者。導電材料可包括金屬,類似銅、鈦、鎢、鋁,或其類似者。接著,移除上方未形成導電材料的光阻劑及晶種層的部分。可藉由可接受灰化或剝離製程移除光阻劑,諸如,使用氧電漿或其類似者。一旦移除光阻劑,則(諸如)藉由使用可接受蝕刻製程(諸如,藉由濕式或乾式蝕刻)移除晶種層的經曝光部分。晶種層及導電材料的剩餘部分形成金屬化圖案154及通孔。通孔形成於穿過介電層148至(例如)金屬化圖案146的部分的開口中。
在圖15中,介電層156沈積於金屬化圖案154及介電層148上。在一些實施例中,介電層156由聚合物形成,聚合物可為可使用微影罩幕予以圖案化的感光性材料,諸如,PBO、聚醯亞胺、BCB,或其類似者。在其他實施例中,介電層156由以下各者形成:氮化物,諸如,氮化矽;氧化物,諸如,氧化矽、PSG、BSG、BPSG;或其類似者。介電層156可藉由旋轉塗佈、疊層、CVD、其類似者或其組合形成。
在圖16中,接著圖案化介電層156。圖案化形成開口以曝光金屬化圖案154的部分,以後續地形成墊162。圖案化可藉由可接受製程,諸如,藉由在介電層為感光性材料時將介電層156曝光於光或藉由使用(例如)各向異性蝕刻進行蝕刻。若介電層156為感光性材料,則介電層156可在曝光之後顯影。
前側重佈線結構160經展示為一實例。較多或較少介電層及金屬化圖案可形成於前側重佈線結構160中。若將形成較少介電層及金屬化圖案,則可省略上文所論述的步驟及製程。若將形成較多介電層及金屬化圖案,則可重複上文所論述的步驟及製程。一般熟習此項技術者將容易理解將省略或重複哪些步驟及製程。
在圖17中,墊162形成於前側重佈線結構160的外側上。墊162用以耦接至導電連接件166(參見圖20),且可被稱作凸塊下金屬(under bump metallurgy;UBM)162。在所說明實施例中,穿過開口形成墊162,開口穿過介電層156至金屬化圖案154。作為形成墊162的一實例,晶種層(未圖示)形成於介電層156上方。在一些實施例中,晶種層為金屬層,金屬層可為包括由不同材料形成的多個子層的單層或複合層。在一些實施例中,晶種層包括鈦層及在鈦層上方的銅層。可使用(例如)PVD或其類似者形成晶種層。光阻劑接著在晶種層上形成並經圖案化。光阻劑可藉由旋轉塗佈或其類似者形成且可曝光於光以用於圖案化。光阻劑的圖案對應於墊162。圖案化形成穿過光阻劑的開口以曝光晶種層。導電材料形成於光阻劑的開口中且形成於晶種層的經曝光部分上。導電材料可藉由鍍覆形成,諸如,電鍍或化學鍍敷,或其類似者。導電材料可包括金屬,類似銅、鈦、鎢、鋁,或其類似者。接著,移除上方未形成導電材料的光阻劑及晶種層的部分。可藉由可接受灰化或剝離製程移除光阻劑,諸如,使用氧電漿或其類似者。一旦移除光阻劑,則(諸如)藉由使用可接受蝕刻製程(諸如,藉由濕式或乾式蝕刻)移除晶種層的經曝光部分。晶種層及導電材料的剩餘部分形成墊162。在以不同方式形成墊162的實施例中,可利用較多光阻劑及圖案化步驟。
在圖18中,進一步圖案化介電層156。在一些實施例中,IPD組件170的開口164與墊162的開口同時形成。此圖案化形成開口164以曝光金屬化圖案154的部分,以用於後續地接合IPD 170。圖案化可藉由可接受製程,諸如,藉由在介電層為感光性材料時將介電層156曝光於光或藉由使用(例如)各向異性蝕刻進行蝕刻。若介電層156為感光性材料,則介電層156可在曝光之後顯影。
圖19A至圖19D說明根據一些實施例的開口164的橫截面圖。圖19A說明穿過寬度小於金屬化圖案154的寬度的介電層156的開口164。圖19B說明穿過寬度大於金屬化圖案154的寬度的介電層156的開口164。
圖19C及圖19D說明具有楔形側壁164A的開口164。在圖19C中,開口164藉由微影製程形成,且使得楔形側壁164A平滑。在圖19D中,開口164藉由雷射鑽孔製程形成,且使得楔形側壁164A略微粗糙。開口164的粗糙側壁164A可引起IPD 170的較大黏著及接合強度。
在圖20A中,導電連接件166形成於UBM 162上,且IPD組件170經由開口164接合至金屬化圖案154。IPD組件可使用具有焊料層的微型凸塊接合至金屬化圖案154。在一些實施例中,導電連接件166可在IPD組件接合且安裝至重佈線結構160之前安裝於墊162上。在一些實施例中,導電連接件166可在IPD組件接合且安裝至重佈線結構160之後安裝於墊162上。
IPD組件170可在無任何UBM或墊的情況下接合至前側重佈線結構160的金屬化圖案。藉由移除IPD組件170接頭區域下方的UBM或墊,縮減了IPD組件170的總高度H1。在一些實施例中,相比於接合至UBM或墊的IPD組件,可將自介電層156的頂部表面的IPD組件170高度H1縮減大於20 µm。因此,降低了IPD組件170的背側表面觸碰基底400(參見圖26)的可能性,且放大了包含IPD組件170的封裝結構的製程裕度。
在接合至重佈線結構160之前,IPD組件170可根據用以在IPD組件170中形成被動元件的適用製造製程予以處理。舉例而言,IPD組件各自在IPD組件170的主結構172中包括一或多個被動元件。主結構172可包含基底及/或密封體。在包含基底的實施例中,基底可為半導體基底,諸如經摻雜或未經摻雜矽或SOI基底的主動層。半導體基底可包含其他半導體材料,諸如,鍺;化合物半導體,其包含碳化矽、鎵化砷、磷化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP;或其組合。亦可使用其他基底,諸如多層或梯度基底。被動元件可包含電容器、電阻器、電感器、其類似者,或其組合。被動元件可形成於半導體基底中及/或半導體基底上及/或密封體內,且可藉由互連結構174互連以形成積體被動元件170,互連結構174由(例如)主結構172上的一或多個介電層中的金屬化圖案形成。
IPD組件170進一步包括經形成且耦接至互連件174的微型凸塊176,對互連件174進行外部連接。微型凸塊176具有形成於微型凸塊176的一端上的焊料層或凸塊178,微型凸塊176在前側重佈線結構160與IPD組件170之間形成焊接接頭。相比於習知焊料球,諸如用於球狀柵格陣列(ball grid array;BGA)連接件(參見導電連接件166)中的焊料球(其可具有範圍介於(例如)約150 µm至約300 µm的直徑),微型凸塊具有範圍介於(例如)約10 µm至約40 µm的小得多的直徑。在一些實施例中,微型凸塊可具有約40 µm或更大的間距。
在一些實施例中,無法在接合製程期間將IPD組件170加壓至前側重佈線結構160上。在此等實施例中,IPD組件170的接合可藉由(例如)拾放工具將IPD組件170定位於導電連接件166的位階處開始。接下來,拾放工具將IPD組件170放至開口164及前側重佈線結構160的經曝光金屬化圖案154上。在後續接合製程期間,微型凸塊藉由(例如)回焊製程接合至金屬化圖案154,且由於接合製程,形成電性地且機械地連接IPD組件170的微型凸塊176與封裝的金屬化圖案154的焊接接頭。微型凸塊176的較小大小允許微型凸塊176之間的精密間距且實現高密度連接。
圖20B說明重佈線結構160的一部分、IPD組件170中的一者、UBM 162中的一者以及導電連接件166中的一者的詳細視圖。微型凸塊176及焊料層178具有如自金屬化圖案154的表面所量測的高度H2。UBM 162具有如自金屬化圖案154的表面所量測的高度H3,其中高度H3大於高度H2。在一些實施例中,H2與H3之間的差值可大於20 µm。
返回參考圖20A,導電連接件166可為BGA連接件、焊料球、金屬柱、受控塌陷晶粒連接(controlled collapse chip connection;C4)凸塊、微型凸塊、化學鍍鎳鈀浸金(electroless nickel-electroless palladium-immersion gold technique;ENEPIG)技術形成的凸塊,或其類似者。導電連接件166可包含導電材料,諸如,焊料、銅、鋁、金、鎳、銀、鈀、錫、其類似者或其組合。在一些實施例中,導電連接件166藉由經由諸如蒸發、電鍍、印刷、焊料轉移、植球或其類似者的此等常用方法最初形成焊料層而形成。一旦焊料層已形成於結構上,則可執行回焊以便將材料塑形成所要凸塊形狀。在另一實施例中,導電連接件166為藉由濺鍍、印刷、電鍍、化學鍍敷、CVD或其類似者所形成的金屬柱(諸如,銅柱)。金屬柱可無焊料且具有實質上垂直的側壁。在一些實施例中,金屬頂蓋層(未圖示)形成於金屬柱連接件166的頂部上。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、其類似者或其組合,且可藉由鍍敷製程形成。
圖21A及圖21B說明根據一些實施例的IPD組件170的橫截面圖。在圖21A中,IPD組件170的主結構172包含運用模製材料182所密封的被動元件180,或可在半導體基底172中。被動元件180可包含電容器、電阻器、電感器、其類似者,或其組合。模製材料182可為模製化合物、聚合物、環氧樹脂、氧化矽填充材料、類似者,或其組合。在一些實施例中,基底172可為半導體基底,諸如經摻雜或未經摻雜矽或SOI基底的主動層。半導體基底可包含其他半導體材料,諸如,鍺;化合物半導體,其包含碳化矽、鎵化砷、磷化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP;或其組合。互連結構174在主結構172上的一或多個介電層中包含金屬化圖案,且微型凸塊176及焊料層178耦接至互連結構174。
圖21B中的IPD組件170類似於圖21A中的IPD組件170,除圖21B的互連結構174包含更多金屬化圖案以介電層之外。金屬化圖案及介電層的此增加允許更多功率及地面網路插入於IPD組件170內,以縮減IPD組件170的寄生電容及/或電感,從而可改良IPD組件170的效能。對IPD組件170的此等改良可在更高頻率下為IPD組件170產生更穩定的電壓。
圖22A至圖22C說明根據一些實施例的用於IPD組件170的底填充料方案的橫截面圖。底填充料材料可為環氧樹脂或具有填充劑或助焊劑的聚合物。圖22A說明完全填充底填充料方案,其中底填充料184完全地填充IPD組件170與前側重佈線結構160之間的區域且圍繞微型凸塊176。底填充料184可在附接IPD組件170之後藉由毛細流動製程形成,或可在附接IPD組件170之前藉由適合的沈積或印刷方法形成。
圖22B說明部分填充底填充料方案,其中底填充料184部分地填充IPD組件170與前側重佈線結構160之間的區域,且部分地圍繞微型凸塊176。底填充料184可在附接IPD組件170之後藉由毛細流動製程形成,或可在附接IPD組件170之前藉由適合的沈積或印刷方法形成。
圖22C說明無填充底填充料方案,其中無底填充料填充IPD組件170與前側重佈線結構160之間的區域。
在圖23中,執行載體基底剝離以使載體基底100自背側重佈線結構(例如,介電層104)脫離(剝離)。根據一些實施例,剝離包含將諸如雷射光或UV光的光投影於釋放層102上,以使得釋放層102在光熱下分解且可移除載體基底100。接著翻轉結構且將其置放於膠帶190上。
如在圖23中進一步說明,穿過介電層104形成開口以曝光金屬化圖案106的部分。舉例而言,可使用雷射鑽孔、蝕刻或其類似者形成開口。
在圖24中,藉由沿著(例如)鄰近區600與602之間的切割道區的單一化186來執行單一化製程。在一些實施例中,單一化186包含切割製程、雷射製程或其組合。單一化186將第一封裝區600自第二封裝區602單一化。
圖25說明所得經單一化封裝200,封裝200可來自第一封裝區600或第二封裝區602中的一者。封裝200亦可被稱作積體扇出型(integrated fan-out;InFO)封裝200。在一些實施例中,在將第二封裝300接合至InFO封裝200之後執行單一化製程。
圖26說明包含封裝200(可被稱作第一封裝200)、第二封裝300以及基底400的封裝結構500。第二封裝300包含基底302及耦接至基底302的一或多個堆疊式晶粒308(308A及308B)。基底302可由半導體材料製成,諸如,矽、鍺、金剛石或其類似者。在一些實施例中,亦可使用化合物材料,諸如,矽鍺、碳化矽、鎵化砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、此等的組合及其類似者。另外,基底302可為SOI基底。通常,SOI基底包含諸如磊晶矽、鍺、矽鍺、SOI、絕緣層上矽鍺(silicon germanium on insulator;SGOI)或其組合的半導體材料的層。在一個替代性實施例中,基底302基於諸如玻璃纖維強化樹脂芯的絕緣芯。一個實例芯材料為玻璃纖維樹脂,諸如FR4。芯材料的替代方案包含雙馬來醯亞胺三嗪(bismaleimide-triazine;BT)樹脂,或替代地,其他印刷電路板(PCB)材料或膜。累積膜,諸如味之素累積膜(Ajinomoto build-up film;ABF)或其他疊層物,可用於基底302。
基底302可包含主動及被動元件(未圖示)。如一般熟習此項技術者將認識到,廣泛多種元件,諸如電晶體、電容器、電阻器、此等的組合以及其類似者可用以產生對於半導體封裝300的設計的結構及功能要求。所述元件可使用任何適合的方法形成。
基底302亦可包含金屬化層(未圖示)及穿孔306。金屬化層可形成於主動及被動元件上方,且經設計以連接各種元件以形成功能電路。金屬化層可由介電質(例如,低k介電材料)與導電材料(例如,銅)的交替層形成,其中通孔互連導電材料層,且金屬化層可經由任何適合的製程(諸如沈積、鑲嵌、雙鑲嵌,或其類似者)形成。在一些實施例中,基底302實質上不含主動及被動元件。
基底302可在基底302的第一側上具有接合墊303以耦接至堆疊式晶粒308,且在基底302的第二側上具有接合墊304以耦接至導電連接件314,基底302的第二側與第一側對置。在一些實施例中,接合墊303及304藉由在基底302的第一側及第二側上將凹槽(未圖示)形成至介電層(未圖示)中而形成。可形成凹槽以允許接合墊303及304嵌入至介電層中。在其他實施例中,省略凹槽,此是因為接合墊303及304可形成於介電層上。在一些實施例中,接合墊303及304包含由銅、鈦、鎳、金、鈀、其類似者或其組合製成的薄晶種層(未圖示)。接合墊303及304的導電材料可沈積於薄晶種層上方。導電材料可藉由電化學鍍敷製程、化學鍍敷製程、CVD、ALD、PVD、其類似者或其組合形成。在一實施例中,接合墊303及304的導電材料為銅、鎢、鋁、銀、金、其類似者或其組合。
在一實施例中,接合墊303及304為包含三個導電材料層(諸如,鈦層、銅層以及鎳層)的UBM。然而,一般熟習此項技術者將認識到,存在適合於形成UBM 303及304的許多適合的材料及層的配置,諸如,鉻/鉻銅合金/銅/金的配置、鈦/鈦鎢/銅的配置,或銅/鎳/金的配置。可用於UBM 303及304的任何適合的材料或材料層全部意欲包含於當前申請案的範疇內。在一些實施例中,穿孔306延伸穿過基底302且將至少一個接合墊303耦接至至少一個接合墊304。
在所說明實施例中,堆疊式晶粒308藉由線接合310耦接至基底302,但可使用其他連接,諸如,導電凸塊。在一實施例中,堆疊式晶粒308為堆疊式記憶體晶粒。舉例而言,堆疊式記憶體晶粒308可包含低功率(low-power;LP)雙資料速率(double data rate;DDR)記憶體模組,諸如LPDDR1、LPDDR2、LPDDR3、LPDDR4,或類似記憶體模組。
在一些實施例中,堆疊式晶粒308及線接合310可由模製材料312密封。可使用(例如)壓縮模製將模製材料312模製於堆疊式晶粒308及線接合310上。在一些實施例中,模製材料312為模製化合物、聚合物、環氧樹脂、氧化矽填充材料、其類似者,或其組合。可執行固化步驟以固化模製材料312,其中固化可為熱固化、UV固化、其類似者,或其組合。
在一些實施例中,堆疊式晶粒308及線接合310埋入於模製材料312中,且在固化模製材料312之後,執行諸如研磨的平坦化步驟以移除模製材料312的多餘部分且為第二封裝300提供實質上平坦的表面。
在形成第二封裝300之後,封裝300藉助於導電連接件314、接合墊304以及金屬化圖案106接合至第一封裝200。在一些實施例中,堆疊式記憶體晶粒308可經由線接合310、接合墊303及304、穿孔306、導電連接件314以及穿孔112耦接至積體電路晶粒114。
導電連接件314可類似於上文所描述的導電連接件166,且不在本文中重複描述,但導電連接件314與導電連接件166不必相同。在一些實施例中,在接合導電連接件314之前,導電連接件314塗佈有助焊劑(未圖示),諸如免清助焊劑。導電連接件314可浸漬於助焊劑中,或助焊劑可噴射至導電連接件314上。在另一實施例中,助焊劑可塗覆至金屬化圖案106的表面。
在一些實施例中,導電連接件314可具有環氧樹脂助焊劑(未圖示),所述環氧樹脂助焊劑在導電連接件314藉由第二封裝300附接至第一封裝200之後剩餘的環氧樹脂助焊劑的環氧樹脂部分中的至少一些回焊之前形成於導電連接件314上。此剩餘環氧樹脂部分可充當底填充料以縮減應力且保護產生於回焊所述導電連接件314的接頭。在一些實施例中,底填充料(未圖示)可形成於第二封裝300與第一封裝200之間,且環繞導電連接件314。底填充料可在附接第二封裝300之後藉由毛細流動製程形成,或可在附接第二封裝300之前藉由適合的沈積方法形成。
第二封裝300與第一封裝200之間的接合可為焊料接合或直接金屬至金屬(諸如,銅至銅或錫至錫)接合。在一實施例中,第二封裝300藉由回焊製程接合至第一封裝200。在此回焊製程期間,導電連接件314與接合墊304及金屬化圖案106接觸,從而實體地且電性地將第二封裝300耦接至第一封裝200。在接合製程之後,IMC(未圖示)可形成於金屬化圖案106與導電連接件314的界面處,且亦形成於導電連接件314與接合墊304之間的界面處(未圖示)。
半導體封裝500包含安裝至基底400的封裝200及300。基底400可被稱作封裝基底400。封裝200使用導電連接件166安裝至封裝基底400。在封裝200安裝至基底400的情況下,IPD組件170插入於封裝200的重佈線結構160與基底400之間。IPD組件170可藉由間隙G1與基底400分離,所述間隙G1可受本發明的改良控制。
封裝基底400可由半導體材料製成,諸如矽、鍺、金剛石或其類似者。或者,亦可使用化合物材料,諸如矽鍺、碳化矽、鎵化砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、此等的組合及其類似者。另外,封裝基底400可為SOI基底。通常,SOI基底包含諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合的半導體材料的層。在一個替代性實施例中,封裝基底400基於諸如玻璃纖維強化樹脂芯的絕緣芯。一個實例芯材料為玻璃纖維樹脂,諸如FR4。芯材料的替代方案包含雙馬來醯亞胺三嗪BT樹脂,或替代地,其他PCB材料或膜。累積膜,諸如ABF或其他疊層物,可用於封裝基底400。
封裝基底400可包含主動及被動元件(圖22中未展示)。如一般熟習此項技術者將認識到,廣泛多種元件,諸如電晶體、電容器、電阻器、此等的組合及其類似者,可用以產生對於半導體封裝500的設計的結構及功能要求。所述元件可使用任何適合的方法形成。
封裝基底400亦可包含金屬化層及通孔(未圖示),以及金屬化層及通孔上方的接合墊402。金屬化層可形成於主動及被動元件上方,且經設計以連接各種元件以形成功能電路。金屬化層可由介電質(例如,低k介電材料)與導電材料(例如,銅)的交替層形成,其中通孔互連導電材料層,且金屬化層可經由任何適合的製程(諸如沈積、鑲嵌、雙鑲嵌,或其類似者)形成。在一些實施例中,封裝基底400實質上不含主動及被動元件。
在一些實施例中,可回焊導電連接件166以將封裝200附接至接合墊402。導電連接件166電性地及/或實體地將基底400,包含基底400中的金屬化層,耦接至第一封裝200。
導電連接件166可具有環氧樹脂助焊劑(未圖示),所述環氧樹脂助焊劑在導電連接件166藉由封裝200附接至基底400之後剩餘的環氧樹脂助焊劑的環氧樹脂部分中的至少一些回焊之前形成於導電連接件166上。此剩餘環氧樹脂部分可充當底填充料以縮減應力且保護產生於回焊所述導電連接件166的接頭。在一些實施例中,底填充料(未圖示)可形成於第一封裝200與基底400之間,且環繞導電連接件166及IPD組件170。底填充料可在附接封裝200之後藉由毛細流動製程形成,或可在附接封裝200之前藉由適合的沈積方法形成。
本發明的實施例包含封裝結構,所述封裝結構包含增加系統效能且放大製程裕度以改良封裝結構的可靠性及聯合產率的IPD設計。封裝結構可包含扇出型或扇入型封裝,且可包含一或多個重佈線層(RDL)。IPD組件可接合至封裝結構的一或多個RDL。IPD組件可接合至鄰近將兩個封裝/基底耦接且接合在一起的導電接頭的一或多個RDL。鄰近導電接頭可包含一或多個RDL上的凸塊下金屬化物(UBM)及耦接至UBM的焊接接頭。IPD組件可在無任何UBM的情況下接合至一或多個RDL。藉由移除IPD組件接頭區域下方的UBM,縮減了IPD組件的總高度且放大了製程裕度。
一實施例為一種封裝結構,所述結構包含:第一晶粒;模製化合物,其至少側向地密封所述第一晶粒;第一重佈線結構,其包含在所述第一晶粒及所述模製化合物上方延伸的金屬化圖案;第一導電連接件,其包括耦接至所述第一重佈線結構的焊球及凸塊下金屬化物;以及積體被動元件,其藉由微型凸塊接合接頭接合至所述第一重佈線結構中的第一金屬化圖案,所述積體被動元件鄰近所述第一導電連接件。
在上述實施例中,所述微型凸塊接合接頭的焊料層接觸所述第一重佈線結構的所述第一金屬化圖案,且其中所述第一導電連接件的所述凸塊下金屬化物接觸所述第一重佈線結構中的第二金屬化圖案。
在上述實施例中,所述第一金屬化圖案在所述第一重佈線結構中與所述第二金屬化圖案在同一位階處。
在上述實施例中,封裝結構進一步包括:使用所述第一導電連接件接合至所述第一重佈線結構的基底。
在上述實施例中,所述積體被動元件插入於所述第一重佈線結構與所述基底之間。
在上述實施例中,封裝結構進一步包括:延伸穿過所述模製化合物的電連接件,所述模製化合物鄰近所述第一晶粒;以及包括第二晶粒的封裝結構,所述封裝結構藉由第二導電連接件接合至所述電連接件,所述第一晶粒插入於所述封裝結構與所述基底之間。
另一實施例為一種封裝結構的形成方法,所述方法包含:形成第一封裝,其包含:在載體基底上方形成電連接件;將第一晶粒附接至所述載體基底,所述電連接件自所述第一晶粒的第二側延伸至所述第一晶粒的第一側,所述第二側與所述第一側對置,所述電連接件鄰近所述第一晶粒;運用模製化合物密封所述第一晶粒及所述電連接件;形成上覆於所述第一晶粒的所述第一側及所述模製化合物的重佈線結構,所述重佈線結構包括金屬化圖案;將包括凸塊下金屬化物的第一導電連接件耦接至所述重佈線結構的第一金屬化圖案;以及藉由接合接頭將積體被動元件接合至所述重佈線結構的第二金屬化圖案。
在上述實施例中,封裝結構的形成方法進一步包括:使用第二組導電連接件將第二封裝接合至所述第一封裝,所述第二封裝接近所述第一晶粒的所述第二側。
在上述實施例中,所述接合接頭包括具有焊料層的微型凸塊,所述焊料層接觸所述重佈線結構的所述第二金屬化圖案。
在上述實施例中,封裝結構的形成方法進一步包括:圖案化第一介電層以形成第一開口從而曝光所述第二金屬化圖案的第一部分,所述積體被動元件的所述接合接頭與所述第一開口在一起。
在上述實施例中,所述第一開口比所述第二金屬化圖案寬。
在上述實施例中,所述第一開口比所述第二金屬化圖案窄。
在上述實施例中,所述第一開口的側壁自所述第一介電層的頂部表面朝向所述第二金屬化圖案逐漸變窄。
在上述實施例中,圖案化所述第一介電層以形成第一開口包括執行雷射鑽孔製程或微影以形成所述第一開口。
在上述實施例中,封裝結構的形成方法進一步包括:在所述重佈線結構與所述積體被動元件之間形成底填充料,所述底填充料圍繞所述接合接頭。
在上述實施例中,封裝結構的形成方法進一步包括:使用所述第一導電連接件將基底接合至所述第一封裝,其中在所述接合之後,所述積體被動元件插入於所述重佈線結構與所述基底之間。
在上述實施例中,所述第一金屬化圖案在所述重佈線結構中與所述第二金屬化圖案在同一位階處。
另一實施例為一種封裝結構的形成方法,所述方法包含:形成鄰近第一晶粒的第一穿孔,所述第一穿孔自所述第一晶粒的第二側延伸至所述第一晶粒的第一側,所述第二側與所述第一側對置;運用模製材料密封所述第一穿孔及所述第一晶粒;在所述第一晶粒的所述第一側、所述第一穿孔以及所述模製材料上方形成第一重佈線結構,所述第一重佈線結構包括多個金屬化圖案及多個介電層;在所述第一重佈線結構的第一介電層上方且穿過所述第一介電層形成第一凸塊下金屬化物,以接觸所述第一重佈線結構的第一金屬化圖案;以及藉由接合接頭將積體被動元件接合至所述第一重佈線結構的第二金屬化圖案,所述接合接頭延伸穿過所述第一重佈線結構的所述第一介電層。
在上述實施例中,封裝結構的形成方法進一步包括:使用第二導電連接件將第二封裝接合至所述第一穿孔,所述第二封裝接近所述第一晶粒的所述第二側。
在上述實施例中,所述接合接頭包括具有焊料層的微型凸塊,所述焊料層接觸所述第一重佈線結構的所述第二金屬化圖案。
前文概述若干實施例的特徵,以使得熟習此項技術者可較佳地理解本發明的態樣。熟習此項技術者應理解,其可易於使用本發明作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。熟習此項技術者亦應認識到,此類等效構造並不脫離本發明的精神及範疇,且其可在不脫離本發明的精神及範疇的情況下在本文中進行各種改變、替代以及更改。
100‧‧‧載體基底
102‧‧‧釋放層
104、108、132、140、148、156‧‧‧介電層
106、138、146、154‧‧‧金屬化圖案
110‧‧‧背側重佈線結構
112、306‧‧‧穿孔
114‧‧‧積體電路晶粒
116‧‧‧黏著劑
118‧‧‧半導體基底
120、174‧‧‧互連結構
122‧‧‧墊124‧‧‧鈍化膜
126‧‧‧晶粒連接件
128‧‧‧介電材料
130‧‧‧密封體
160‧‧‧前側重佈線結構
162‧‧‧墊/凸塊下金屬(UBM)
164‧‧‧開口
164A‧‧‧楔形側壁
166、314‧‧‧導電連接件
170‧‧‧積體被動元件(IPD)組件
172‧‧‧主結構
176‧‧‧微型凸塊
178‧‧‧焊料層/凸塊
180‧‧‧被動元件
182‧‧‧模製材料/半導體基底
184‧‧‧底填充料
186‧‧‧單一化
190‧‧‧膠帶
200‧‧‧第一封裝
300‧‧‧第二封裝
302、400‧‧‧基底
303‧‧‧接合墊/凸塊下金屬(UBM)
304、402‧‧‧接合墊
308‧‧‧堆疊式晶粒/堆疊式記憶體晶粒
308A、308B‧‧‧堆疊式晶粒
310‧‧‧線接合
312‧‧‧模製材料
500‧‧‧封裝結構/半導體封裝
600‧‧‧第一封裝區
602‧‧‧第二封裝區
H1‧‧‧高度
H2‧‧‧高度
H3‧‧‧高度
G1‧‧‧間隙
當結合附圖閱讀時,自以下實施方式最好地理解本發明的態樣。應注意,根據行業中的標準慣例,各種特徵未按比例繪製。事實上,為論述清楚起見,可任意增加或縮減各種特徵的尺寸。 圖1至圖18、圖20A、圖20B、以及圖23至圖26說明根據一些實施例的在用於形成封裝結構的製程期間的中間步驟的橫截面圖。 圖19A至圖19D說明根據一些實施例的鈍化開口的橫截面圖。 圖21A及圖21B說明根據一些實施例的積體被動元件的橫截面圖。 圖22A至圖22C說明根據一些實施例的用於積體被動元件的底填充料方案的橫截面圖。
100‧‧‧載體基底
102‧‧‧釋放層
600‧‧‧第一封裝區
602‧‧‧第二封裝區

Claims (10)

  1. 一種封裝結構,包括: 第一晶粒; 模製化合物,至少側向地密封所述第一晶粒; 第一重佈線結構,包括在所述第一晶粒及所述模製化合物上方延伸的金屬化圖案; 第一導電連接件,包括耦接至所述第一重佈線結構的焊球及凸塊下金屬化物;以及 積體被動元件,藉由微型凸塊接合接頭接合至所述第一重佈線結構中的第一金屬化圖案,所述積體被動元件鄰近所述第一導電連接件。
  2. 如申請專利範圍第1項所述的封裝結構,其中所述微型凸塊接合接頭的焊料層接觸所述第一重佈線結構的所述第一金屬化圖案,且其中所述第一導電連接件的所述凸塊下金屬化物接觸所述第一重佈線結構中的第二金屬化圖案。
  3. 如申請專利範圍第1項所述的封裝結構,進一步包括: 使用所述第一導電連接件接合至所述第一重佈線結構的基底。
  4. 一種封裝結構的形成方法,包括: 形成第一封裝,包括: 在載體基底上方形成電連接件; 將第一晶粒附接至所述載體基底,所述電連接件自所述第一晶粒的第二側延伸至所述第一晶粒的第一側,所述第二側與所述第一側對置,所述電連接件鄰近所述第一晶粒; 運用模製化合物密封所述第一晶粒及所述電連接件; 形成上覆於所述第一晶粒的所述第一側及所述模製化合物的重佈線結構,所述重佈線結構包括金屬化圖案; 將包括凸塊下金屬化物的第一導電連接件耦接至所述重佈線結構的第一金屬化圖案;以及 藉由接合接頭將積體被動元件接合至所述重佈線結構的第二金屬化圖案。
  5. 如申請專利範圍第4項所述的封裝結構的形成方法,進一步包括: 使用第二組導電連接件將第二封裝接合至所述第一封裝,所述第二封裝接近所述第一晶粒的所述第二側。
  6. 如申請專利範圍第4項所述的封裝結構的形成方法,其中所述接合接頭包括具有焊料層的微型凸塊,所述焊料層接觸所述重佈線結構的所述第二金屬化圖案。
  7. 如申請專利範圍第4項所述的封裝結構的形成方法,其進一步包括: 圖案化第一介電層以形成第一開口從而曝光所述第二金屬化圖案的第一部分,所述積體被動元件的所述接合接頭與所述第一開口在一起。
  8. 如申請專利範圍第4項所述的封裝結構的形成方法,其進一步包括: 在所述重佈線結構與所述積體被動元件之間形成底填充料,所述底填充料圍繞所述接合接頭。
  9. 如申請專利範圍第4項所述的封裝結構的形成方法,其進一步包括: 使用所述第一導電連接件將基底接合至所述第一封裝,其中在所述接合之後,所述積體被動元件插入於所述重佈線結構與所述基底之間。
  10. 一種封裝結構的形成方法,包括: 形成鄰近第一晶粒的第一穿孔,所述第一穿孔自所述第一晶粒的第二側延伸至所述第一晶粒的第一側,所述第二側與所述第一側對置; 運用模製材料密封所述第一穿孔以及所述第一晶粒; 在所述第一晶粒的所述第一側、所述第一穿孔以及所述模製材料上方形成第一重佈線結構,所述第一重佈線結構包括多個金屬化圖案及多個介電層; 在所述第一重佈線結構的第一介電層上方且穿過所述第一介電層形成第一凸塊下金屬化物,以接觸所述第一重佈線結構的第一金屬化圖案;以及 藉由接合接頭將積體被動元件接合至所述第一重佈線結構的第二金屬化圖案,所述接合接頭延伸穿過所述第一重佈線結構的所述第一介電層。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10510650B2 (en) 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
TWI681528B (zh) * 2018-05-28 2020-01-01 力成科技股份有限公司 重佈線結構及其製造方法
TWI716096B (zh) * 2018-09-05 2021-01-11 台灣積體電路製造股份有限公司 半導體封裝體及其形成方法
US11309294B2 (en) 2018-09-05 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
TWI767259B (zh) * 2019-09-17 2022-06-11 日月光半導體製造股份有限公司 基板結構及用於製造半導體封裝之方法

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112018001741T5 (de) * 2017-03-30 2019-12-19 Mitsubishi Electric Corporation Halbleiteranordnung Verfahren zu dessen Herstellung undLeistungswandlervorrichtung
US10535643B2 (en) * 2017-08-04 2020-01-14 Samsung Electronics Co., Ltd. Connection system of semiconductor packages using a printed circuit board
US10269773B1 (en) 2017-09-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US10840227B2 (en) * 2017-11-02 2020-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Under-bump-metallization structure and redistribution layer design for integrated fan-out package with integrated passive device
US10770364B2 (en) * 2018-04-12 2020-09-08 Xilinx, Inc. Chip scale package (CSP) including shim die
KR20190124892A (ko) * 2018-04-27 2019-11-06 삼성전자주식회사 팬-아웃 반도체 패키지
US10804254B2 (en) * 2018-06-29 2020-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package with cavity substrate
US10971446B2 (en) 2018-11-30 2021-04-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11121089B2 (en) * 2018-11-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11139249B2 (en) * 2019-04-01 2021-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of forming the same
US20210066273A1 (en) * 2019-08-30 2021-03-04 Intel Corporation Laser ablation-based surface property modification and contamination removal
US11088125B2 (en) * 2019-09-17 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. IPD modules with flexible connection scheme in packaging
US11476201B2 (en) * 2019-09-27 2022-10-18 Taiwan Semiconductor Manufacturing Company. Ltd. Package-on-package device
DE102020108481B4 (de) * 2019-09-27 2023-07-06 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleiter-Die-Package und Herstellungsverfahren
US11227837B2 (en) * 2019-12-23 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
CN113097184A (zh) * 2019-12-23 2021-07-09 台湾积体电路制造股份有限公司 半导体结构及其形成方法
US11616026B2 (en) * 2020-01-17 2023-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11462418B2 (en) * 2020-01-17 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
TWI777467B (zh) * 2020-03-30 2022-09-11 台灣積體電路製造股份有限公司 半導體裝置及其製造方法
US11527518B2 (en) * 2020-07-27 2022-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Heat dissipation in semiconductor packages and methods of forming same
US20220367406A1 (en) * 2021-05-15 2022-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Die-group package having a deep trench device
US11967591B2 (en) * 2021-08-06 2024-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Info packages including thermal dissipation blocks
US12100634B2 (en) * 2021-10-13 2024-09-24 Nanya Technology Corporation Semiconductor device with re-fill layer

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4980232B2 (ja) 2005-11-02 2012-07-18 太陽誘電株式会社 システムインパッケージ
JP2008091638A (ja) * 2006-10-02 2008-04-17 Nec Electronics Corp 電子装置およびその製造方法
US20090108433A1 (en) * 2007-10-30 2009-04-30 Kenji Masumoto Multilayer semiconductor device package assembly and method
US7935570B2 (en) * 2008-12-10 2011-05-03 Stats Chippac, Ltd. Semiconductor device and method of embedding integrated passive devices into the package electrically interconnected using conductive pillars
US8008121B2 (en) * 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US8884431B2 (en) * 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9123763B2 (en) * 2011-10-12 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure having at least one package comprising one die being disposed in a core material between first and second surfaces of the core material
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US10177115B2 (en) 2014-09-05 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
US10079192B2 (en) * 2015-05-05 2018-09-18 Mediatek Inc. Semiconductor chip package assembly with improved heat dissipation performance
US20170098589A1 (en) * 2015-10-05 2017-04-06 Mediatek Inc. Fan-out wafer level package structure

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10510650B2 (en) 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
TWI691026B (zh) * 2018-02-02 2020-04-11 台灣積體電路製造股份有限公司 製造半導體元件的方法
US10756010B2 (en) 2018-02-02 2020-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packaging structure having through interposer vias and through substrate vias
US11456240B2 (en) 2018-02-02 2022-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
TWI681528B (zh) * 2018-05-28 2020-01-01 力成科技股份有限公司 重佈線結構及其製造方法
TWI716096B (zh) * 2018-09-05 2021-01-11 台灣積體電路製造股份有限公司 半導體封裝體及其形成方法
US11309294B2 (en) 2018-09-05 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
TWI767259B (zh) * 2019-09-17 2022-06-11 日月光半導體製造股份有限公司 基板結構及用於製造半導體封裝之方法

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