TW201724273A - Techniques for bottom-up filling of three-dimensional semiconductor device topographies - Google Patents

Abstract

Techniques are disclosed for bottom-up filling of semiconductor device topographies. In accordance with some embodiments, a seed layer may be formed over a bottom surface of a feature patterned in a dielectric layer. The seed layer may be, for example, a work function metal (WFM) layer or a barrier layer. In accordance with some embodiments, the fill metal may be, at least initially, selectively deposited over only the seed layer, and as deposition continues, the fill metal may grow to fill the feature from bottom to top, in some cases with no seam or void formed therein. Optional selective passivation of the sidewalls of the feature (or other layer therein) may inhibit fill metal deposition on those surfaces, facilitating selective deposition. In accordance with some embodiments, an etch and recess process that utilizes a sacrificial fill material may be used in forming the seed layer at the feature bottom.

Description

Bottom-up filling technique for three-dimensional semiconductor device topography

The present invention relates to a technique for bottom-up filling of a three-dimensional semiconductor device topography.

In a typical three-dimensional transistor architecture, three-dimensional fins stand vertically from the underlying germanium substrate. The metal gate system covers the top and sides of the fin to provide a so-called three-gate transistor. In contrast, a conventional two-dimensional planar transistor has only a single meandering surface, and a gate is disposed over the single meandering surface. The gate dielectric is normally placed between the gate and the lower layer.

100A‧‧‧ integrated circuit

102‧‧‧ dielectric layer

103‧‧‧ dielectric layer

104‧‧‧Semiconductor body

105‧‧‧Explosive semiconductor body

106‧‧‧ Notch

106a‧‧‧ Groove/hole section

106b‧‧‧ bottom part

106c‧‧‧ Sidewall section

107‧‧‧Contact metal layer

108‧‧‧ dielectric layer

110‧‧‧Baffle layer

112‧‧‧Work function metal layer

113‧‧‧Baffle layer

114‧‧‧Filling materials

116‧‧‧metal layer

118‧‧‧Characteristic area

120‧‧‧Contact metal layer

200‧‧‧Source/bungee contacts

100B‧‧‧ integrated circuit

100A’‧‧‧ integrated circuit

100B’‧‧‧ integrated circuit

1000‧‧‧Computation System

1002‧‧‧ motherboard

1004‧‧‧ processor

1006‧‧‧Communication chip

Figure 1 illustrates features formed by conformal fill in interlayer dielectric (ILD).

2A is a cross-sectional view of an integrated circuit (IC) configured in accordance with an embodiment of the present disclosure.

2B is a layer forming a filling material in accordance with an embodiment of the present disclosure. A cross-sectional view of the IC of Figure 2A is shown.

2C is a cross-sectional view of the IC of FIG. 2B after partial removal of the fill material, work function metal (WFM) layer, and barrier layer in accordance with an embodiment of the present disclosure.

2D is a cross-sectional view of the IC of FIG. 2C after removal of the remainder of the fill material in accordance with an embodiment of the present disclosure.

2E is a cross-sectional view of the IC of FIG. 2D after forming a metal layer in accordance with an embodiment of the present disclosure.

3A is a cross-sectional view of an IC configured in accordance with another embodiment of the present disclosure.

3B is a cross-sectional view of the IC of FIG. 3A after forming a layer of fill material in accordance with an embodiment of the present disclosure.

3C is a cross-sectional view of the IC of FIG. 3B after partial removal of the second barrier layer and filler material in accordance with an embodiment of the present disclosure.

3D is a cross-sectional view of the IC of FIG. 3C after removal of the remainder of the fill material in accordance with an embodiment of the present disclosure.

3E is a cross-sectional view of the IC of FIG. 3D after forming a metal layer in accordance with an embodiment of the present disclosure.

4 is a cross-sectional view of an IC configured in accordance with another embodiment of the present disclosure.

5 is a cross-sectional view of an IC configured in accordance with another embodiment of the present disclosure.

6 is a cross-sectional view of a source/drain (S/D) contact configured in accordance with an embodiment of the present disclosure.

7 is a diagram illustrating a computing system implemented in an integrated circuit structure in accordance with an example embodiment or an apparatus formed using the disclosed techniques.

These and other features of the present embodiments will be better understood by reading the following description in conjunction with the drawings. In the drawings, various identical or nearly identical components that are illustrated in the various figures are represented by like numerals. For the sake of brevity, not every component is labeled in every figure. Further, it will be understood that the illustrated embodiments are not necessarily to For example, while some figures generally indicate straight lines, right angles, and smooth surfaces, the actual implementation of the disclosed techniques may have less perfect straight lines, right angles, etc., and some features may have surface topography or otherwise non-smooth It is the real world limit of a given manufacturing process. In short, the figures are only provided to illustrate the example structure.

SUMMARY OF THE INVENTION AND EMBODIMENTS

The bottom-up filling of the topography of a three-dimensional semiconductor device reveals the technique. According to some embodiments, the seed layer may be formed over the bottom surface of the recess, the hole, or other of the layers patterned in the dielectric layer. The seed layer may be, for example, a work function metal (WFM) layer or a barrier layer. In either case, according to some embodiments, at least initially may be selectively deposited only over the seed layer. In some cases where no seams or voids are formed, as the deposition continues, the filler metal can grow from bottom to top to fill the features. In some instances, an optional selection of sidewalls of features (or other layers thereof) Selective passivation inhibits deposition of the filler metal on the surfaces having passivation molecules deposited thereon, thereby facilitating selective formation of filler metal within the features. According to some embodiments, an etching and recessing/digging process using a sacrificial filler material can be used for the seed layer at the bottom portion of the feature. Numerous configurations and variations will be apparent in light of this disclosure.

Overview

As the size shrinks, it becomes difficult to fill the topography in the three-dimensional crystal device. Existing conformal filling techniques result in the formation of seams or voids, such as those illustrated in Figure 1, which illustrates the formation of features in an inter-layer dielectric (ILD). Conformal fill. These seams or voids cause device reliability problems and are normally incurable without the application of extreme heat. Because of the difference in deposition rates on the horizontal field compared to the vertical sidewalls, some existing processes give order non-conformal fills. In addition, the existing bottom-up filling process utilizing surface modification by ion implantation is limited to having a low aspect ratio and a constant size and pitch, and utilizing no electricity. These ones of electroless chemistry are very difficult to maintain in controlling the formation of particles.

Thus, and in accordance with some embodiments of the present disclosure, the bottom-up fill technique is disclosed for the topography of a three-dimensional semiconductor device. According to some embodiments, a seed layer may be formed over a bottom surface of a recess, hole or other patterned feature in the dielectric layer. For example, the seed layer can be a work function metal (WFM) layer or a barrier layer. According to some embodiments, in either case, The filler metal may at least initially be selectively deposited only over the seed layer. As the deposition continues, the filler metal can grow to fill the features from bottom to top, with no seams or voids in some cases. In some examples, optional selective passivation of the sidewalls of the feature (or other layers therein) can inhibit deposition of a filler metal on the surfaces having passivation molecules disposed thereon, thereby facilitating selectivity within the features A filler metal is formed. According to some embodiments, the etching and recessing/digging process using the sacrificial filler material can be used in forming the seed layer in the bottom portion of the feature.

In accordance with some embodiments, the disclosed techniques can be used in forming gate structures and source/drain contact structures, such as in a three-dimensional transistor architecture. In accordance with some embodiments, the techniques disclosed herein may be utilized without regard to feature size and spacing to provide seamless or seamless (with the presence of minimized (or otherwise reduced) defects ( Gapless) is filled from bottom to top. As will be appreciated in accordance with the present disclosure, in some instances, removing or reducing the presence of seams or gaps in a metal (eg, gate metal; source/drain contact metal) may improve device reliability and mass production. . Numerous suitable uses and applications will be apparent in light of this disclosure.

According to some embodiments, the visual or other means of the device may be filled, for example, by a given integrated circuit or with a chemically distinct layer at the bottom of the feature and without seams or otherwise seamlessly filling the feature. Detection (eg, scanning electron microscope or SEM, imaging; transmission electron microscope or TEM, imaging) can detect the use of the disclosure technique. In some cases, filling the semiconductor fins The presence of voids or seams in the regions may be indicative of the techniques disclosed herein.

Method and structure

2A to 2E illustrate a manufacturing process flow of an integrated circuit (IC) for forming an IC 100A according to an embodiment of the present disclosure. According to some embodiments, the process flow of FIGS. 2A-2E can be used to selectively deposit a filler material in a three-dimensional p-type metal-oxide-semiconductor (O.S.) device (eg, The gate material) is provided from bottom to top. Other suitable uses of the process flow of Figures 2A-2E will be apparent in light of this disclosure.

The process can begin with Figure 2A, which is a cross-sectional view of an integrated circuit (IC) 100A configured in accordance with an embodiment of the present disclosure. As can be seen, the IC 100A can include a dielectric layer 102. As will be appreciated in light of the present disclosure, dielectric layer 102 can be formed from any suitable dielectric material. For example, in some cases, dielectric layer 102 may be formed from an oxide, such as silicon dioxide (SiO _2). In some cases, dielectric layer 102 can be formed from a nitride such as tantalum nitride (Si ₃ N ₄ ), hafnium oxynitride (SiON), tantalum carbonitride (SiCN), or boron nitride (BN). In some cases, dielectric layer 102 can be formed from carbides, such as tantalum carbide (SiC). In a more general sense and in accordance with some embodiments, the dielectric layer 102 can be formed from any of the foregoing materials or combinations. In other examples, dielectric layer 102 can be a homogeneous dielectric structure (eg, comprising only a single dielectric material). In some other examples, dielectric layer 102 can be a heterogeneous dielectric structure (eg, comprising portions of different dielectric materials) in some embodiments. In some embodiments, dielectric layer 102 can be, for example, an interlayer dielectric (ILD).

Dielectric layer 102 can be patterned with features 106. In some examples, feature 106 can have, for example, one or more groove/hole portions 106a. In some cases, feature 106 can have a bottom portion 106b and one or more side wall portions 106c. The dimensions and geometry of dielectric layer 102 and features 106 can be customized for a given target application or terminal use. As will be appreciated in light of this disclosure, the patterned features 106 can be performed within the dielectric layer 102 via any suitable standard, custom or suitable patterning technique. Other suitable materials, dimensions, geometries, and formation techniques for dielectric layer 102 and features 106 will depend on a given application and will be apparent in light of this disclosure.

Moreover, as can be seen from FIG. 2A, the IC 100A can include a semiconductor body 104 disposed within the dielectric layer 102 and protruding into the feature 106, resulting in one or more recesses that are side-by-side in the semiconductor body 104 in the dielectric layer 102. The presence of a slot (or hole) 106a. As will be appreciated in light of the present disclosure, the semiconductor body 104 can be formed from any suitable semiconductor material. For example, in some cases, the semiconductor body 104 can be from germanium (Si), germanium (Ge), germanium telluride (SiGe), tantalum carbide (SiGeC), or tantalum carbide (SiC). In some cases, the semiconductor body 104 can be formed from a III-V composite semiconductor, such as GaN, GaAs, InAs, InP, or InGaAs. (InGaAs). In a more general sense and in accordance with some embodiments, the semiconductor body 104 can be formed from any or a combination of the foregoing materials.

As desired for a given target application or terminal usage, the dimensions and geometry of the semiconductor body 104 can be customized. In some cases, the semiconductor body 104 can be configured as a fin or other fin-like protrusion. In accordance with some embodiments, as will be appreciated in light of the present disclosure, semiconductor body 104 can be utilized to form, for example, a fin-based transistor device or other suitable fin-based semiconductor architecture.

As will be appreciated in light of this disclosure, the formation of semiconductor body 104 can be performed via any suitable standard, custom or suitable patterning (e.g., finFET fabrication) technique. In some examples, the semiconductor body 104 can have one or more layers, such as a hard mask or other layer formed thereon (eg, on its upper surface) and any overlying/overlying layers, Like dielectric layer 108 (discussed below). Other suitable materials, dimensions, geometries, and forming techniques for the semiconductor body 104 will depend on the given application and will be apparent in light of this disclosure.

As can be further seen from FIG. 2A, the IC 100A can include a dielectric layer 108. According to an embodiment, the dielectric layer 108 can be configured to function as a gate dielectric layer. Dielectric layer 108 can be formed from any suitable high-k dielectric material (e.g., having a dielectric constant k greater than or equal to that of cerium oxide). For example, in some cases, dielectric layer 108 may be formed from an oxide such as hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), zirconium dioxide (ZrO ₂ ), tantalum oxide (Ta _{2 )} O ₅ ), titanium dioxide (TiO ₂ ), lanthanum oxide (La ₂ O ₃ ) or lanthanum oxide (Gd ₂ O ₃ ). In some cases, the dielectric layer 108 may be formed from a doped silicon oxide, such as for example, hafnium silicate (HfSiO _x), aluminum silicate (AlSiO _x), zirconium silicate (ZrSiO _x), tantalum silicate (TaSiO _x), titanium silicate (TiSiO _x), lanthanum silicate (LaSiO _x) or gadolinium silicate (GdSiO _x). In some cases, the dielectric layer 108 may be formed from silicon oxide doped with from, for example, such as hafnium silicate (HfSiO _x), aluminum silicate (AlSiO _x), zirconium silicate (ZrSiO _x), silicon Barium acid (TaSiO _x ), titanium silicate (TiSiO _x ), barium strontium silicate (LaSiO _x ) or barium strontium silicate (GdSiO _x ). Other suitable rare earth oxides and rare earth cerates will depend on the intended application and will be apparent as disclosed herein. In a more general sense and in accordance with some embodiments, the dielectric layer 108 can be formed from any one or combination of the foregoing materials. According to some embodiments, dielectric layer 108 and dielectric layer 102 may be composed of different materials.

As desired for a given target application or terminal usage, the dimensions and geometry of the dielectric layer 108 can be customized. In some cases, dielectric layer 108 can have an average thickness, for example, in the range of about 1 to 10 nm (eg, about 1 to 5 nm, about 5 to 10 nm, or any other subrange in the range of about 1 to 10 nm). . In some cases, dielectric layer 108 can have an average thickness, for example, in the range of about 0.5 to 5 nm (eg, any other subrange in the range of about 0.5 to 2.5 nm, about 2.5 to 5 nm, or about 0.5 to 5 nm). . In some cases, the dielectric material 108 can have an average thickness, for example, in the range of about 0.1 to 3 nm (eg, about 0.1 to 1 nm, about 1 to 2 nm, about 2 to 3 nm, or about 0.1 to 3 nm). Any other subrange). In some cases, dielectric layer 108 can have an average thickness of, for example, about 1 nm or less (eg, about 0.5 nm or less, about 0.1 nm or less, etc.).

In some examples, dielectric layer 108 can have a substantially uniform thickness over a topography provided, for example, by low-level dielectric layer 102 (eg, features 106 formed therein) and semiconductor body 104. In some examples, dielectric layer 108 can be provided as a substantial conformal layer over such topography. In other examples, the dielectric layer 108 can be provided to have a thickness that is non-uniform or otherwise varied above such topography. For example, in some cases, the first portion of the dielectric layer 108 can have a thickness in the first range, while the second portion can have a thickness in the second, different range. In some examples, dielectric layer 108 can have first and second portions having an average thickness that differs from each other by about 20% or less, about 15% or less, about 10% or less, or about 5% or less. In some cases, the dielectric layer 108 can extend from the bottom portion 106b of the feature 106 to the full height of the sidewall portion 106c of the feature 106. In some other instances, the dielectric layer 108 can extend from the bottom portion 106b of the feature 106 to a height equal to the sidewall portion 106c of the feature 106 of the thickness of the dielectric layer 108 (eg, as can be seen from Figure 4 below). 5 to see).

As will be appreciated in light of the present disclosure, dielectric layer 108 can be formed using any suitable technique. For example, in some cases, a chemical vapor deposition (CVD) process such as plasma-enhanced CVD (CVD) and atomic layer deposition (ALD; atomic layer) may be performed. The dielectric layer 108 is formed by either or a combination of the deposition processes. Other suitable materials, dimensions, geometries, and formation techniques for dielectric layer 108 will depend on a given application and will be apparent in light of this disclosure.

According to some embodiments, the barrier layer 110 may be formed over the dielectric layer 108. In some cases, the barrier layer 110 can be formed, for example, from a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), vanadium nitride (VN), tantalum nitride (NbN), or nitride. Zirconium (ZrN) either or a combination. In a more general sense and in accordance with some embodiments, the barrier layer 110 can be formed from any suitable material that can be at least partially reliable for use with the primary IC 100A (or other primary ICs configured as described herein). Sex layer. As will be understood in accordance with the present disclosure, barrier layer 110 can be formed in any of the exemplary dimensions, geometries, and techniques discussed above, such as opposing dielectric layer 108, in accordance with some embodiments. In some cases, the morphology of the barrier layer 110 to the underlying dielectric layer 108 can be conformal. In some examples, the barrier layer 110 initially extends at least from the bottom portion 106b of the feature 106 to the full height of the sidewall portion 106c of the feature 106. In some examples, the barrier layer 110 can extend from the bottom portion 106b of the feature 106 to less than the full height of the sidewall portion 106c of the feature 106. Other suitable materials, dimensions, geometries, and forming techniques for the barrier layer 110 will depend on the given application and will be apparent in light of this disclosure.

According to some embodiments, a function function metal (WFM) layer 112 may be formed over the barrier layer 110. As will be appreciated in light of this disclosure, the WFM layer 112 can be formed from any suitable work function metal. For example, in some cases, the WFM layer 112 can be derived from tungsten (W), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), vanadium nitride (VN), tantalum nitride (NbN), and Zirconium nitride (ZrN). As will be appreciated in accordance with the present disclosure, in accordance with some embodiments, the WFM layer 112 can be, for example, phased. Dielectric layer 108 is formed in any of the exemplary dimensions, geometries, and techniques discussed above. In some cases, the WFM layer 112 is conformal to the topography of the underlying barrier layer 110. In some examples, the WFM layer 112 can at least initially extend from the bottom portion 106b of the feature 106 to the full height of the sidewall portion 106c of the feature 106. In some examples, the WFM layer 112 can extend from the bottom portion 106b of the feature 106 to a full height below the sidewall portion 106c of the feature 106. According to some embodiments, the WFM layer 112 can be at least partially as a seed layer, for example for the metal layer 116 (discussed below with respect to Figure 2E). Other suitable materials, dimensions, geometries, and forming techniques for the WFM layer 112 will depend on the given application and will be apparent in light of this disclosure.

The process can continue as in FIG. 2B, which is a cross-sectional view of IC 100A of FIG. 2A after forming a layer of fill material 114 in accordance with an embodiment of the present disclosure. As can be seen, the fill material 114 can be disposed over the WFM layer 112, the barrier layer 110, and the dielectric layer 108 within the features 106 (eg, within the recesses/holes 106a alongside the semiconductor body 104). Filler material 114 can be any of a wide variety of materials. For example, in some cases, the fill material 114 can be any or a combination of cerium oxide (not having), a carbide hard mask, and tungsten (W). In some cases, the fill material 114 can be a dielectric or other insulating material that can selectively form a metal (such as, for example, the metal layer 116 discussed below). In a more general sense and in accordance with some embodiments, the filler material 114 can be formed from any of the foregoing materials or combinations. As will be understood in light of the present disclosure, filling material 114 in a general sense may be considered to sacrifice the filler material.

The dimensions and geometry of the fill material 114 can be customized as desired for a given target application or terminal and in some instances can depend, at least in part, on the dimensions and geometry of the features 106 and the semiconductor body 104 therein. As will be appreciated in accordance with the present disclosure, the fill material 114 is deposited using any suitable technique. For example, in some cases, a chemical vapor deposition (CVD) process such as plasma-enhanced CVD (CVD), atomic layer deposition (ALD; atomic layer) may be used. The deposition process 114 and the spin-on deposition (SOD) process are combined to deposit the filler material 114. Any one or combination of a chemical-mechanical planarization (CMP) process and an etch-and-clean process may be used to remove unwanted filler material 114 (eg, possibly Overburden over the surface above the IC 100A). Other suitable materials, dimensions, geometries, and forming techniques for the fill material 114 will depend on the given application and will be apparent in light of this disclosure.

The process may continue as in FIG. 2C, which is a cross-sectional view of IC 100A of FIG. 2B after partial removal of fill material 114, WFM layer 112, and barrier layer 110 in accordance with an embodiment of the present disclosure. As will be appreciated in light of this disclosure, the fill material 114, the WFM layer 112, and the barrier layer 110 can be partially removed from the features 106 using any suitable technique. For example, in some cases, a wet etch process or a dry etch process, an etch chemistry, a sanding or planarization process (eg, CMP) that can be customized for a given target application and end use can be used. ) and fly ash processing (ash Process (eg, it does not oxidize any metal present) either or in combination to partially remove (or dig into) the fill material 114, the WFM layer 112, and the barrier layer 110. According to some embodiments, partially removing the fill material 114 may occur sequentially or in parallel with the partially removed WFM layer 112 and the barrier layer 110. As will be understood in accordance with the present disclosure, the same etchant used to simultaneously partially remove the fill material 114, the WFM layer 112, and the barrier layer 110 is also used to subsequently remove the residue of the fill material 114 (eg, as described below) 2D discussion), then what it is expected to be to ensure the appropriate processing timing desired for a given target application and terminal usage. Depending on the embodiment, each of the fill material 114, the WFM layer 112, and the barrier layer 110 may remain only in, for example, feature 106 when portions of each of the fill material 114, the WFM layer 112, and the barrier layer 110 are removed from the features 106. In the bottom portion 106b. In some examples, each of the barrier layer 110 and the WFM layer 112 can extend from the bottom portion 106b of the feature 106 to a full height below the sidewall portion 106c of the feature 106.

The process can continue as in FIG. 2D, which is a cross-sectional view of IC 100A of FIG. 2C after removal of the residue of fill material 114 in accordance with an embodiment of the present disclosure. As will be appreciated in accordance with the present disclosure, any of the techniques discussed above with respect to FIG. 2C and partially removing the filler material 114 may be used for this purpose in accordance with some embodiments. Depending on the embodiment, upon removal of the residue of the fill material 114, the WFM layer 112 and the barrier layer 110 may still remain, for example, only partially in the bottom portion 106b of the feature 106. Portions of the WFM layer 112 above the bottom portion 106b may be at least partially as, for example, a seed layer for the metal layer 116 (discussed below).

The process can continue as in FIG. 2E, which is a cross-sectional view of IC 100A of FIG. 2D after forming metal layer 116 in accordance with an embodiment of the present disclosure. As will be appreciated in accordance with the present disclosure, metal layer 116 can be formed from any suitable electrically conductive material. For example, in some cases, metal layer 116 may be formed from a metal such as copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), gold. (Au), titanium (Ti) or tantalum (Ta). In some cases, metal layer 116 may be formed from the nitride, such as titanium nitride (TiN) or tantalum nitride (TaN). In a more general sense and in accordance with some embodiments, the metal layer 116 can be formed from any of the foregoing materials or combinations.

The dimensions and geometry of the metal layer 116 can be customized as desired for a given target application or terminal, and in some cases can depend, at least in part, on the dimensions and geometry of the features 106 and the semiconductor body 104 therein. In accordance with some embodiments, metal layer 116 may be selectively formed over a thin layer (eg, a seed layer) of WFM layer 112 over bottom portion 106b of feature 106 (eg, selective deposition or otherwise selective) Growing). For this purpose, it will be apparent in light of the present disclosure that the metal layer 116 can be formed using any suitable technique. For example, in some cases, the metal layer 116 can be formed via any one or combination of an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, and an electroless deposition process. Other suitable materials, dimensions, geometries, and forming techniques for metal layer 116 will depend on the particular application and will be apparent in light of this disclosure.

In some cases and depending on the embodiment, the metal layer 116 may initially only Growth on a thin layer (e.g., seed layer) of the WFM layer 112 results in a seamless, underlying, filled metal layer 116 within features 106 around the semiconductor body 104. Depending on the embodiment, as metal layer 116 reaches and clears the top of semiconductor body 104, growth of metal layer 116 may continue inwardly of feature 106. In some examples, a void or seam may be formed in region 118 of feature 106 as metal layer 116 clears the top of semiconductor body 104. As will be understood in accordance with the present disclosure, in some instances it may be desirable to eliminate or otherwise reduce the presence of such voids or seams. For this purpose, as will be appreciated in light of the present disclosure, the metal layer 116 can be soldered back and forth using any suitable metal reflow process. However, in other cases, such voids or seams may remain in region 118 without having an effect on IC 200A (or other primary IC configured as described herein) or otherwise having negligible or Accepted influence.

According to some embodiments, after partially removing the fill material 114, the WFM layer 112, and the barrier layer 110 (eg, as discussed above with respect to FIG. 2C) or after removing the residue of the fill material 114 (eg, on top) As discussed with respect to Figure 2D, the dielectric layer 108 can optionally be subjected to selective passivation of its exposed portions. In some examples and in accordance with an embodiment, passivation of the exposed surface of dielectric layer 108 may be filled from bottom to top of metal layer 116 lift feature 106 (as discussed above with respect to FIG. 2E).

As will be appreciated in light of the present disclosure, dielectric layer 108 may be partially or completely passivated using any suitable passivation material and technique. For example, in some cases, the dielectric layer 108 can be selectively passivated using one or more self-assembled monolayers (SAMs). Such as It will be understood in accordance with the present disclosure that selective dielectric passivation of dielectric layer 108 via SAM can occur from a vapor phase or from molecules (or both) dissolved in a solvent. In some cases, one or more SAMs preferentially attached to the oxidized surface can be used to selectively passivate the dielectric layer 108, such as phosphoric acid, thiols, carboxylic acid. And ammonia. Some suitable examples include n-octadecylphosphonic acid (ODPA; octadecylphosphonic acid), octadecanethiol (ODT; 1-octadecanethiol), and octadecanoic acid (ODCA; stearic acid). ). In some cases, the dielectric layer 108 can be selectively passivated using one or more SAMs preferentially attached to the dielectric surface, such as chloro-, alkoxy- And amino-silanes having an alkane chain length in the range of 1 to 20 carbons. Some suitable examples include organosilicon complexes such as octadecyltrichlorosilane (ODTCS; octadecyltrichlorosilane), octadecyltris (dimethylamino)silane, and Octadecyltrimethoxydecane (ODTMS; octadecyltrimethoxysilane). In some examples, a passivant may be selected so as not to react with either or both of WFM layer 112, dielectric layer 102, and dielectric layer 108 (or otherwise negligible reaction). In a more general sense and in accordance with some embodiments, any of the materials and techniques described above or in combination may be used to provide selective passivation of the dielectric layer 108. Passivation of materials due to reactivity with any surrounding materials If the selectivity is insufficient, then any unwanted passivant material can be removed from the surface in which the passivation is not intended to use thermal annealing, wet etching, and dry etching processes.

3A-3E illustrate an IC manufacturing process flow for forming an IC 100B in accordance with another embodiment of the present disclosure. According to some embodiments, the process flow of FIGS. 3A-3E can be used to selectively deposit a filler material (eg, by a three-dimensional n-type metal-oxide-semiconductor device) in a three-dimensional metal-oxide-semiconductor device. The gate material) is provided from bottom to top. Other suitable uses of the process flow of Figures 3A-3E will be apparent in light of this disclosure.

The process can begin as in Figure 3A, which is a cross-sectional view of an IC 100B configured in accordance with another embodiment of the present disclosure. As can be seen, the IC 100B can include a dielectric layer 102 patterned with features 106 as discussed above. Again, as can be seen from FIG. 3A, IC 100B can include semiconductor body 104 disposed within dielectric layer 102 and protruding into feature 106, causing side-by-side semiconductor body 104 to appear in dielectric layer 102 as discussed above. One or more grooves (or holes) 106a. As can be further seen from FIG. 3A, IC 100B can include dielectric layer 108, barrier layer 110, and WFM layer 112 as discussed above.

However, in accordance with some embodiments, unlike the IC 100A discussed above, the IC 100B may further include a barrier layer 113 formed over the WFM layer 112. The barrier layer 113 can be formed from any of a wide variety of materials. For example, in some cases, the barrier layer 113 may be formed from a metal such as tantalum (Ta), titanium (Ti), or manganese (Mn). In some cases, it can form from nitride The barrier layer 113 is, for example, tantalum nitride (TaN), titanium nitride (TiN) or manganese nitride (MnN). In a more general sense and in accordance with some embodiments, the barrier layer 113 can be formed from any one or combination of the foregoing materials.

As will be appreciated in light of this disclosure, the barrier layer 113 can be formed, for example, with respect to any of the example dimensions, geometries, and techniques discussed above for the dielectric layer 108, in accordance with some embodiments. In some examples, the barrier layer 113 can at least initially extend from the bottom portion 106b of the feature 106 to the full height of the sidewall portion 106c of the feature 106. In some examples, the barrier layer 113 can extend from the bottom portion 106b of the feature 106 to a full height below the sidewall portion 106c of the feature 106. According to some embodiments, the barrier layer 113 can be at least partially as, for example, a seed layer for the metal layer 116 (discussed above and below with respect to FIG. 3E). Other suitable materials, dimensions, geometries, and forming techniques for the barrier layer 113 will depend on the given application and will be apparent in light of this disclosure.

The process can continue as in FIG. 3B, which is a cross-sectional view of IC 100B of FIG. 3A after forming a layer of fill material 114 in accordance with an embodiment of the present disclosure. As can be seen, the fill material 114 (discussed above) can be disposed within the features 106 above the barrier layer 113, the WFM layer 112, the barrier layer 110, and the dielectric layer 108 (eg, in a recess alongside the semiconductor body 104). / hole 106a). As noted above, in accordance with some embodiments, the filler material 114 may generally be considered to be a sacrificial filler material. Any or a combination of the CMP process and the etching and cleaning processes as discussed above may be used to remove unwanted excess fill material 114 (eg, an overlying layer that may spread over the upper surface of IC 100B).

The process may continue as in FIG. 3C, which is a cross-sectional view of IC 100B of FIG. 3B after partial removal of barrier layer 113 and fill material 114 in accordance with some embodiments of the present disclosure. In accordance with some embodiments, as will be appreciated in accordance with the present disclosure, the fill material 114 and the barrier layer 113 can be partially removed from the feature 106 using any suitable technique, including, for example, the control of FIG. 2C and the partial removal of the fill material 114 discussed above. Any of these example techniques. According to some embodiments, the partial removal of the fill material 114 may occur sequentially or simultaneously with partial removal of the barrier layer 113. As will be understood in accordance with the present disclosure, the same etchant used to partially remove the fill material 114 and the barrier layer 113 at the same time is also used to remove residuals that subsequently remove the fill material 114 (eg, as described below with respect to FIG. 3D). As discussed, then as desired for a given target application or terminal usage, it may be desirable to ensure proper processing timing. According to some embodiments, when the fill material 114 and the barrier layer 113 are removed from the feature 106, the fill material 114 and the barrier layer 113 may, for example, only partially remain in the bottom portion 106b of the feature 106. In some examples, the barrier layer 113 can extend from the bottom portion 106b of the feature 106 to a full height below the sidewall portion 106c of the feature 106.

The process can continue as in FIG. 3D, which is a cross-sectional view of IC 100B of FIG. 3C after removal of the residue of fill material 114 in accordance with an embodiment of the present disclosure. As will be appreciated in accordance with the present disclosure, any of the techniques discussed above may be used for this purpose, such as with reference to FIG. 3C and partially removing fill material 114 and barrier layer 113, in accordance with some embodiments.

According to an embodiment, the barrier layer 113 may still only partially remain, for example, at the bottom portion of the feature 106 when the residue of the filler material 114 is removed. 106b. Portions of the barrier layer 113 above the bottom portion 106b may be at least partially as, for example, a seed layer for the metal layer 116 (discussed below). The WFM layer 112 and the barrier layer 110 may remain above the bottom portion 106b of the feature 106 and optionally over the sidewall portion 106c of the feature 106.

The process can continue as in FIG. 3E, which is a cross-sectional view of IC 100B of FIG. 3D after formation of metal layer 116 in accordance with an embodiment of the present disclosure. A thin layer (eg, a seed layer) of the metal layer 116 (discussed above) to the barrier layer 113 can be selectively formed (eg, selectively deposited or otherwise selectively grown) over the bottom portion 106b of the feature 106. Above. According to some embodiments, the metal layer 116 may be selectively formed at least initially in this manner without being formed on the WFM layer 112. For this purpose, the metal layer 116 can be formed using any suitable technique as discussed above. In some cases and in accordance with an embodiment, the metal layer 116 may initially be grown only on a thin layer (eg, a seed layer) of the barrier layer 113, resulting in a seamless seam of the metal layer 116 within the feature 106 around the semiconductor body 104, Bottom-up fill. As metal layer 116 reaches and clears the top of semiconductor body 104, growth of metal layer 116 may continue inwardly of feature 106. In some cases, as metal layer 116 clears the top of semiconductor body 104, voids or seams may be formed in region 118 of feature 106 as discussed above. If desired, the presence of such voids or seams can be eliminated or otherwise reduced as described above.

According to some embodiments, after partially removing the fill material 114 and the barrier layer 113 (eg, as discussed above with respect to FIG. 3C) or after removal After the residue of fill material 114 (e.g., as discussed above with respect to Figure 3D), WFM layer 112 optionally suffers from selective passivation of any of its exposed surfaces. In some examples and in accordance with an embodiment, passivation of the exposed surface of WFM layer 112 may be filled from bottom to top of metal layer 116 lift feature 106 (as discussed above with respect to FIG. 3E). In accordance with some embodiments, passivation of the WFM layer 112 may be provided using, for example, any of the example materials and techniques discussed above with respect to selected passivation of the dielectric layer 108. Moreover, in accordance with some embodiments, any unwanted passivating material can be removed from the surface in which the passivation system is not intended to use any of the thermal annealing, wet etching processes, and dry etching processes discussed above or in combination.

Dielectric layer 108 may be selectively formed within feature 106 in accordance with some embodiments. For example, consider Figures 4-5, which are cross-sectional views of IC 100A ' and IC 100B ' configured in accordance with some embodiments of the present disclosure, respectively. As can be seen herein, the dielectric layer 108 can be formed over the semiconductor body 104 and the bottom portion 106b of the feature 106, for example, but not over the sidewall portion 106c of the feature 106. In some examples, the dielectric layer 108 may extend from the bottom portion 106b of the feature 106 to the sidewall portion 106c of the feature 106 by a thickness approximately equal to the thickness of the dielectric layer 108.

To this end, in accordance with some embodiments, a sacrificial barrier layer (such as, for example, any of the SAM materials discussed above) may be formed over a given surface (eg, sidewall portion 160c), wherein dielectric layer 108 is undesirable. And selective atomic layer deposition (ALD) can be utilized to deposit the dielectric material of the dielectric layer 108. The molecules of the applied SAM material can form a blanket monolayer that blocks deposition of the dielectric layer 108, for example, on the sidewall portion 106c (or any other desired portion) of the feature 106. According to some embodiments, the applied SAM material can be subsequently removed, for example, via a thermal treatment. In some cases, heat treatment at a temperature in the range of about 200 to 400 ° C (for example, about 200 to 250 ° C, about 250 to 300 ° C, about 300 to 350 ° C, about 350 to 400 ° C, or about 200 to 400 Any other sub-range in the range of °C) may be sufficient to remove any applied SAM material. As will be understood in accordance with the present disclosure, due to the low temperature at which a given SAM barrier layer will thermally decompose there, it may be desirable to adequately provide low temperature formation of the dielectric layer 108 to avoid premature degradation of the SAM layer (premature) Degradation). In some examples and in accordance with some embodiments, a low temperature ALD process for dielectric materials such as hafnium oxide (HfO ₂ ) or zirconium dioxide (ZrO ₂ ) may be utilized. For example, in the ALD process, tetrakis(dimethylamido)hafnium will react with water at about 250 ° C to form an HfO ₂ film in accordance with the following relationship:

As will be appreciated in accordance with the present disclosure, the exposed sidewall portion 106c of the feature 106 (eg, as in FIG. 4) or the WFM layer 112 (eg, as in FIG. 5) in the dielectric layer 102, in accordance with some embodiments. Optionally, selective passivation can be selectively performed with any of the example passivation materials (e.g., SAM) and techniques discussed above with respect to optional selective passivation of dielectric layer 108.

As previously noted, the techniques disclosed herein can be used, for example, in forming gate structures and source/drain contacts structures, in accordance with some embodiments. For example, consider Figure 6, which is a cross-sectional view of a source/drain (S/D) contact 200 configured in accordance with an embodiment of the present disclosure. As can be seen, the S/D contact 200 can include a dielectric layer 102 and a semiconductor body 104 (both discussed above).

The S/D contact 200 can also include a dielectric layer 103. As will be appreciated in accordance with the present disclosure, dielectric layer 103 can be formed, for example, in contrast to dielectric layer 102 in any of the example materials, dimensions, geometries, and techniques discussed above. In some cases, dielectric layer 103 can be of a different material composition than dielectric layer 102.

As can be further seen from FIG. 6, the S/D contact 200 can also include an epitaxial semiconductor body 105 formed over the semiconductor body 104. The epitaxial semiconductor body 105 can be, for example, a three-dimensional semiconductor structure. As will be appreciated in accordance with the present disclosure, the epitaxial semiconductor body 105 can be formed, for example, against the semiconductor body 104 in any of the example materials discussed above. As will be appreciated in light of this disclosure, any suitable technique can be used to form the epitaxial semiconductor body 105. For example, in some cases, an epitaxy process such as metalorganic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MPE), atomic layer can be used. The epitaxial semiconductor body 105 is formed by any one or a combination of a deposition process (ALD) and a chemical vapor deposition (CVD) process. The dimensions and geometry of the epitaxial semiconductor body 105 can be customized as desired for a given target application or terminal. Other suitable materials, dimensions, geometries, and formation techniques for the epitaxial semiconductor body 105 It will depend on the given application and will be apparent in light of this disclosure.

According to some embodiments, the dielectric layer 103 may be etched back to reveal the top surface of the epitaxial semiconductor body 105, and the contact metal layer 107 may be formed over the exposed top surface of the epitaxial semiconductor body 105. Contact metal layer 107 can be formed from any suitable conductive metal or metal halide. For example, in some cases, the contact metal layer 107 may be formed from either or a combination of nickel niobide (NiSi _x ) and cobalt telluride (CoSi _x ). In some other cases, the contact metal layer 107 can be formed, for example, from any of the exemplary conductive materials discussed above with respect to the metal layer 116.

It will be apparent in light of the present disclosure that the contact metal layer 107 can be formed using any suitable technique. For example, in some cases, the contact metal layer 107 may be formed using any one or combination of a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, and an atomic layer deposition (ALD) process. The dimensions and geometry of the contact metal layer 107 can be customized as desired for a given target application or terminal, and in some cases can depend, at least in part, on the topography of the underlying epitaxial semiconductor body 105. Other suitable materials, dimensions, geometries, and forming techniques for contacting metal layer 107 will depend on the particular application and will be apparent in light of this disclosure.

As can be further seen from FIG. 6, the S/D contact 200 can also include a dielectric layer 108 formed over the topography provided by the underlying contact metal layer 107 (and possibly the dielectric layer 103), Barrier layer 110 and WFM layer 112 (each of which has been discussed above). According to some embodiments, the contact metal layer can be formed over the topography of the underlying layer provided by, for example, the WFM layer 112. 120. As will be appreciated in accordance with the present disclosure, contact metal layer 120 can be formed, for example, with respect to metal layer 116 in any of the example materials and techniques discussed above, in accordance with some embodiments. The dimensions and geometry of the contact metal layer 120 can be customized as desired for a given target application or terminal, and in some cases can depend, at least in part, on the dimensions and geometry of the recess 106. Other suitable materials, dimensions, geometries, and forming techniques for contacting metal layer 120 will depend on the particular application and will be apparent in light of this disclosure.

Sample system

FIG. 7 illustrates a computing system 1000 implemented in accordance with an exemplary embodiment using an integrated circuit structure or apparatus formed using the disclosed techniques. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 can include a number of components including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically or electrically coupled to the motherboard 1002 or otherwise integrated therein. As will be appreciated, the motherboard 1002 can be, for example, any printed circuit board, whether it be a motherboard, a daughterboard mounted on the motherboard, or the only board of the system 1000. Depending on its application, computing system 1000 can include one or more other components that may or may not be physically and electrically coupled to motherboard 1002. These other components may include, but are not limited to, volatile memory (eg, DRAM), non-volatile memory (eg, ROM), graphics processors, digital signal processors, crypto processors, chipsets , antenna, display, touch screen display, touch screen control , battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera and mass storage device It is a hard disk drive, a compact disc (CD), a digital versatile disc (DVD), etc.). In accordance with an embodiment, any of the components included in computing system 1000 can include one or more integrated circuit structures or devices formed using the disclosed techniques. In some embodiments, multiple functions may be integrated into one or more of the wafers (eg, note that communication chip 1006 can be, for example, part of processor 1004 or otherwise integrated into processor 1004).

Communication chip 1006 enables wireless communication for transmitting data to and from computing system 1000. The term "wireless" and derived therefrom can be used to describe circuits, devices, systems, methods, techniques, communication channels, and the like that can communicate data using electromagnetic emissions modulated by non-solid media. The term does not imply that the associated device does not contain any lines, although in some embodiments they may not. The communication chip 1006 can be configured with any number of wireless standards or protocols including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+ , HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocol defined as 3G, 4G, 5G and above. Computing system 1000 can include a plurality of communication chips 1006. For example, the first communication chip 1006 can be dedicated to shorter range wireless communication, such as Wi-Fi and Bluetooth, and second. The communication chip 1006 can be dedicated to a longer range of wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

Processor 1004 of computing system 1000 encapsulates the integrated circuit die packaged within processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry built using one or more integrated circuit structures or devices formed using the techniques disclosed in the various aspects of the description. The term "processor" may refer to any portion of any device or device that processes, for example, electronic data from a register and/or memory to transform the electronic data into storables and/or memory.

The communication chip 1006 can also include integrated circuit dies that are packaged within the communication chip 1006. In accordance with some such exemplary embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the techniques disclosed herein. As will be appreciated in light of this disclosure, it is noted that multiple standard wireless capabilities can be directly integrated into the processor 1004 (eg, where the functionality of any of the chips 1006 is integrated into the processor 1004, rather than having separate communication chips) . It is further noted that the processor 1004 can be a chipset having such wireless capabilities. In short, any number of processors 1004 and/or communication chips 1006 can be used. Also, any one wafer or wafer set can have multiple functions integrated therein.

In various configurations, the computing device 1000 can be a laptop, a netbook, a notebook, a smart phone, a tablet, a personal digital assistant (PDA), an ultra mobile PC (ultra- Mobile PC), mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder or processing data Or any other electronic device using one or more integrated circuit structures or devices formed using the techniques disclosed herein in various aspects.

Further example embodiments

The following examples are further examples, from which numerous permutations and configurations will be apparent.

Example 1 is an integrated circuit comprising: a first dielectric layer having features patterned therein, the feature having a bottom portion and a sidewall portion, and the semiconductor body extends through the bottom portion of the feature; a second dielectric layer, Arranging in the feature on the semiconductor body and the bottom portion of the feature, wherein the second dielectric layer is higher in dielectric constant than the first dielectric layer; the seed layer is disposed in the second At least a portion of the dielectric layer is over the feature; and a metal layer disposed over the seed layer, wherein: the metal layer and the seed layer are of different material composition; and the metal layer does not have the semiconductor body Side by side seams and at least one of the apertures.

Example 2 includes the subject matter of any of Examples 1, 3 to 5, 13-14, and 16-19, wherein the seed layer includes a work function metal (WFM) layer.

Example 3 includes the subject matter of Example 2, wherein the WFM layer includes tungsten (W), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), vanadium nitride (VN), tantalum nitride (NbN), and At least one of zirconium nitride (ZrN); and having an average thickness in the range of about 0.1 to 3 nm.

Example 4 includes the subject matter of Example 2, wherein the WFM layer extends from a bottom portion of the feature to a full height below a sidewall portion of the feature.

Example 5 includes the subject matter of any one of Examples 1 to 4, 13 to 14, and 16 to 19, wherein at least a portion of the second dielectric layer is passivated with a self-assembled monolayer (SAM), the SAM comprising Octamethylphosphonic acid (ODPA), octadecyl mercaptan (ODT), octadecanoic acid (ODCA), octadecyltrichlorodecane (ODTCS), octadecyltris(dimethylamino)decane ( At least one of ODTAS) and octadecyltrimethoxydecane (ODTMS).

Example 6 includes the subject matter of any of Examples 1, 7-13, and 15-19, wherein the seed layer includes a barrier layer.

Example 7 includes the subject matter of Example 6, wherein the barrier layer comprises: tantalum (Ta), titanium (Ti), manganese (Mn), tantalum nitride (TaN), titanium nitride (TiN), and manganese nitride (MnN). At least one; and having an average thickness in the range of about 0.1 to 3 nm.

Example 8 includes the subject matter of Example 6, wherein the barrier layer extends from the bottom portion of the feature to the full height of the sidewall portion of the feature.

Example 9 includes the subject matter of Example 6 and further includes a WFM layer disposed over at least a portion of the second dielectric layer between the second dielectric layer and the seed layer.

Example 10 includes the subject matter of Example 9, wherein the WFM layer comprises: tungsten (W), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), vanadium nitride (VN), tantalum nitride (NbN), and At least one of zirconium nitride (ZrN); and having an average thickness in the range of about 0.1 to 3 nm.

Example 11 includes the subject matter of Example 9, wherein the WFM layer extends from the bottom portion of the feature to the full height of the sidewall portion of the feature.

Example 12 includes the subject matter of Example 9, wherein at least a portion of the WFM layer is passivated with a self-assembled monolayer (SAM) comprising n-octadecylphosphonic acid (ODPA), octadecanethiol (ODT) At least one of octadecanoic acid (ODCA), octadecyltrichlorodecane (ODTCS), octadecyltris(dimethylamino)decane (ODTAS), and octadecyltrimethoxydecane (ODTMS) By.

The example 13 includes the target of any one of the examples 1 to 12 and 14 to 19, and further includes a barrier layer disposed on the at least a portion of the second dielectric layer between the second dielectric layer and the seed layer Within the feature.

Example 14 includes the subject matter of Example 13, wherein the barrier layer extends from the bottom portion of the feature to a full height below the sidewall portion of the feature; and has an average thickness in the range of about 0.1 to 3 nm.

Example 15 includes the subject matter of Example 13, wherein the barrier layer extends from the bottom portion of the feature to a full height of the sidewall portion of the feature; and has an average thickness in the range of about 0.1 to 3 nm.

Example 16 includes the subject matter of any one of Examples 1 to 15 and 17 to 19, wherein the seed dielectric layer comprises: hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), zirconium dioxide (ZrO ₂ ) , lanthanum oxide (Ta ₂ O ₅ ), titanium dioxide (TiO ₂ ), lanthanum oxide (La ₂ O ₃ ), yttrium oxide (Gd ₂ O ₃ ), ceric acid (HfSiO _x ), aluminum silicate (AlSiO _x ) , zirconium silicate (ZrSiO _x), tantalum silicate (TaSiO _x), titanium silicate (TiSiO _x), lanthanum silicate (LaSiO _x) and gadolinium silicate (GdSiO _x) is at least one; and having about 0.1 Average thickness in the range of ~3 nm.

Example 17 includes the subject matter of any one of Examples 1-16 and 18-19, wherein the second dielectric layer extends from the bottom portion of the feature to the sidewall portion of the feature equal to the thickness of the second dielectric layer the height of.

Example 18 includes the subject matter of any of Examples 1-17 and 19, wherein the second dielectric layer extends from the bottom portion of the feature to a full height of the sidewall portion of the feature.

Example 19 includes the subject matter of any of Examples 1-18, wherein the portion of the metal layer directly over the semiconductor body has at least one of a seam and a void therein.

Example 20 is a method of forming an integrated circuit, the method comprising: providing a first dielectric layer having features patterned therein, the feature having a bottom portion and a sidewall portion, and the semiconductor body extends through the bottom of the feature Forming a second dielectric layer over the semiconductor body and the bottom portion of the feature, wherein the second dielectric layer is higher in dielectric constant than the first dielectric layer; Forming a seed layer over the dielectric layer; and forming a metal layer over the seed layer, wherein: the metal layer and the seed layer are of different material composition; and the metal layer does not have a seam alongside the semiconductor body And at least one of the pores.

Example 21 includes the subject matter of any of the examples 20, 22-25, 31-32, and 34-37, wherein the seed layer includes a work function metal (WFM) layer, and the method further includes: the WFM layer within the feature A filler material is deposited thereon, wherein the filler material comprises at least one of cerium oxide (SiO ₂ ), tungsten (W), and a carbide hard mask.

Example 22 includes the subject matter of Example 21 and further comprising: removing portions of each of the fill material and the WFM layer from the feature such that each of the fill material and the WFM layer remain partially at the bottom portion of the feature Where the WFM layer extends from the bottom portion of the feature to a full height below the sidewall portion of the feature.

Example 23 includes the subject matter of Example 22 and further includes removing residuals of the fill material from the feature.

Example 24 includes the subject matter of Example 23 and further comprising: initially selectively depositing the metal layer only over the WFM layer; and growing the metal layer to fill the feature, wherein the metal layer does not have side-by-side with the semiconductor body At least one of seams and voids.

Example 25 includes the subject matter of any of Examples 20-24, 31-32, and 34-37 and further comprising: passivating at least a portion of the second dielectric layer with a self-assembled monolayer (SAM), the SAM comprising positive Octadecylphosphonic acid (ODPA), octadecyl mercaptan (ODT), octadecanoic acid (ODCA), octadecyltrichlorodecane (ODTCS), octadecyltris(dimethylamino)decane At least one of (ODTAS) and octadecyltrimethoxydecane (ODTMS).

Example 26 includes the subject matter of any one of Examples 20, 27-31, and 33-37, wherein the seed layer includes a barrier layer, and the method includes: the second dielectric between the second dielectric layer and the seed layer a success function metal (WFM) layer overlying the electrical layer; and depositing a fill material over the barrier layer within the feature, wherein the fill material comprises cerium oxide (SiO ₂ ), tungsten (W), and a carbide hard mask At least one of them.

Example 27 includes the subject matter of Example 26 and further comprising: removing portions of each of the filler material and the barrier layer from the feature such that each of the filler material and the barrier layer partially remain in the bottom portion of the feature Where the barrier layer extends from the bottom portion of the feature to a full height below the sidewall portion of the feature.

Example 28 includes the subject matter of Example 27 and further includes removing residuals of the fill material from the feature.

Example 29 includes the subject matter of Example 28 and further comprising: initially selectively depositing the metal layer only over the barrier layer; and growing the metal layer to fill the feature, wherein the metal layer does not have side-by-side with the semiconductor body At least one of the seams and the voids.

Example 30 includes the subject matter of Example 26 and further comprising: passivating at least a portion of the WFM layer with a self-assembled monolayer (SAM) comprising n-octadecylphosphonic acid (ODPA), octadecanethiol ( ODT), octadecanoic acid (ODCA), octadecyltrichlorodecane (ODTCS), octadecyltris(dimethylamino)decane (ODTAS), and octadecyltrimethoxydecane (ODTMS) At least one.

Example 31 includes the subject matter of any of Examples 20-30 and 32-37 and further comprising: forming a barrier layer over the second dielectric layer between the second dielectric layer and the seed layer.

Example 32 includes the subject matter of Example 31, wherein the barrier layer extends from the bottom portion of the feature to a full height below the sidewall portion of the feature.

Example 33 includes the subject matter of Example 31, wherein the barrier layer extends from the bottom portion of the feature to the full height of the sidewall portion of the feature.

Example 34 includes the subject matter of any one of Examples 20 to 33 and 35 to 37, wherein the second dielectric layer extends from the bottom portion of the feature to the sidewall portion of the feature equal to the thickness of the second dielectric layer the height of.

Example 35 includes the subject matter of any of Examples 20-34 and 36-37, the second dielectric layer extending from the bottom portion of the feature to the full height of the sidewall portion of the feature.

The example 36 includes the subject matter of any of the examples 20-35 and 37, wherein the portion of the metal layer directly over the semiconductor body has at least one of a seam and a void therein.

Example 37 is an integrated circuit formed by a method including the subject matter of any of Examples 20 to 36.

Example 38 is an integrated circuit comprising: a first dielectric layer having a semiconductor fin extending therethrough; a second dielectric layer disposed over the semiconductor fin, wherein the second dielectric layer is a dielectric layer having a higher dielectric constant; a first barrier layer disposed over the second dielectric layer; a work function metal (WFM) layer disposed over the first barrier layer; and a first metal a layer disposed over the WFM layer, wherein the first metal layer does not have at least one of a seam and a void.

The example 39 includes the subject matter of any of the examples 38 and 40 and further includes a second barrier layer disposed over the WFM layer, wherein the first metal layer is disposed over the second barrier layer.

Example 40 includes the subject matter of any one of Examples 38-39 and 41-43, wherein the first metal layer has no seams and voids except in the region of the first metal layer directly above the semiconductor fin At least one of which The region has at least one of a seam and a void therein.

The example 41 includes the targets of any one of the examples 38, 40, and 42-43 and further includes: an epitaxial semiconductor body disposed on the semiconductor fin; and a second metal layer disposed on the epitaxial semiconductor body; The first metal layer is disposed on the epitaxial semiconductor body and the second metal layer and configured to serve as a source/drain junction.

Examples 42, wherein at least one of the second metal layer comprises a nickel silicide (NiSi _x) and cobalt silicide (CoSi _x) 41 comprises the subject matter of the examples.

Example 43 includes the subject matter of Example 41 and further comprising: a third dielectric layer, wherein the first dielectric layer is disposed in the third dielectric layer, wherein: the first and third dielectric layers are different material compositions And the second and third dielectric layers are of different material compositions.

The foregoing description of the exemplary embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the disclosure be not limited by the description The case of an application for which priority is claimed in the future may request the disclosed subject matter in a different manner, and may generally include one or more definitions of any of the groups disclosed or otherwise shown herein.

100A‧‧‧ integrated circuit

102‧‧‧ dielectric layer

104‧‧‧Semiconductor body

106‧‧‧ Notch

106a‧‧‧ Groove/hole section

106b‧‧‧ bottom part

106c‧‧‧ Sidewall section

108‧‧‧ dielectric layer

110‧‧‧Baffle layer

112‧‧‧Work function metal layer

Claims (25)

An integrated circuit comprising: a first dielectric layer having features patterned therein, the feature having a bottom portion and a sidewall portion, and the semiconductor body extends through the bottom portion of the feature; the second dielectric layer is disposed in The semiconductor body and the bottom portion of the feature are over the feature, wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer; a seed layer disposed on the second dielectric layer At least partially over the feature; and a metal layer disposed over the seed layer, wherein: the metal layer and the seed layer have different material compositions; and the metal layer does not have a seam alongside the semiconductor body And at least one of the pores. The integrated circuit of claim 1, wherein the seed layer comprises a work function metal (WFM) layer. The integrated circuit of claim 2, wherein the WFM layer comprises: tungsten (W), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), vanadium nitride (VN), tantalum nitride At least one of (NbN) and zirconium nitride (ZrN); having an average thickness in the range of about 0.1 to 3 nm; and extending from a bottom portion of the feature to a full height below a sidewall portion of the feature. The integrated circuit of claim 1, wherein at least part of the second dielectric layer is passivated by a self-assembled monolayer (SAM) comprising n-octadecylphosphonic acid (ODPA), ten Octanethiol (ODT), octadecanoic acid (ODCA), octadecyltrichlorodecane (ODTCS), octadecyltris(dimethylamino)decane (ODTAS), and octadecyltrimethoxy At least one of decane (ODTMS). The integrated circuit of claim 1, wherein the seed layer comprises a barrier layer. The integrated circuit of claim 5, wherein the barrier layer comprises tantalum (Ta), titanium (Ti), manganese (Mn), tantalum nitride (TaN), titanium nitride (TiN), and manganese nitride. At least one of (MnN); having an average thickness in the range of about 0.1 to 3 nm; and extending from the bottom portion of the feature to a full height of the sidewall portion below the feature. The integrated circuit of claim 5, further comprising a WFM layer disposed in the feature between at least a portion of the second dielectric layer between the second dielectric layer and the seed layer. The integrated circuit of claim 7, wherein the WFM layer comprises: tungsten (W), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), vanadium nitride (VN), tantalum nitride At least one of (NbN) and zirconium nitride (ZrN); Having an average thickness in the range of about 0.1 to 3 nm; and extending from the bottom portion of the feature to the full height of the sidewall portion of the feature. The integrated circuit of claim 7, wherein at least part of the WFM layer is passivated by a self-assembled monolayer (SAM) comprising n-octadecylphosphonic acid (ODPA), octadecane sulfur Alcohol (ODT), octadecanoic acid (ODCA), octadecyltrichlorodecane (ODTCS), octadecyltris(dimethylamino)decane (ODTAS), and octadecyltrimethoxydecane (ODTMS) At least one of them. The integrated circuit of claim 1, further comprising a barrier layer disposed in the feature between at least a portion of the second dielectric layer between the second dielectric layer and the seed layer, wherein the The barrier layer: extends from the bottom portion of the feature to a full height below the sidewall portion of the feature; and has an average thickness in the range of about 0.1 to 3 nm. The integrated circuit of claim 1, further comprising a barrier layer disposed in the feature between at least a portion of the second dielectric layer between the second dielectric layer and the seed layer, wherein the a barrier layer: extending from the bottom portion of the feature to the full height of the sidewall portion of the feature; and having an average thickness in the range of about 0.1 to 3 nm. The scope of the patent application integrated circuit to item 1, wherein the second dielectric layer: comprising hafnium dioxide (HfO _2), aluminum oxide (Al ₂ O _3), zirconium dioxide (ZrO _2), tantalum oxide (Ta ₂ O ₅ ), titanium dioxide (TiO ₂ ), lanthanum oxide (La ₂ O ₃ ), yttrium oxide (Gd ₂ O ₃ ), niobate (HfSiO _x ), aluminum niobate (AlSiO _x ), zirconium silicate ( ZrSiO _x), tantalum silicate (TaSiO _x), titanium silicate (TiSiO _x), lanthanum silicate (LaSiO _x) and gadolinium silicate (GdSiO _x) is at least one; with the range of about 0.1 ~ 3nm of the An average thickness; and a height of the sidewall portion of the feature extending from the bottom portion of the feature to a thickness equal to the thickness of the second dielectric layer. The integrated circuit of claim 1, wherein the second dielectric layer comprises: hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), zirconium dioxide (ZrO ₂ ), tantalum oxide (Ta) ₂ O ₅ ), titanium dioxide (TiO ₂ ), lanthanum oxide (La ₂ O ₃ ), yttrium oxide (Gd ₂ O ₃ ), niobate (HfSiO _x ), aluminum niobate (AlSiO _x ), zirconium silicate ( ZrSiO _x), tantalum silicate (TaSiO _x), titanium silicate (TiSiO _x), lanthanum silicate (LaSiO _x) and gadolinium silicate (GdSiO _x) is at least one; with the range of about 0.1 ~ 3nm of the An average thickness; and a full height from the bottom portion of the feature to the sidewall portion of the feature. The integrated circuit of any one of clauses 1 to 13, wherein the portion of the metal layer directly over the semiconductor body has at least one of a seam and a void therein. A method of forming an integrated circuit, the method comprising: providing a first dielectric layer having features patterned therein, the Having a bottom portion and a sidewall portion, and the semiconductor body extends through the bottom portion of the feature; forming a second dielectric layer over the semiconductor body and the bottom portion of the feature, wherein the second dielectric layer has The first dielectric layer also has a high dielectric constant; forming a seed layer over the second dielectric layer; and forming a metal layer over the seed layer, wherein: the metal layer and the seed layer have different material compositions; And the metal layer does not have at least one of seams and voids alongside the semiconductor body. The method of claim 15, wherein the seed layer comprises a work function metal (WFM) layer, and the method further comprises: depositing a filler material over the WFM layer within the feature, wherein the filler material comprises cerium oxide At least one of (SiO ₂ ), tungsten (W), and a carbide hard mask. The method of claim 16, further comprising: removing a portion of each of the filler material and the WFM layer from the feature such that each of the filler material and the WFM layer partially retains the feature In the bottom portion, wherein the WFM layer extends from the bottom portion of the feature to a full height below the sidewall portion of the feature; removing the residue of the fill material from the feature; initially selecting only above the WFM layer Depositing the metal layer; and growing the metal layer to fill the feature, wherein the metal layer does not have At least one of a seam and a void of the semiconductor body side by side. The method of claim 15, wherein the seed layer comprises a barrier layer and the method further comprises: forming a success function metal (WFM) over the second dielectric layer between the second dielectric layer and the seed layer a layer; and depositing a filler material over the barrier layer within the feature, wherein the filler material comprises at least one of cerium oxide (SiO ₂ ), tungsten (W), and a carbide hard mask. The method of claim 18, further comprising: removing a portion of each of the filler material and the barrier layer from the feature such that each of the filler material and the barrier layer partially retains the feature In the bottom portion, wherein the barrier layer extends from the bottom portion of the feature to a full height below the sidewall portion of the feature; the residue of the filler material is removed from the feature; initially only selected over the barrier layer The metal layer is deposited; and the metal layer is grown to fill the feature, wherein the metal layer does not have at least one of seams and voids alongside the semiconductor body. The method of claim 15, further comprising: forming a barrier layer over the second dielectric layer between the second dielectric layer and the seed layer. An integrated circuit comprising: a first dielectric layer having a semiconductor fin extending therethrough; a second dielectric layer disposed over the semiconductor fin, wherein the second dielectric The electrical layer has a higher dielectric constant than the first dielectric layer; a first barrier layer disposed over the second dielectric layer; and a work function metal (WFM) layer disposed over the first barrier layer And a first metal layer disposed over the WFM layer, wherein the first metal layer does not have at least one of a seam and a void. The integrated circuit of claim 21, further comprising a second barrier layer disposed on the WFM layer, wherein the first metal layer is disposed on the second barrier layer. The integrated circuit of claim 21, wherein the first metal layer does not have at least one of a seam and a void, except in a region directly in the first metal layer above the semiconductor fin, wherein The region has at least one of a seam and a void therein. The integrated circuit of claim 21, further comprising: an epitaxial semiconductor body disposed on the semiconductor fin; and a second metal layer disposed on the epitaxial semiconductor body, wherein the second metal layer And comprising at least one of nickel hydride (NiSi _x ) and cobalt hydride (CoSi _x ); wherein the first metal layer is disposed on the epitaxial semiconductor body and the second metal layer and configured to serve as a source/汲Extreme contact. The integrated circuit of claim 24, further comprising: a third dielectric layer, wherein the first dielectric layer is disposed in the third dielectric layer, wherein: the first and third dielectric layers have Different material compositions; The second and third dielectric layers have different material compositions.