TW201635698A - Amplification Systems and Methods with Output Regulation - Google Patents

Abstract

Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes: a first channel configured to receive a first input signal and a second input signal and generate a first output signal and a second output signal based at least in part on the first input signal and the second input signal; and a second channel configured to receive a third input signal and a fourth input signal and generate a third output signal and a fourth output signal based at least in part on the third input signal and the fourth input signal. A first differential signal is equal to the first input signal minus the second input signal. A second differential signal is equal to the third input signal minus the fourth input signal. The first output signal corresponds to a first phase.

Description

System and method for amplifying a plurality of input signals and modulating and generating a plurality of output signals

Certain embodiments of the invention relate to integrated circuits. More specifically, some embodiments of the present invention provide systems and methods for output adjustment. By way of example only, some embodiments of the invention have been applied to an amplification system. However, it should be recognized that the invention has a broader scope of applicability.

Fig. 1 is a simplified conventional diagram showing an amplification system using a class D amplifier having one channel. The amplification system 100 includes a modulator 102, an output stage 104, a low pass filter 106, and an output load 116. Modulator 102 includes an oscillator 108, a comparator 110, and a loop filter 112. For example, the output load 116 is a speaker. In another example, modulator 102, output stage 104, and low pass filter 106 are included in a class D amplifier. In another example, low pass filter 106 includes one or more inductors and/or one or more capacitors. In another example, low pass filter 106 includes one or more Bead Cores and/or one or more capacitors.

Loop filter 112 receives input audio signal 118 and output signal 120 (eg, a pulse width modulated signal) and outputs filtered signal 122 to comparator 110. For example, input audio signal 118 includes a pair of input signals. Oscillator 108 generates clock signal 126 (CLK) and ramp signal 124 (RAMP), which is received by comparator 110. Comparator 110 outputs a comparison signal 128 indicative of a comparison between ramp signal 124 and filtered signal 122. Output stage 104 receives comparison signal 128 and generates output signal 120 (PWM OUT). Low pass filter 106 converts output signal 120 to audio signal 130 to drive output load 116. As shown in FIG. 1, a single channel including modulator 102 and output stage 104 is implemented. Multiple channels can be used for audio amplification applications.

In one embodiment, loop filter 112 amplifies the error signal between input audio signal 118 and the feedback signal associated with output signal 120. For example, loop filter 112 includes a low pass filter that has a very high gain in the low frequency range (eg, a high gain greater than 1000) and a very low gain in the high frequency range (eg, a low gain that is much less than one). In another example, If the signal includes a low frequency component and a high frequency component, the loop filter 112 amplifies the low frequency component with a high gain and amplifies the high frequency component with a low gain (for example, a low gain much smaller than 1). In another example, if the high frequency component is close to the switching frequency of the amplification system 100, the loop filter 112 attenuates the high frequency component. In one embodiment, loop filter 112 includes one or more analog integrator stages.

Figure 2 is a simplified conventional diagram of an amplification system with multiple channels. The amplification system 200 includes a plurality of channels 202 ₁ , . . . , 202 _n , . . . , 202 _N , where N 2 and 1 n N. The first channel 202 ₁ includes a loop filter 204 ₁ , comparators 206 ₁ and 208 ₁ , a logic controller 210 ₁ , driving elements 212 ₁ and 214 ₁ , transistors 216 ₁ , 218 ₁ , 220 ₁ and 222 ₁ , And a low pass filter 224 ₁ . Logic controller 210 ₁ includes one or more buffers. For example, low pass filter 224 ₁ includes one or more inductors and/or one or more capacitors. In another example, low pass filter 224 ₁ includes one or more bead cores and/or one or more capacitors. The other channels have elements similar to the first channel. As shown in FIG. 2, these channels 202 ₁ , . . . , 202 _n , . . . , 202 _N share a common ramp signal 228 and generate an output signal (eg, 234 ₁ , . . . , 234 _n , . . . , 234 _N and/or 236). ₁ , ..., 236 _n , ..., 236 _N ) such that the audio signals are supplied to the output loads 226 ₁ , ..., 226 _n , ..., 226 _N (e.g., speakers), respectively.

In one embodiment, loop filter 204 ₁ amplifies the error signal between the input differential signal and the feedback differential signal associated with the output differential signal. The input differential signal represents the difference between the input signals 230 ₁ and 232 ₁ and the output differential signal represents the difference between the output signals 234 ₁ and 236 ₁ . For example, loop filter 204 ₁ is a low pass filter and it has a very high gain in the low frequency range (eg, a high gain greater than 1000) and a very low gain in the high frequency range (eg, much less than 1 low) Gain). In another example, if the signal includes a low frequency component and a high frequency component, the loop filter 204 ₁ amplifies the low frequency component with a high gain and amplifies the high frequency with a low gain (eg, a low gain much smaller than 1). Component. In another example, if the high frequency component is close to the switching frequency of the amplification system 200, the loop filter 204 ₁ attenuates the high frequency component. In one embodiment, loop filter 204 ₁ includes one or more analog integrator stages. In some embodiments, the loop filter in the other channels is the same as the loop filter 204 ₁ .

Figure 3 is a simplified general diagram of an amplification system comprising two channels. Amplification system 1700 includes two channels 1702 ₁ and 1702 ₂ . The first channel 1702 ₁ includes a loop filter 1704 ₁ , comparators 1706 ₁ and 1708 ₁ , a logic controller 1710 ₁ , drive elements 1712 ₁ and 1714 ₁ , transistors 1716 ₁ , 1718 ₁ , 1720 ₁ and 1722 ₁ , And a low pass filter 1724 ₁ . Logic controller 1710 ₁ includes one or more buffers. For example, low pass filter 1724 ₁ includes one or more inductors and/or one or more capacitors. In another example, low pass filter 1724 ₁ includes one or more bead cores and/or one or more capacitors. The second channel 1702 ₂ has elements similar to the first channel. As shown in FIG. 3, the two channels 1702 ₁ and 1702 ₂ share a common ramp signal 1728 (RAMP) and generate an output signal (eg, 1734 ₁ , 1734 ₂ and/or 1736 ₁ , 1736 ₂ ) to cause an audio signal. They are supplied to output loads 1726 ₁ and 1726 ₂ (for example, speakers).

For example, loop filter 1704 ₁ amplifies the error signal between the input differential signal and the feedback differential signal associated with the output differential signal. The input differential signal represents the difference between the input signals 1730 ₁ and 1732 ₁ and the output differential signal represents the difference between the output signals 1734 ₁ and 1736 ₁ . For example, loop filter 1704 ₁ is a low pass filter and it has a very high gain in the low frequency range (eg, a high gain greater than 1000) and a very low gain in the high frequency range (eg, much less than 1 low) Gain). In another example, if the signal includes a low frequency component and a high frequency component, the loop filter 1704 ₁ amplifies the low frequency component with a high gain and amplifies the high frequency with a low gain (eg, a low gain much smaller than 1). Component. In another example, if the high frequency component is close to the switching frequency of the amplification system 1700, the loop filter 1704 ₁ attenuates the high frequency component. In one embodiment, loop filter 1704 ₁ includes one or more analog integrator stages. In some embodiments, loop filter 1704 _{2 is the} same as loop filter 1704 ₁ .

Section 4 (a) FIG channel when the input differential signals ₁₇₀₂₁ and ₁₇₀₂₂ are equal to 0 enlarged simplified timing diagram of the conventional system of 1700 volts. Waveform 2802 represents the input differential signal of channel 1702 ₁ as a function of time, waveform 2804 represents output signal 1736 ₁ as a function of time, waveform 2806 represents output signal 1734 ₁ as a function of time, and waveform 2808 represents the input of channel 1702 ₂ . The differential signal is represented as a function of time, waveform 2810 represents output signal 1736 ₂ as a function of time, and waveform 2812 represents output signal 1734 ₂ as a function of time. For example, the input differential signals of channels 1702 ₁ and 1702 ₂ are each equal to 0 volts indicating that input signals 1730 ₁ and 1732 _{1 are} identical, and input signals 1730 ₂ and 1732 _{2 are} identical.

Section 4 (b) is the same as FIG channel input differential _17,021 and _17,022 and a signal amplification system were higher than 0V simplified timing diagram of the conventional 1700. Waveform 2820 represents the input differential signal of channel 1702 ₁ as a function of time, waveform 2822 represents output signal 1736 ₁ as a function of time, waveform 2824 represents output signal 1734 ₁ as a function of time, and waveform 2826 represents the input of channel 1702 ₂ . The differential signal is represented as a function of time, waveform 2828 represents output signal 1736 ₂ as a function of time, and waveform 2829 represents output signal 1734 ₂ as a function of time. For example, an input differential signal of channel 1702 ₁ above 0 volts indicates that input signal 1730 _{1 is} higher than input signal 1732 ₁ . In another example, the input differential signal of channel 1702 ₂ is above 0 volts indicating that input signal 1730 _{2 is} higher than input signal 1732 ₂ .

Section 4 (c) when the channel input differential FIG. ₁₇₀₂₁ and _17022, and the same signal amplification system were lower than 0 volts simplified timing diagram of the conventional 1700. Waveform 2830 represents the input differential signal of channel 1702 ₁ as a function of time, waveform 2832 represents output signal 1736 ₁ as a function of time, waveform 2834 represents output signal 1734 ₁ as a function of time, and waveform 2836 represents the input of channel 1702 ₂ . The differential signal is represented as a function of time, waveform 2838 represents output signal 1736 ₂ as a function of time, and waveform 2840 represents output signal 1734 ₂ as a function of time. For example, an input differential signal of channel 1702 ₁ below 0 volts indicates that input signal 1730 _{1 is} lower than input signal 1732 ₁ . In another example, the input differential signal of channel 1702 ₂ is below 0 volts indicating that input signal 1730 _{2 is} lower than input signal 1732 ₂ .

As shown in Figures 4(a), 4(b) and/or 4(c), in response to the same input differential signals for channels 1702 ₁ and 1702 ₂ , output signals 1734 ₁ and 1734 ₂ have The same phase is substantially the same, and the output signals 1736 ₁ and 1736 ₂ have substantially the same phase.

Amplification systems 100, 200 and 1700 often have certain drawbacks. It is therefore highly desirable to improve such an amplification system.

Certain embodiments of the invention relate to integrated circuits. More specifically, some embodiments of the present invention provide systems and methods for output adjustment. By way of example only, some embodiments of the invention have been applied to an amplification system. However, it should be recognized that the invention has a broader scope of applicability.

According to one embodiment, a system for amplifying a plurality of input signals to generate a plurality of output signals includes: a first channel, a second channel, and a third channel. The first channel is configured to receive one or more first input signals, process the one or more first input signals, and Information associated with a ramp signal and generating one or more first output signals based on at least information associated with the one or more first input signals and the first ramp signal. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and the second ramp signal, and based at least on the one or more second input signals The information associated with the second ramp signal generates one or more second output signals. The third channel is configured to receive one or more third input signals, process information associated with the one or more third input signals and the third ramp signal, and based at least on the one or more third input signals And the information associated with the third ramp signal generates one or more third output signals. The first ramp signal corresponds to the first phase. The second ramp signal corresponds to the second phase. The first phase is different from the second phase.

According to another embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The system for signaling includes: a first channel and a second channel. The first channel is configured to receive one or more first input signals, process information associated with the one or more first input signals and the first ramp signal, and based at least on the one or more first input signals The information associated with the first ramp signal generates one or more first output signals. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and the second ramp signal, and based at least on the one or more second input signals The information associated with the second ramp signal generates one or more second output signals. The first ramp signal corresponds to the first phase. The second ramp signal corresponds to the second phase. The difference between the first phase and the second phase is equal to 180 degrees.

According to another embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The system for signaling includes: a first channel and a second channel. The first channel includes a first loop filter, a first signal processing component, and a first output component, and is configured to receive one or more first input signals, process the one or more first input signals and ramp signals Associated information and generating one or more first output signals based on at least information associated with the one or more first input signals and ramp signals. The second channel includes a second loop filter, a second signal processing component, and a second output component, and is configured to receive one or more second input signals, process the one or more second input signals, and ramp signals Associated information and generating one or more based at least on information associated with the one or more second input signals and ramp signals Two output signals. The first loop filter is configured to process information associated with the one or more first input signals and to generate one or more first filtered ones based on at least information associated with the one or more first input signals signal. The first signal processing component is configured to process information associated with the one or more first filtered signals and to generate one or more first based on at least information associated with the one or more first filtered signals Processed signal. The first output component is configured to process information associated with the one or more first processed signals and to generate one or more first outputs based on at least information associated with the one or more first processed signals signal. The second loop filter is configured to process information associated with the one or more second input signals and to generate one or more second filtered ones based on at least information associated with the one or more second input signals signal. The second signal processing component is configured to process information associated with the one or more second filtered signals and to generate one or more second based on at least information associated with the one or more second filtered signals Processed signal. The second output component is configured to process information associated with the one or more second processed signals and to generate one or more second outputs based on at least information associated with the one or more second processed signals signal. One or more first processed signals are associated with the first phase. One or more second processed signals are associated with the second phase. The difference between the first phase and the second phase is equal to 180 degrees.

In one embodiment, one is for amplifying a plurality of input signals to generate a plurality of inputs The system for signaling includes: a first channel and a second channel. The first channel includes a first loop filter and one or more first comparators and is configured to receive one or more first input signals, the processing being associated with the one or more first input signals and ramp signals And generating one or more first output signals based on at least information associated with the one or more first input signals and the ramp signals. The second channel includes a second loop filter and one or more second comparators and is configured to receive one or more second input signals, the processing being associated with the one or more second input signals and the ramp signals And generating one or more second output signals based on at least information associated with the one or more second input signals and the ramp signals. The first loop filter is configured to process information associated with the one or more first input signals and to generate one or more first filtered ones based on at least information associated with the one or more first input signals signal. The one or more first comparators include one or more first ends and one or more second ends, and are configured to receive one or more first filtered signals at the first end and The second end receives the ramp signal and generates one or more first comparison signals based on at least information associated with the first filtered signal and the ramp signal, and outputs the one or more first comparison signals to generate one or more The first output signal. The second loop filter is configured to process information associated with the one or more second input signals and to generate one or more second filtered ones based on at least information associated with the one or more second input signals signal. The one or more second comparators include one or more third ends and one or more fourth ends, and are configured to receive one or more second filtered signals at the third end and receive at the fourth end And ramping the signal and generating one or more second comparison signals based on at least information associated with the second filtered signal and the ramp signal, and outputting the one or more second comparison signals to generate one or more second outputs signal. One or more second ends include one or more inverting terminals, and one or more fourth terminals include one or more non-inverting terminals, or one or more second terminals include one or more non-inverting terminals And one or more fourth ends include one or more inverting terminals.

In another embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The signalling system includes an oscillator component configured to generate a ramp signal associated with a ramp frequency, and a loop filter component configured to receive the one or more input signals and based at least on the one or more The information associated with the input signal generates one or more filtered signals; and a comparator component configured to receive the one or more filtered signals and ramp signals and based at least on the one or more filtered The information associated with the ramp signal generates one or more comparison signals. The oscillator element is further configured to: periodically change the ramp frequency such that one or more changes in the ramp frequency are generated in each jitter period corresponding to the jitter frequency, and outputting a ramp associated with the changed ramp frequency signal. The jitter frequency is greater than the upper limit of the predetermined audio frequency range.

In another embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The signalling system includes an oscillator component configured to generate a ramp signal associated with a ramp frequency, the ramp frequency corresponding to one or more ramp cycles, and a loop filter component configured to receive one or more Input signals and generating one or more filtered signals based on at least information associated with the one or more input signals; and a comparator component configured to receive the one or more filtered signals and ramp signals Generating one or more comparison signals based on at least information associated with the one or more filtered signals and ramp signals. Oscillator The piece is further configured to change the charging current or the discharging current at the end of the first ramp period such that the first duration of the first ramp period is different than the second duration of the second ramp period following the first ramp period. The first duration and the second duration correspond to different magnitudes of the ramp frequency.

According to one embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The method of signaling includes: receiving one or more first input signals; processing information associated with the one or more first input signals and the first ramp signal; and based at least on the one or more first input signals The information associated with the first ramp signal generates one or more first output signals. The method also includes receiving one or more second input signals, processing information associated with the one or more second input signals and the second ramp signal, and based at least on the one or more second input signals and The information associated with the second ramp signal generates one or more second output signals. Additionally, the method includes receiving one or more third input signals; processing information associated with the one or more third input signals and the third ramp signal; and based at least on the one or more third input signals And the information associated with the third ramp signal generates one or more third output signals. The first ramp signal corresponds to the first phase. The second ramp signal corresponds to the second phase. The first phase is different from the second phase.

According to another embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The method of signaling includes: receiving one or more first input signals; processing information associated with the one or more first input signals and the first ramp signal; and based at least on the one or more first input signals The information associated with the first ramp signal generates one or more first output signals. The method also includes receiving one or more second input signals, processing information associated with the one or more second input signals and the second ramp signal, and based at least on the one or more second input signals and The information associated with the second ramp signal generates one or more second output signals. The first ramp signal corresponds to the first phase. The second ramp signal corresponds to the second phase. The difference between the first phase and the second phase is equal to 180 degrees.

According to another embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The method of signaling includes: receiving, by the first channel including the first loop filter, the first signal processing component, and the first output component, one or more first input signals; processing the one or more first input signals And information associated with the ramp signal; and generating one or more first output signals based on at least information associated with the one or more first input signals and the ramp signals. The party The method also includes receiving, by the second channel including the second loop filter, the second signal processing component, and the second output component, one or more second input signals; processing the one or more second input signals and the ramp Information associated with the signal; and generating one or more second output signals based on at least information associated with the one or more second input signals and the ramp signals. Processing information associated with the one or more first input signals and the ramp signals includes: processing, by the first loop filter, information associated with the one or more first input signals; based at least on the one or more first Generating information associated with the input signal to generate one or more first filtered signals; processing, by the first signal processing component, information associated with the one or more first filtered signals; and based at least on one or more The information associated with the filtered signal generates one or more first processed signals. Generating the one or more first output signals based on at least information associated with the one or more first input signals and the ramp signals includes processing, by the first output element, information associated with the one or more first processed signals And generating one or more first output signals based on at least information associated with the one or more first processed signals. Processing information associated with the one or more second input signals and the ramp signal includes: processing, by the second loop filter, information associated with the one or more second input signals; based at least on one or more second Generating information associated with the input signal to generate one or more second filtered signals; processing, by the second signal processing component, information associated with the one or more second filtered signals; and based at least on one or more The information associated with the filtered signal generates one or more second processed signals. Generating the one or more second output signals based on at least information associated with the one or more second input signals and the ramp signals includes processing, by the second output element, information associated with the one or more second processed signals And generating one or more second output signals based on at least information associated with the one or more second processed signals. One or more first processed signals are associated with the first phase. One or more second processed signals are associated with the second phase, and the difference between the first phase and the second phase is equal to 180 degrees.

In one embodiment, one is for amplifying a plurality of input signals to generate a plurality of inputs The method of signaling includes receiving one or more first input signals by a first channel including a first loop filter and one or more first comparators; processing the one or more first input signals and ramps Information associated with the signal; and generating one or more first output signals based on at least information associated with the one or more first input signals and the ramp signals. The method also includes: Receiving one or more second input signals by a second channel comprising a second loop filter and one or more second comparators; processing information associated with the one or more second input signals and ramp signals; And generating one or more second output signals based on at least information associated with the one or more second input signals and the ramp signals. Processing information associated with the one or more first input signals and the ramp signals includes processing, at the first loop filter, information associated with the one or more first input signals, and based at least on one or more Information associated with an input signal generates one or more first filtered signals. Generating the one or more first output signals based on at least information associated with the one or more first input signals and the ramp signals includes receiving one or more of the one or more first ends of the one or more first comparators First filtered signals; receiving, by the one or more second ends of the one or more first comparators, a ramp signal; generating one or more based on at least information associated with the first filtered signal and the ramp signal a first comparison signal; outputting the one or more first comparison signals; and generating one or more first output signals based on at least information associated with the one or more first comparison signals. Processing information associated with the one or more second input signals and the ramp signals includes processing, by the second loop filter, information associated with the one or more second input signals, and based at least on one or more The information associated with the two input signals generates one or more second filtered signals. Generating the one or more second output signals based on at least information associated with the one or more second input signals and the ramp signals includes receiving one or more of the one or more third ends of the one or more second comparators Second filtered signals; receiving, by one or more fourth ends of the one or more second comparators, a ramp signal; generating one or more based on at least information associated with the second filtered signal and the ramp signal a second comparison signal; outputting the one or more second comparison signals; and generating one or more second output signals based on at least information associated with the one or more second comparison signals. One or more second ends include one or more inverting terminals, and one or more fourth terminals include one or more non-inverting terminals, or one or more second terminals include one or more non-inverting terminals And one or more fourth ends include one or more inverting terminals.

In another embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The method of signaling includes: generating a ramp signal associated with a ramp frequency; receiving one or more input signals; and processing information associated with the one or more input signals. The method also includes generating one or more filtered filters based on at least information associated with the one or more input signals a signal of the wave; receiving the one or more filtered signals and a ramp signal; processing information associated with the one or more filtered signals and the ramp signal; and based at least on the one or more filtered signals The information associated with the ramp signal generates one or more comparison signals. Generating a ramp signal associated with the ramp frequency includes periodically varying the ramp frequency such that one or more changes in the ramp frequency are generated in each jitter period corresponding to the jitter frequency, and the output is related to the changed ramp frequency Linked ramp signal. The jitter frequency is greater than the upper limit of the predetermined audio frequency range.

In another embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The method of signaling includes: generating a ramp signal associated with a ramp frequency, the ramp frequency corresponding to one or more ramp cycles; receiving one or more input signals; and processing information associated with the one or more input signals . The method also includes generating one or more filtered signals based on at least information associated with the one or more input signals; receiving the one or more filtered signals and ramp signals; and based at least on the one or The plurality of filtered signals and the information associated with the ramp signals generate one or more comparison signals. Generating a ramp signal associated with the ramp frequency includes changing a charge current or a discharge current at the end of the first ramp period such that a first duration of the first ramp period is second with a second ramp period following the first ramp period The duration is different. The first duration and the second duration correspond to different magnitudes of the ramp frequency.

According to one embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The signal output system includes: a first channel configured to receive the first input signal and the second input signal and to generate the first output signal and the second output signal based at least in part on the first input signal and the second input signal; A second channel configured to receive the third input signal and the fourth input signal and to generate a third output signal and a fourth output signal based at least in part on the third input signal and the fourth input signal. The first differential signal is equal to the first input signal minus the second input signal. The second differential signal is equal to the third input signal minus the fourth input signal. The first output signal corresponds to the first phase. The second output signal corresponds to the second phase. The third output signal corresponds to the third phase. The fourth output signal corresponds to the fourth phase. The first phase difference is equal to the first phase minus the third phase. The second phase difference is equal to the second phase minus the fourth phase. The first differential signal is the same as the second differential signal. The first phase difference is not equal to zero. The second phase difference is not equal to zero. The first phase difference is the same as the second phase difference.

According to another embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The signalling system includes: a first channel configured to receive one or more first input signals, and generate one or more first output signals based at least in part on the one or more first input signals; and a second A channel configured to receive one or more second input signals and to generate one or more second output signals based at least in part on the one or more second input signals. The first differential signal associated with the one or more first input signals is equal to the second differential signal associated with the one or more second input signals. The one or more first output signals correspond to one or more first phases. The one or more second output signals correspond to one or more second phases. Each of the one or more differences between the one or more first phases and the corresponding one or more second phases is equal to 180 degrees.

According to another embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The signal output system includes: a first channel configured to receive the first input signal and the second input signal and to generate the first output signal and the second output signal based at least in part on the first input signal and the second input signal; A second channel configured to receive the third input signal and the fourth input signal and to generate a third output signal and a fourth output signal based at least in part on the third input signal and the fourth input signal. The first differential signal is equal to the first input signal minus the second input signal. The second differential signal is equal to the third input signal minus the fourth input signal. When the first output signal and the second output signal both correspond to the first logic level, and the third output signal and the fourth output signal both correspond to the second logic level, the second logic level is different from the first logic level.

In one embodiment, one is for amplifying a plurality of input signals to generate a plurality of inputs The method for outputting a signal includes: receiving a first input signal and a second input signal; generating a first output signal and a second output signal based at least in part on the first input signal and the second input signal; receiving the third input signal and the fourth input signal And generating a third output signal and a fourth output signal based at least in part on the third input signal and the fourth input signal. The first differential signal is equal to the first input signal minus the second input signal. The second differential signal is equal to the third input signal minus the fourth input signal. The first output signal corresponds to the first phase. The second output signal corresponds to the second phase. The third output signal corresponds to the third phase. The fourth output signal corresponds to the fourth phase. The first phase difference is equal to the first phase minus the third phase. The second phase difference is equal to the second phase minus the fourth phase. The first differential signal is the same as the second differential signal. The first phase difference is not equal to zero. The second phase difference is not equal to zero. the first The phase difference is the same as the second phase difference.

In another embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The method of signaling includes: receiving one or more first input signals; generating one or more first output signals based at least in part on the one or more first input signals; receiving one or more second input signals; and at least Generating one or more second output signals based in part on the one or more second input signals. The first differential signal associated with the one or more first input signals is equal to the second differential signal associated with the one or more second input signals. The one or more first output signals correspond to one or more first phases. The one or more second output signals correspond to one or more second phases. Each of the one or more differences between the one or more first phases and the corresponding one or more second phases is equal to 180 degrees.

In another embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The method for outputting a signal includes: receiving a first input signal and a second input signal; generating a first output signal and a second output signal based at least in part on the first input signal and the second input signal; receiving the third input signal and the fourth input signal Generating a third output signal and a fourth output signal based at least in part on the third input signal and the fourth input signal. The first differential signal is equal to the first input signal minus the second input signal. The second differential signal is equal to the third input signal minus the fourth input signal. When the first output signal and the second output signal both correspond to the first logic level, and the third output signal and the fourth output signal both correspond to the second logic level, the second logic level is different from the first logic level.

One or more benefits can be achieved based on the embodiments. These and other additional objects, features and advantages of the present invention will be <RTIgt;

100,200,300,500,600,800,1600,1700,1800‧‧‧Amplification system

102,802‧‧‧ modulator

104,804‧‧‧Output

106,224 ₁ ,324 ₁ ,542,544,642,644,806,1642,1644,1724 ₁ ,1824 ₁ ,1824 ₂ ‧‧‧Low-pass filtering

108,808‧‧‧Oscillator

110,206 ₁ ,208 ₁ ,306 ₁ ,308 ₁ ,506,508,510,512,606,608,610,612,810,914,918,1514,1518,1606,1608,1610,1612,1706 ₁ ,1708 ₁ ,1806 ₁ ,1806 ₂ ,1808 ₁ ,1808 ₂ ‧‧‧ Comparator

_{112,204 1, 304 1, 502,504,602,604,812,1602,1604,1704 1} , 1704 2, 1804 1, 1804 2 ‧‧‧ loop filter

116,226 ₁ ,...,226 _n ,...,226 _N ,546,548,646,648,816,1646,1648,1722 ₁ ,1722 ₂ ,1826 ₁ ,1826 ₂ ‧‧‧ Output load

118,818‧‧‧ Input audio signal

120,234 ₁ ,...,234 _n ,...,234 _N ,236 ₁ ,...,236 _n ,...,236 _N ,334 ₁ ,336 ₁ ,572,574,576,578,672,674,676,678,820,1672,1674,1676,1678,1734 ₁ ,1734 ₂ ,1736 ₁ , 1736 ₂ , 1834 ₁ , 1834 ₂ , 1836 ₁ , 1836 ₂ ‧‧‧ Output signal

122,584,586,684,686,822,1684,1686‧‧‧ Filtered signals

124,228,328 ₁ ,...,328 _N ,568,570,668,824,1668,1728,1828‧‧‧Ramp signal

126, 826 ‧ ‧ clock signal

128,592,594,828‧‧‧Comparative signals

130,580,582,680,682,830,1680,1682‧‧‧ audio signals

202 ₁ ,...,202 _n ,...,202 _N ,302 ₁ ,...,302 _n ,...,302 _N ,1702 ₁ ,1702 ₂ ,1802 ₁ ,1802 ₂ ‧‧‧ Channel

210 ₁ , 310 ₁ , 514, 516, 614, 616, 1614, 1616, 1710 ₁ , 1810 ₁ , 1810 ₂ ‧ ‧ Logic controller

212 ₁ , 214 ₁ , 312 ₁ , 314 ₁ , 518 , 520 , 522 , 524 , 618 , 620 , 622 , 624 , 1618 , 1620 , 1622 , 1624 , 1712 ₁ , 1714 ₁ , 1812 ₁ , 1812 ₂ , 1814 ₁ , 1814 ₂ ‧ ‧ drive components

216 ₁ , 218 ₁ , 220 ₁ , 222 ₁ , 316 ₁ , 318 ₁ , 320 ₁ , 322 ₁ , 526 , 528 , 530 , 532 , 534 , 536 , 538 , 540 , 626 , 628 , 630 , 632 , 634 , 636 , 638 , 640 , 1626 , 1628 , 1630 , 1632 , 1634 , 1636 , 1638 , 1640 , 1716 ₁ , 1718 ₁ , 1720 ₁ , 1722 ₁ , 1816 ₁ , 1816 ₂ , 1818 ₁ , 1818 ₂ , 1820 ₁ , 1820 ₂ , 1822 ₁ , 1822 ₂ ‧ ‧ ‧ crystal

230 ₁ , 232 ₁ , 332 ₁ , 330 ₁ , 560 , 562 , 564 , 566 , 660 , 662 , 664 , 666 , 1660 , 1662 , 1664 , 1666 , 1730 ₁ , 1730 ₂ , 1732 ₁ , 1732 ₂ , 1830 ₁ , 1830 ₂ , 1832 ₁ , 1832 ₂ ‧ ‧ input signal

326 ₁ , 326 _N ‧‧‧Speaker load

402 ₁ , 402 ₂ , 402 ₃ , 402 _N , 702, 1006, 1008, 1102, 1202, 1902, 1904, 1906, 1908, 1910, 1912, 2002, 2004, 2006, 2008, 2010, 2012, 2102, 2104, 2106,2108,2110,2112,2802,2804,2806,2808,2810,2812,2820,2822,2824,2826,2828,2829,2830,2832,2834,2836,2838,2840‧‧ waveform

550,552,554,556,650,652,924,1524,1650,1652,1654,1656‧‧ ‧buffer

588,590,688,690,692,694,1688,1690,1692,1694,1807 ₁ ,1807 ₂ ,1809 ₁ ,1809 ₂ ‧‧‧ Comparator output signal

596,597,598,599,696,697,698,699,930,1322,1324,1326,1328,1412,1414,1530,1696,1697,1698,1699‧‧ signals

654, 656‧‧ ‧ reverse gate

902,1502‧‧‧jitter sequencer

904, 906, 1504, 1506‧‧‧ current source

908, 910, 1508, 1510‧ ‧ switch

912, 1512‧‧‧ Transconductance amplifier

916,1516‧‧‧ capacitor

920,922,1520,1522‧‧‧Anti-gate

926, 1526‧‧‧Charging signal

928,1528‧‧‧discharge signal

932,1532‧‧‧Charging current

934,1534‧‧‧Discharge current

996,998‧‧‧ reference signal

1018, 1020, 1022, 1024, 1026‧‧‧

1028, 1030‧‧‧ rising edge

1302, 1410‧‧‧ Current controlled oscillating components

1304‧‧‧Linear Feedback Shift Register (LFSR)

1308, 1314, 1408‧‧‧ Current Digital Analog Converter (DAC)

1306, 1312‧‧‧Encoder components

1310, 1404‧‧‧ counter components

1316, 1318, 1320, 1402, 1416‧‧‧ Current signal

1406‧‧‧Encoder

1819 ₁ , 1819 ₂ ‧‧‧ Phase control components

2092 ₁ ,2092 ₂ ,2094 ₁ ,2094 ₂ ,2096 ₁ ,2096 ₂ ,2098 ₁ ,2098 ₂ ,2192 ₁ ,2192 ₂ ,2194 ₂ ,2194 ₁ ,2194 ₂ ,2196 ₁ ,2196 ₂ ,2198 ₁ ,2198 ₂ ‧‧‧current

Fig. 1 is a simplified conventional diagram showing an amplification system using a class D amplifier having one channel.

Figure 2 is a simplified conventional diagram of an amplification system with multiple channels.

Figure 3 is a simplified conventional diagram of an amplification system with two channels.

Figure 4(a) is a simplified conventional timing diagram of the amplification system shown in Figure 3 when the input differential signals for both channels are equal to 0 volts.

Figure 4(b) is a simplified conventional timing diagram of the amplification system shown in Figure 3 when the input differential signals of the two channels are the same and both are above 0 volts.

Figure 4(c) is a simplified conventional timing diagram of the amplification system shown in Figure 3 when the input differential signals of the two channels are the same and both are below 0 volts.

Figure 5 is a simplified diagram of an amplification system having multiple channels in accordance with an embodiment of the present invention.

Fig. 6 is a simplified timing chart of the amplification system shown in Fig. 5 according to an embodiment of the present invention.

In accordance with an embodiment of the invention, a simplified diagram of an amplification system having two channels is shown.

Figure 7(b) is a simplified diagram showing an amplification system with two channels, in accordance with another embodiment of the present invention.

Figure 7(c) is a simplified diagram showing an amplification system having two channels, in accordance with yet another embodiment of the present invention.

Figure 8 is a simplified diagram of an amplification system in accordance with an embodiment of the present invention.

Figure 9 is a simplified timing diagram of an oscillator with period jitter as part of the amplification system shown in Figure 8 in accordance with an embodiment of the present invention.

Figure 10(a) is a simplified diagram showing certain elements of an oscillator with periodic jitter as part of the amplification system shown in Figure 8, in accordance with one embodiment of the present invention.

Figure 10(b) is a simplified timing diagram of the oscillator as shown in Figure 10(a) as part of an amplification system, in accordance with one embodiment of the present invention.

Figure 10(c) is a simplified diagram showing certain elements of an oscillator with periodic jitter as part of the amplification system shown in Figure 8, in accordance with another embodiment of the present invention.

Figure 11 is a simplified timing diagram of an amplification system as shown in Figure 8 including an oscillator having periodic jitter and receiving one or more input signals, in accordance with one embodiment of the present invention.

Figure 12 is a simplified spectrogram showing the combination of periodic jitter and pseudo-random jitter of an oscillator as part of the amplification system shown in Figure 8, in accordance with another embodiment of the present invention.

Figure 13 is a simplified spectrogram of an amplification system as shown in Figure 8 including an oscillator having a combination of periodic jitter and pseudo-random jitter, when the input signal is zero, in accordance with one embodiment of the present invention.

Figure 14(a) is a simplified diagram showing certain elements of an oscillator having a combination of periodic jitter and pseudo-random jitter as part of the amplification system of Figure 8 in accordance with one embodiment of the present invention. .

Figure 14(b) is a simplified illustration of certain elements of an oscillator having a combination of periodic jitter and pseudo-random jitter, as part of the amplification system illustrated in Figure 8, in accordance with another embodiment of the present invention. Figure.

Figure 15 is a simplified diagram of an amplification system having two channels in accordance with one embodiment of the present invention.

Figure 16 is a simplified timing diagram of the amplification system as shown in Figure 15 when the input differential signals of both channels are equal to 0 volts, in accordance with one embodiment of the present invention.

Figure 17(a) is a simplified diagram showing a portion of the channel when the input differential signal of one channel is equal to 0 volts, and Figure 17(b) is a diagram in accordance with the present invention, in accordance with some embodiments of the present invention. The embodiment shows a simplified diagram of a portion of the channel when the input differential signal of the other channel is equal to 0 volts.

Figure 18 is a simplified timing diagram of the amplification system as shown in Figure 15 when the input differential signals of the two channels are the same and both are above 0 volts, in accordance with one embodiment of the present invention.

19(a)-22(b) are diagrams showing the 15th (b) when the input differential signals of the two channels are the same and both are higher than 0 volts, as in the 15th, according to some embodiments of the present invention. A simplified diagram of a portion of the two channels shown.

Figure 23 is a simplified timing diagram of the amplification system as shown in Figure 15 when the input differential signals of the two channels are the same and both are below 0 volts, in accordance with one embodiment of the present invention.

Figure 24(a) - Figure 27(b) is a diagram showing the difference between the two channels when the input differential signals are the same and both are below 0 volts, as in the 15th, according to some embodiments of the present invention. A simplified diagram of a portion of the two channels shown.

Certain embodiments of the invention relate to integrated circuits. More specifically, some embodiments of the present invention provide systems and methods for output adjustment. By way of example only, some embodiments of the invention have been applied to an amplification system. However, it should be recognized that the invention has a broader scope of applicability.

Referring to FIG 2, since the channel for receiving a plurality of common ramp signal, the output signal _{(e.g., 234 1, ..., 234 n} , ..., 234 N , and / or _{236 1, ..., 236 n,} ..., 236 N) may be Have the same frequency and have the same phase. That is, all power levels can be turned "on" and "off" at approximately the same time, which often causes large fluctuations in the power applied to the amplification system 200.

Figure 5 is a simplified diagram of an amplification system having multiple channels in accordance with an embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. The amplification system 300 includes a plurality of channels 302 ₁ , . . . , 302 _n , . . . , 302 _N , where N 2 and 1 n N.

As an example, the first channel 302 ₁ includes a loop filter 304 ₁ , comparators 306 ₁ and 308 ₁ , a logic controller 310 ₁ , drive elements 312 ₁ and 314 ₁ , transistors 316 ₁ , 318 ₁ , 320 ₁ and 322 ₁ , and a low pass filter 324 ₁ . According to some embodiments, the other channels have elements similar to the first channel. For example, transistors 316 ₁ , 318 ₁ , 320 ₁ and 322 ₁ are N-channel transistors. As an example, logic controller 310 ₁ includes one or more buffers. In another example, low pass filter 324 ₁ includes one or more inductors and/or one or more capacitors. In another example, low pass filter 324 ₁ includes one or more bead cores and/or one or more capacitors. In one embodiment, loop filter 304 ₁ amplifies the error signal between the input differential signal and the feedback differential signal associated with the output differential signal. The input differential signal represents the difference between the input signals 332 ₁ and 330 ₁ and the output differential signal represents the difference between the output signals 334 ₁ and 336 ₁ . For example, loop filter 304 ₁ includes a low pass filter that has a very high gain in the low frequency range (eg, a high gain greater than 1000) and a very low gain in the high frequency range (eg, a low gain that is much less than one). . In another example, if the signal includes a low frequency component and a high frequency component, the loop filter 304 ₁ amplifies the low frequency component with a high gain and amplifies the high frequency with a low gain (eg, a low gain much smaller than 1). Component. In another example, if the high frequency component is close to the switching frequency of the amplification system 300, the loop filter 304 ₁ attenuates the high frequency component. In one embodiment, loop filter 304 ₁ includes one or more analog integrator stages.

According to some embodiments, the ramp signals (eg, 328 ₁ , . . . , 328 _N ) received by the different channels have the same frequency but different phases. In one embodiment, the phase shifts between ramp signals received by different channels are equal. As an example, the first channel 302 ₁ receives the ramp signal 328 ₁ (VRAMP1) for processing the input signals 330 ₁ and 332 ₁ . In another embodiment, the second channel 302 ₂ (not shown in FIG. 5) receives the ramp signal 328 ₂ and the phase shift between the ramp signal 328 ₂ and the ramp signal 328 ₁ is The phase shift between the ramp signal 328 ₃ received by the third channel 302 ₃ (not shown in FIG. 5) and the ramp signal 328 ₁ is And the phase shift between the ramp signal 328 _N (VRAMPN) received by the last channel 302 _N and the ramp signal 328 ₁ is . In another embodiment, the phase shift between the ramp signals received by the different channels is different. As an example, the phase shift between the first channel 302 ₁ and the second channel 302 _{2 is} different from the phase shift between the second channel 302 ₂ and the third channel 302 ₃ .

Figure 6 is a simplified timing diagram of an amplification system 300 in accordance with an embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. Waveform 402 ₁ represents ramp signal 328 ₁ as a function of time, waveform 402 ₂ represents ramp signal 328 ₂ as a function of time, waveform 402 ₃ represents ramp signal 328 ₃ as a function of time, and waveform 402 _N will ramp signal 328 _{N is} expressed as a function of time. As shown in FIG. 6, according to some embodiments, the phase shift between ramp signal 328 ₁ and ramp signal 328 ₂ is φ ₁ , the phase shift between ramp signal 328 ₂ and ramp signal 328 ₃ is φ ' , and The phase shift between ramp signal 328 ₁ and ramp signal 328 _N is φ _N . For example, the phase shift φ ₁ is equal to or not equal to the phase shift φ ' .

Figure 7(a) is a simplified diagram showing an amplification system with two channels, in accordance with an embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. Amplification system 500 includes loop filters 502 and 504, comparators 506, 508, 510 and 512, logic controllers 514 and 516, drive elements 518, 520, 522 and 524, transistors 526, 528, 530, 532, 534, 536, 538 and 540, and low pass filters 542 and 544. For example, amplification system 500 is an amplification system 300 with N equal to two.

In one embodiment, loop filter 502, comparators 506 and 508, logic controller 514, drive elements 518 and 520, transistors 526, 528, 530 and 532, and low pass filter 542 are included in the first channel. In another embodiment, loop filter 504, comparator 510 And 512, logic controller 516, drive elements 522 and 524, transistors 534, 536, 538 and 540, and low pass filter 544 are included in the second channel. Logic controller 514 includes two buffers 550 and 552, and logic controller 516 includes two buffers 554 and 556. In some embodiments, transistors 526, 528, 530, 532, 534, 536, 538, and 540 are N-channel transistors, such as N-channel metal oxide semiconductor field effect transistors (MOSFETs). In some embodiments, transistors 526, 530, 534, and 538 are P-channel transistors (eg, P-channel MOSFETs), while transistors 528, 532, 536, and 540 are N-channel transistors (eg, N-channel MOSFETs). As an example, each of low pass filters 542 and 544 includes one or more inductors and/or one or more capacitors. In another example, each of low pass filters 542 and 544 includes one or more bead cores and/or one or more capacitors.

In another example, loop filter 502, comparators 506 and 508, logic controller 514, drive elements 518 and 520, transistors 526, 528, 530 and 532, and low pass filter 542 and loop filter 304 ₁ , respectively Comparators 306 ₁ and 308 ₁ , logic controller 310 ₁ , drive elements 312 ₁ and 314 ₁ , transistors 316 ₁ , 318 ₁ , 320 ₁ and 322 ₁ , and low pass filter 324 _{1 are} identical. In another example, loop filter 504, comparators 510 and 512, logic controller 516, drive elements 522 and 524, transistors 534, 536, 538 and 540, and low pass filter 544, respectively, and loop filter 304 ₁ , Comparators 306 ₁ and 308 ₁ , logic controller 310 ₁ , drive elements 312 ₁ and 314 ₁ , transistors 316 ₁ , 318 ₁ , 320 ₁ and 322 ₁ , and low pass filter 324 _{1 are} identical.

According to one embodiment, the first channel receives input signals 560 and 562 and ramp signal 568 (RAMP1) and generates output signals 572 and 574 to provide one or more audio signals 580 to an output load 546 (eg, a speaker). In particular, for example, loop filter 502 receives input signals 560 and 562 and generates filtered signals 584 and 586, which are received by comparators 506 and 508, respectively. As an example, comparators 506 and 508 also receive ramp signal 568 and generate comparator output signals 588 and 590, respectively. Logic controller 514 outputs signals 596 and 598 to drive elements 518 and 520, respectively. For example, loop filter 502 receives output signals 572 and 574 as feedback. In one example, signal 596 is at a logic high level if comparator output signal 588 is at a logic high level, and signal 596 is at a logic low level if comparator output signal 588 is at a logic low level. In another example, if comparator output signal 590 is at a logic high level, signal 598 is at a logic high level, and if comparator output signal 590 is at At logic low, signal 598 is at a logic low level.

According to another embodiment, the second channel receives input signals 564 and 566 and ramp signal 570 (RAMP2) and generates output signals 576 and 578 to provide one or more audio signals 582 to an output load 548 (eg, a speaker). In particular, for example, loop filter 504 receives input signals 564 and 566 and generates filtered comparator output signals 588 and 590, which are received by comparators 510 and 512, respectively. As an example, comparators 510 and 512 also receive ramp signal 570 and generate comparison signals 592 and 594, respectively. Logic controller 516 outputs signals 597 and 599 to drive elements 522 and 524, respectively. For example, loop filter 504 receives output signals 576 and 578 as feedback. In one example, if comparison signal 592 is at a logic high level, signal 597 is at a logic high level, and if comparison signal 592 is at a logic low level, signal 597 is at a logic low level. In another example, signal 599 is at a logic high level if comparison signal 594 is at a logic high level, and signal 599 is at a logic low level if comparison signal 594 is at a logic low level.

As an example, ramp signals 568 and 570 have the same frequency, and the phase shift between ramp signal 568 and ramp signal 570 is π (eg, 180 degrees). That is, the ramp signal 568 is inverted from the ramp signal 570.

In one embodiment, loop filter 502 amplifies the error signal between the input differential signal and the feedback differential signal associated with the output differential signal. The input differential signal represents the difference between input signals 560 and 562, while the output differential signal represents the difference between output signals 572 and 574. For example, loop filter 502 is a low pass filter and it has a very high gain in the low frequency range (eg, a high gain greater than 1000) and a very low gain in the high frequency range (eg, a low gain much less than one) ). In another example, if the signal includes a low frequency component and a high frequency component, the loop filter 502 amplifies the low frequency component with a high gain and amplifies the high frequency component with a low gain (eg, a low gain much smaller than 1). . In another example, if the high frequency component is close to the switching frequency of the amplification system 500, the loop filter 502 attenuates the high frequency component. In one embodiment, loop filter 502 includes one or more analog integrator stages. In some embodiments, loop filter 504 is the same as loop filter 502.

Figure 7(b) is a simplified diagram showing an amplification system with two channels, in accordance with another embodiment of the present invention. This figure is only an example and should not be excessively restricted from patent application. The scope of the scope. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. Amplification system 600 includes loop filters 602 and 604, comparators 606, 608, 610 and 612, logic controllers 614 and 616, drive elements 618, 620, 622 and 624, transistors 626, 628, 630, 632, 634, 636, 638 and 640, and low pass filters 642 and 644.

In one embodiment, loop filter 602, comparators 606 and 608, logic controller 614, drive elements 618 and 620, transistors 626, 628, 630 and 632, and low pass filter 642 are included in the first channel. In another embodiment, loop filter 604, comparators 610 and 612, logic controller 616, drive elements 622 and 624, transistors 634, 636, 638 and 640, and low pass filter 644 are included in the second channel. Logic controller 614 includes two buffers 650 and 652, and logic controller 616 includes two reverse gates 654 and 656. In some embodiments, transistors 626, 628, 630, 632, 634, 636, 638, and 640 are N-channel transistors, such as N-channel MOSFETs. In some embodiments, transistors 626, 630, 634, and 638 are P-channel transistors (eg, P-channel MOSFETs), while transistors 628, 632, 636, and 640 are N-channel transistors (eg, N-channel MOSFETs). As an example, each of low pass filters 642 and 644 includes one or more inductors and/or one or more capacitors. In another example, each of low pass filters 642 and 644 includes one or more bead cores and/or one or more capacitors. In another example, loop filter 602, comparators 606 and 608, logic controller 614, drive elements 618 and 620, transistors 626, 628, 630, and 632, and low pass filter 642 and loop filtering, respectively The comparators 304 ₁ , the comparators 306 ₁ and 308 ₁ , the logic controller 310 ₁ , the drive elements 312 ₁ and 314 ₁ , the transistors 316 ₁ , 318 ₁ , 320 ₁ and 322 ₁ , and the low-pass filter 324 _{1 are} identical. In another example, loop filter 604, comparators 610 and 612 are identical to loop filter 304 ₁ , comparators 306 ₁ and 308 _{1 , respectively} .

According to one embodiment, the first channel receives input signals 660 and 662 and ramp signal 668 (RAMP) and generates output signals 672 and 674 to provide one or more audio signals 680 to an output load 646 (eg, a speaker). In particular, for example, loop filter 602 receives input signals 660 and 662 and output signals 672 and 674 as feedback, and generates filtered signals 684 and 686, which are compared by comparators 606 and 608, respectively. receive. As an example, comparators 606 and 608 also receive ramp signal 668 and generate comparator output signals 688 and 690, respectively. Logic controller 614 outputs signals 696 and 698 to drive elements 618 and 620, respectively. For example, if comparator output signal 688 is at a logic high level, then signal 696 is at a logic high level, and If comparator output signal 688 is at a logic low level, then signal 696 is at a logic low level. In another example, signal 698 is at a logic high level if comparator output signal 690 is at a logic high level, and signal 698 is at a logic low level if comparator output signal 690 is at a logic low level. In some embodiments, logic controller 614 is removed and comparator output signals 688 and 690 are identical to signals 696 and 698, respectively. For example, each of comparators 606, 608, 610, and 612 receives ramp signal 668 at a non-inverting terminal (eg, the "+" terminal). In another example, each of the comparators 606, 608, 610, and 612 receives the ramp signal 668 at the inverting terminal (eg, the "-" terminal).

According to another embodiment, the second channel receives input signals 664 and 666 and ramp signal 668 and generates output signals 676 and 678 to provide one or more audio signals 682 to an output load 648 (eg, a speaker). In particular, for example, loop filter 604 receives input signals 664 and 666 and output signals 676 and 678 as feedback, and generates filtered comparator output signals 688 and 690, filtered comparator output signals 688 and 690, respectively. Received by comparators 610 and 612. As an example, comparators 610 and 612 also receive ramp signal 668 and generate comparator output signals 692 and 694, respectively. Logic controller 616 outputs signals 697 and 699 to drive elements 622 and 624, respectively. For example, if comparator output signal 692 is at a logic high level, then signal 697 is at a logic low level, and if comparator output signal 692 is at a logic low level, then signal 697 is at a logic high level. In another example, signal 699 is at a logic low level if comparator output signal 694 is at a logic high level, and signal 699 is at a logic high level if comparator output signal 694 is at a logic low level. In another example, the comparator 606 receives the filtered signal 684 at the inverting terminal (eg, the "-" terminal); the comparator 608 receives the filtered signal 686 at the inverting terminal (eg, the "-" terminal); Comparator 610 receives comparator output signal 688 at the inverting terminal (eg, the "-" terminal); and comparator 612 receives comparator output signal 690 at the inverting terminal (eg, the "-" terminal).

In one embodiment, loop filter 602 amplifies the error signal between the input differential signal and the feedback differential signal associated with the output differential signal. The input differential signal represents the difference between input signals 660 and 662, while the output differential signal represents the difference between output signals 672 and 674. For example, loop filter 602 is a low pass filter and has a very high gain in the low frequency range (eg, a high gain greater than 1000) and a very low gain in the high frequency range (eg, a low gain much less than one) ). In another example, if the signal includes a low frequency component and a high frequency component, then Loop filter 602 amplifies low frequency components with high gain and amplifies high frequency components with low gain (eg, low gain much less than one). In another example, if the high frequency component is close to the switching frequency of the amplification system 600, the loop filter 602 attenuates the high frequency component. In one embodiment, loop filter 602 includes one or more analog integrator stages. In some embodiments, loop filter 604 is the same as loop filter 602.

Figure 7(c) is a simplified diagram showing an amplification system having two channels, in accordance with yet another embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. Amplification system 1600 includes loop filters 1602 and 1604, comparators 1606, 1608, 1610 and 1612, logic controllers 1614 and 1616, drive elements 1618, 1620, 1622 and 1624, transistors 1626, 1628, 1630, 1632, 1634, 1636, 1638 and 1640, and low pass filters 1642 and 1644.

In one embodiment, loop filter 1602, comparators 1606 and 1608, logic controller 1614, drive elements 1618 and 1620, transistors 1626, 1628, 1630 and 1632, and low pass filter 1642 are included in the first In the channel. In another embodiment, loop filter 1604, comparators 1610 and 1612, logic controller 1616, drive elements 1622 and 1624, transistors 1634, 1636, 1638 and 1640, and low pass filter 1644 are included In the second channel. Logic controller 1614 includes two buffers 1650 and 1652, and logic controller 1616 includes two buffers 1654 and 1656. In some embodiments, transistors 1626, 1628, 1630, 1632, 1634, 1636, 1638, and 1640 are N-channel transistors, such as N-channel MOSFETs. In some embodiments, transistors 1626, 1630, 1634, and 1638 are P-channel transistors (eg, P-channel MOSFETs), while transistors 1628, 1632, 1636, and 1640 are N-channel transistors (eg, N-channel MOSFET). As an example, each of low pass filters 1642 and 1644 includes one or more inductors and/or one or more capacitors. In another example, each of low pass filters 1642 and 1644 includes one or more bead cores and/or one or more capacitors. In another example, loop filter 1602, comparators 1606 and 1608, logic controller 1614, drive elements 1618 and 1620, transistors 1626, 1628, 1630 and 1632, and low pass filter 1642, respectively, and loop filtering The comparators 304 ₁ , the comparators 306 ₁ and 308 ₁ , the logic controller 310 ₁ , the drive elements 312 ₁ and 314 ₁ , the transistors 316 ₁ , 318 ₁ , 320 ₁ and 322 ₁ , and the low-pass filter 324 _{1 are} identical. In another example, loop filter 1604, comparators 1610 and 1612 are identical to loop filter 304 ₁ , comparators 306 ₁ and 308 _{1 , respectively} .

According to one embodiment, the first channel receives input signals 1660 and 1662 and ramp signal 1668 (RAMP) and generates output signals 1672 and 1674 to provide one or more audio signals 1680 to output load 1646 (eg, a speaker). In particular, for example, loop filter 1602 receives input signals 1660 and 1662 and output signals 1672 and 1674 as feedback, and generates filtered signals 1684 and 1686, which are compared by comparators 1606 and 1608, respectively. receive. As an example, comparators 1606 and 1608 also receive ramp signal 1668 and generate comparator output signals 1688 and 1690, respectively. Logic controller 1614 outputs signals 1696 and 1698 to drive elements 1618 and 1620, respectively. For example, if comparator output signal 1688 is at a logic high level, signal 1696 is at a logic high level, and if comparator output signal 1688 is at a logic low level, then signal 1696 is at a logic low level. In another example, signal 1698 is at a logic high level if comparator output signal 1690 is at a logic high level, and signal 1698 is at a logic low level if comparator output signal 1690 is at a logic low level. In some embodiments, logic controller 1614 is removed and comparator output signals 1688 and 1690 are identical to signals 1696 and 1698, respectively. In some embodiments, logic controller 1616 is removed and comparator output signals 1692 and 1694 are identical to signals 1697 and 1699, respectively. For example, each of comparators 1610 and 1612 receives a ramp signal 1668 at a non-inverting terminal (eg, the "+" terminal), and each of comparators 1606 and 1608 receives at an inverting terminal (eg, the "-" terminal) Ramp signal 1668.

According to another embodiment, the second channel receives input signals 1664 and 1666 and ramp signal 1668 and generates output signals 1676 and 1678 to provide one or more audio signals 1682 to an output load 1648 (eg, a speaker). In particular, for example, loop filter 1604 receives input signals 1664 and 1666 and output signals 1676 and 1678 as feedback, and generates filtered comparator output signals 1688 and 1690, filtered comparator output signals 1688 and 1690, respectively. Received by comparators 1610 and 1612. As an example, comparators 1610 and 1612 also receive ramp signal 1668 and generate comparator output signals 1692 and 1694, respectively. In another example, logic controller 1616 outputs signals 1697 and 1699 to drive elements 1622 and 1624, respectively. In another example, comparator 1606 receives signal 1684 at a non-inverting terminal (eg, a "+" terminal); comparator 1608 receives a filtered signal 1686 at a non-inverting terminal (eg, a "+" terminal); The comparator 1610 receives the comparator output signal 1688 at the inverting terminal (eg, the "-" terminal); and the comparator 1612 receives the comparator output signal 1690 at the inverting terminal (eg, the "-" terminal).

In one embodiment, loop filter 1602 amplifies the error signal between the input differential signal and the feedback differential signal associated with the output differential signal. The input differential signal represents the difference between input signals 1660 and 1662, while the output differential signal represents the difference between output signals 1672 and 1674. For example, loop filter 1602 is a low pass filter and it has a very high gain in the low frequency range (eg, a high gain greater than 1000) and a very low gain in the high frequency range (eg, a low gain much less than one) ). In another example, if the signal includes a low frequency component and a high frequency component, the loop filter 1602 amplifies the low frequency component with a high gain and amplifies the high frequency component with a low gain (eg, a low gain much smaller than 1). . In another example, if the high frequency component is close to the switching frequency of the amplification system 1600, the loop filter 1602 attenuates the high frequency component. In one embodiment, loop filter 1602 includes one or more analog integrator stages. In some embodiments, loop filter 1604 is the same as loop filter 1602.

As described above and further emphasized herein, Figures 5, 7(a), 7(b), and 7(c) are merely examples, and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. For example, the phase shift between ramp signals 568 and 570 is not equal to π. In another example, each of the channels 302 ₁ , . . . , 302 _N includes a respective oscillator for generating ramp signals 328 ₁ , . . . , 328 _N , respectively. In another example, channels 302 ₁ , . . . , 302 _N share a common oscillator that generates ramp signals 328 ₁ , . . . , 328 _N . In another example, each of the two channels shown in Figure 7(a) includes a respective oscillator for generating ramp signals 568 and 570, respectively. In another example, the two channels shown in Figure 7(a) share a common oscillator that generates ramp signals 568 and 570.

Referring back to Figure 2, the amplification system 200 often involves high switching frequencies and it may be important to address electromagnetic interference issues.

Figure 8 is a simplified diagram of an amplification system in accordance with an embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. Amplification system 800 includes a modulator 802, an output stage 804, a low pass filter 806, and an output load 816. Modulator 802 includes a loop filter 812, an oscillator 808, and a comparator 810. For example, the output load 816 is a speaker. In another example, low pass filter 806 includes one or more inductors and/or one or more capacitors. In another example, low pass filter 806 includes one or more bead cores and/or one or more capacitors. in In another example, modulator 802, output stage 804, and low pass filter 806 are included in a class D amplifier.

According to one embodiment, loop filter 812 receives input audio signal 818 and outputs filtered signal 822 to comparator 810. For example, input audio signal 818 includes a pair of input signals. In another example, oscillator 808 generates a clock signal 826 and a ramp signal 824. As an example, comparator 810 receives ramp signal 824 and provides comparison signal 828 to output stage 804, which produces output signal 820. In one example, loop filter 812 receives output signal 820 as feedback. For example, low pass filter 806 converts output signal 820 to an audio signal 830 to drive output load 816. As shown in FIG. 8, modulator 802, output stage 804, and low pass filter 806 can be included in one channel of a multi-channel amplification system, in accordance with certain embodiments. For example, output signal 820 includes one or more signals. In another example, output signal 820 represents the difference between the two signals.

According to another embodiment, the oscillator 808 is configured to provide periodic jitter to the oscillating frequency of the clock signal 826 and/or the ramping frequency of the ramp signal 824. For example, the oscillation frequency of the clock signal 826 and/or the ramp frequency of the ramp signal 824 vary within a particular range in response to periodic jitter. In another example, the frequency of the periodic jitter (eg, the repetition rate) is greater than the upper limit of the range of audio frequencies (eg, approximately 20 Hz to approximately 20 KHz). In another example, the oscillation frequency of clock signal 826 is equal to the ramp frequency of ramp signal 824.

According to another embodiment, the oscillator 808 is configured to provide a combination of periodic jitter and pseudo-random jitter to the oscillation frequency of the clock signal 826 and/or the ramp frequency of the ramp signal 824. For example, the oscillating frequency of clock signal 826 and/or the ramping frequency of ramp signal 824 varies within a particular range in response to a combination of periodic jitter and pseudo-random jitter. In another example, the frequency of the pseudo-random jitter (eg, the repetition rate) is less than the lower limit of the range of audio frequencies (eg, about 20 Hz to about 20 KHz).

According to another embodiment, the ramp signal 824 is associated with one or more ramp cycles that are related to the ramp frequency of the ramp signal 824. For example, the oscillator 808 is configured to adjust the ramp signal 824 in the first ramp period to affect the slope of the ramp signal 824 in the next ramp period and/or the duration of the next ramp period. In particular, in some embodiments, the oscillator 808 is configured to change an uphill slope and/or a downhill slope associated with the ramp signal 824 (eg, For example, in a periodic manner or in a pseudo-random manner). According to some embodiments, the amplification system 800 illustrated in FIG. 8 may be implemented in one or more of the channels shown in FIG. 3, 7(a), and/or 7(b) to further improve The one or more channels. For example, a combination of periodic jitter or periodic jitter and pseudo-random jitter is provided to one or more channels that implement an amplification system similar to amplification system 800.

In one embodiment, loop filter 812 amplifies the error signal between input audio signal 818 and the feedback signal associated with output signal 820. For example, loop filter 812 includes a low pass filter that has a very high gain in the low frequency range (eg, a high gain greater than 1000) and a very low gain in the high frequency range (eg, a low gain that is much less than one). In another example, if the signal includes a low frequency component and a high frequency component, the loop filter 812 amplifies the low frequency component with a high gain and amplifies the high frequency component with a low gain (eg, a low gain much smaller than 1). . In another example, if the high frequency component is close to the switching frequency of the amplification system 800, the loop filter 812 attenuates the high frequency component. In one embodiment, loop filter 812 includes one or more analog integrator stages.

FIG. 9 is a simplified timing diagram of oscillator 808 with periodic jitter as part of amplification system 800, in accordance with an embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. Waveform 702 represents the oscillation frequency associated with clock signal 826 and/or the ramp frequency associated with ramp signal 824 of oscillator 808 as a function of time. The jitter period T ₀ starting at t ₀ and ending at t ₈ is shown in FIG. For example, t ₀ t ₁ t ₂ t ₃ t ₄ t ₅ t ₆ t ₇ t ₈ .

According to one embodiment, a plurality of frequency steps occur in the dither period T _0, where each frequency step corresponding to a specific oscillation frequency value or frequency value of the specific slope. For example, between t ₀ and t ₁ , the oscillation frequency or the ramp frequency has a value f ₁ . As an example, between t ₁ and t ₂ , the oscillation frequency or ramp frequency is increased to another value f ₂ and then increased to a value f ₃ between t ₃ and t ₄ . According to some embodiments, between t ₄ and t _5, the oscillation frequency or the frequency of the ramp dither peak period T ₀ f _4. By way of example, between t ₅ and t _8, the oscillation frequency values or the slope of the frequency decreases until the end of wobble period T _0, and then starts the next cycle jitter. For example, the frequency values f ₁ , f ₂ , f ₃ , f ₄ , f ₅ , f _{6 ,} and f ₇ occur again during the next jitter period. In another example, the frequency jitter repetition rate (e.g., dithering sequence repeat) inversely proportional to the wobble period T _0. In another example, the repetition rate is greater in magnitude than the upper limit of the range of audio frequencies (eg, from about 20 Hz to about 20 KHz). As an example, according to some embodiments, the frequency of the audio signal 830 is not affected by the frequency jitter shown in FIG.

Figure 10(a) is a simplified diagram showing certain elements of oscillator 808 with periodic jitter as part of amplification system 800, in accordance with one embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. The oscillator 808 includes a jitter sequencer 902, current sources 904 and 906, switches 908 and 910, a transconductance amplifier 912, a capacitor 916, comparators 914 and 918, inverse gates 920 and 922, and a buffer 924.

According to one embodiment, the jitter sequencer 902 receives the clock signal 826 and generates a signal 930 to trigger a change in the charging current 932 associated with the current source 904 and/or the discharging current 934 associated with the current source 906. For example, switch 908 is opened or closed in response to charge signal 926, and switch 910 is opened or closed in response to discharge signal 928. In one example, if the charge signal 926 is at a logic high level, the discharge signal 928 is at a logic low level, and if the charge signal 926 is at a logic low level, the discharge signal 928 is at a logic high level. In another example, clock signal 826 varies between a logic high level and a logic low level, similar to discharge signal 928. For example, clock signal 826 is associated with one or more oscillation periods corresponding to the oscillation frequency of clock signal 826. In another example, ramp signal 824 is associated with one or more ramp periods corresponding to the ramp frequency of ramp signal 824. In another example, the switching period is equal to the ramp period in duration. In another example, the switching period and the ramp period begin at the same time and end at the same time. In another example, during a ramp cycle, ramp signal 824 increases in magnitude over a period of time during the ramp period and decreases in magnitude over another period of the ramp period.

According to another embodiment, the jitter sequencer 902 detects a rising edge of the clock signal 826 and generates a signal 930 to change the charging current 932 and/or the discharging current 934 to cause the frequency of the clock signal 826 and/or the slope of the ramp signal 824. Frequency jitter. For example, the change in the oscillation frequency of the clock signal 826 and/or the ramp frequency of the ramp signal 824 is determined by the magnitude of the charge current 932 and/or the discharge current 934. In another example, at the rising edge of clock signal 826, ramp signal 824 reaches a peak within the ramp period. In another example, the charging current 932 is equal in magnitude to the discharging current 934. In another example, the charging current 932 and the discharging current 934 are equal in magnitude. In another example, the charging period used to charge capacitor 916 is determined based on a comparison between ramp signal 824 and reference signal 998 (eg, V _REF+ ). In another example, the discharge period for discharging capacitor 916 is determined based on a comparison between ramp signal 824 and reference signal 996 (eg, V _REF- ).

Figure 10(b) is a simplified timing diagram of oscillator 808 as shown in Figure 10(a) as part of amplification system 800, in accordance with one embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. Waveform 1006 represents clock signal 826 (eg, CLK) as a function of time, and waveform 1008 represents ramp signal 824 (eg, V _RAMP ) as a function of time. For example, t ₉ t ₁₀ t ₁₁ t ₁₂ t ₁₃ .

According to one embodiment, as shown in section 10 (b) drawing, in a first ramp cycle (e.g., T _n) during which the magnitude of the ramp signal 824 from the 1018 (e.g., at t ₉₎ is reduced to a value 1020 (e.g. At t ₁₀ ), then increase to magnitude 1022 (eg, at t ₁₁ ). For example, the ramp cycle (e.g., T _n) during the charging current 932 and / or 934 remains in a discharge current within a certain range (e.g., a range between the maximum value and the minimum value) of the first magnitude. According to some embodiments, at t _11, the second ramp cycle (e.g., T _{n + 1)} starts, and the rising edge of the clock signal 1028 occurs 826. For example, the jitter sequencer 902 outputs a signal 930 to vary the charging current 932 and/or the discharging current 934 to dither the oscillation frequency of the clock signal 826 and/or the ramp frequency of the ramp signal 824. In another example, in response to change in the charging current 932 and / or discharge current 934, a second ramp cycle (e.g., T _{n + 1)} of the slope of the ramp signal 824 becomes a first ramp cycle (e.g., T _n The slope of the mid-ramp signal 824 is different. In another example, in response to change in the charging current 932 and / or discharge current 934, a second ramp cycle (e.g., T _{n + 1)} becomes continuous and the duration of the first ramp cycle (e.g., T _n) of The time is different. In some embodiments, a change in the slope of the ramp signal 824 (eg, an uphill slope and/or a downhill slope) results in a change in the ramp frequency associated with the ramp signal 824 and/or the oscillation frequency associated with the clock signal 826. .

According to another embodiment, the second ramp cycle (e.g., T _{n + 1)} period, the ramp signal 824 from the value 1022 (e.g., at t ₁₁₎ is reduced to a value 1024 (e.g., at t _12), and then Increase to magnitude 1026 (eg, at t ₁₃ ). For example, during the second ramp period (eg, Tn ₊₁ ), the range between the maximum and minimum values of charge current 932 and/or discharge current 934 remains at the second magnitude. In another example, the second magnitude is different from the first magnitude. According to some embodiments, at t ₁₃ , a third ramp period (eg, T _n+2 ) begins and another rising edge 1030 occurs in clock signal 826 . For example, the jitter sequencer 902 changes the signal 930 to change the charging current 932 and/or the discharging current 934 to dither the oscillation frequency of the clock signal 826 and/or the ramp frequency of the ramp signal 824. In another example, in response to change in the charging current 932 and / or 934 of the discharge current, the third ramp cycle (e.g., T _{n + 2)} of the slope of the ramp signal 824 becomes a cycle with a second ramp (e.g., T _n The slope of the ₊₁ ) mid-slope signal 824 is different. In another example, in response to a change in charge current 932 and/or discharge current 934, the duration of the third ramp period (eg, Tn ₊₂ ) becomes the same as the second ramp period (eg, Tn ₊₁ ) The duration is different. In some embodiments, a change in the slope of the ramp signal 824 (eg, an uphill slope and/or a downhill slope) results in a change in the ramp frequency associated with the ramp signal 824 and/or the oscillation frequency associated with the clock signal 826. . For example, the magnitudes 1018, 1022, and 1026 of the ramp signal 824 are related to the reference signal 998 (eg, V _REF+ ), while the magnitudes 1020 and 1024 of the ramp signal 824 are related to the reference signal 996 (eg, V _REF- ).

Figure 10(c) is a simplified diagram showing certain elements of oscillator 808 with periodic jitter as part of amplification system 800, in accordance with another embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. The oscillator 808 includes a current controlled oscillating element 1410, an encoder 1406, a current digital analog converter (DAC) 1408, and a counter element 1404. For example, counter element 1404, encoder 1406, current DAC 1408 are included in jitter sequencer 902. In another example, a current DAC (eg, current DAC 1408) is included in current source 904 and/or current source 906. In another example, current controlled oscillating element 1410 includes current sources 904 and 906, switches 908 and 910, capacitor 916, transconductance amplifier 912, comparators 914 and 918, NAND gates 920 and 922, and buffer 924.

According to one embodiment, counter element 1404 receives clock signal 826 and generates signal 1412, which is encoded by encoder 1406. As an example, encoded signal 1414 is received by current DAC 1408, which outputs current signal 1416 (eg, I _dac2 ) to current controlled oscillating element 1410. In another example, current controlled oscillating element 1410 also receives current signal 1402 (eg, I ₀ ) and outputs clock signal 826 and ramp signal 824. As shown in FIG. 10(c), counter element 1404 changes signal 1412 in response to clock signal 826 to dither the oscillation frequency of clock signal 826 and/or the ramp frequency of ramp signal 824. For example, clock signal 826 is associated with one or more switching cycles corresponding to the oscillating frequency of clock signal 826. In another example, ramp signal 824 is associated with one or more ramp periods corresponding to the ramp frequency of ramp signal 824. In another example, the switching period is equal to the ramp period in duration. In another example, the switching period and the ramp period begin at the same time and end at the same time. In another example, current signal 1402 is fixed.

In accordance with another embodiment, at the beginning of the first switching cycle, counter element 1404 generates signal 1412 at a first value, and in response to signal 1412 being at a first value, current DAC 1408 generates a current signal 1416 at a first magnitude. . For example, the oscillating frequency of clock signal 826 and/or the ramping frequency of ramp signal 824 are dithered in response to current signal 1416 being at a first magnitude. In another example, at the beginning of a second switching cycle following the first switching cycle, counter element 1404 generates a signal 1412 at a second value, and in response to signal 1412 being at a second value, current DAC 1408 is generated at a second The magnitude of the current signal 1416. In another example, the oscillating frequency of clock signal 826 and/or the ramping frequency of ramp signal 824 are again dithered in response to current signal 1416 being at a second magnitude.

According to another embodiment, the ramp frequency of the ramp signal 824 is determined as follows: Wherein β represents a constant, I ₀ represents a direct current signal 1402, and I _dac2 represents a current signal 1416.

According to some embodiments, if I _dac2 <<I ₀ , the ramp frequency of the ramp signal 824 is determined as follows: Based on Equation 2, the ramp frequency of ramp signal 824 is modulated by current signal 1416. For example, the charging current 932 and the discharging current 934 satisfy the following formula: I _charge = I _discharge = I ₀ + I _{dac 2} (Equation 3)

According to another embodiment, if no input signal is received by the amplification system 800, the modulation period associated with the output signal 820 (eg, PWM) is determined as follows: Wherein T _{i, PWM} denotes the modulation period of the current output signal 820 _associated, T _{i-1, RAMP} represents the period of a ramp, and T _{i, RAMP} represents the current ramp cycle.

According to another embodiment, if the amplification system 800 receives one or more input signals, the duty cycle of the output signal 820 changes, and the modulation period associated with the output signal 820 is determined as follows: Where a represents a positive number associated with the input signal. According to some embodiments, based on Equation 5, if a varies as the input signal increases, the duty cycle of the output signal 820 increases and more frequency values of the output signal 820 occur.

11 is a simplified timing diagram of an amplification system 800 including an oscillator 808 with periodic jitter and receiving an input audio signal 818, in accordance with one embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. Waveform 1102 represents the value of the modulation frequency associated with output signal 820 (eg, PWM) of amplification system 800 as a function of time. For example, the amplification system 800 includes an oscillator 808 having periodic jitter as shown in FIG. 9, 10(a), 10(b), and/or 10(c).

As shown in Fig. 11, there are two jitter periods T ₁ and T _m . According to one embodiment, a plurality of frequency steps occur in each of the jitter periods T ₁ and T _m , wherein each frequency step corresponds to a particular switching frequency value. However, in some embodiments, the frequency value of the jitter period T _{1 is different} from the frequency value of the jitter period T _m , and further, the frequency values appearing in the jitter periods T ₁ and T _m and the frequency values in other jitter periods Different, as shown in Figure 11. According to some embodiments, by varying the charging current 932 and the discharging current 934 as compared to FIG. 9, more frequency values occur due to the jitter of the ramp signal 824 over time.

As described above and further emphasized here, FIG. 9, 10(a), 10(b), 10(c) and 11 are merely examples, which should not unduly limit the scope of patent application. The scope. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. In some embodiments, the jitter sequencer 902 is external to the oscillator 808. In some embodiments, counter element 1404, encoder 1406, and current DAC 1408 are external to oscillator 808. For example, although the 9th and 11th figures show the period jitter, the period jitter can be combined with the pseudo random jitter, as shown in FIG.

Figure 12 is a simplified spectrogram showing the combination of periodic jitter and pseudo-random jitter of oscillator 808 as part of amplification system 800, in accordance with another embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art.

According to one embodiment, the audio frequency range is between a frequency value f _c1 (eg, approximately 20 Hz) and a frequency value f _c2 (eg, approximately 20 kHz), and the oscillation frequency of the clock signal 826 (eg, f _osc ) is in magnitude Greater than the upper limit of the audio frequency range. As an example, the frequency associated with the period jitter shown in FIG. 9 and/or FIG. 11 (eg, f _j1 ) is greater in magnitude than the upper limit of the range of audio frequencies. In another example, the frequency associated with the pseudo-random jitter (eg, f _j2 ) is less than the lower limit of the range of audio frequencies. According to some embodiments, the frequency components of the audio signal 830 are not affected by periodic jitter and/or pseudo-random jitter. According to another embodiment, if the number of frequency values of the periodic jitter is N _j1 and the number of frequency values of the pseudo random jitter is N _j2 , the number of frequency values associated with the output signal 820 is determined without any input signal. As follows: N _total = N _{j 1} × N _{j 2} (Equation 6) where N _total represents the number of frequency values associated with the output signal 820. For example, if N _j1 =7 and N _j2 =16, then N _total = 112. According to some embodiments, if the amplification system 800 receives an input signal, more frequency values occur, as shown in FIG.

Figure 13 is a simplified spectrogram showing an amplification system 800 including an oscillator 808 having a combination of periodic jitter and pseudo-random jitter when the input audio signal 818 is zero, in accordance with one embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. Waveform 1202 represents the magnitude associated with output signal 820 (eg, PWM) of amplification system 800 as a function of frequency.

Figure 14(a) is an illustration of an embodiment of the present invention, shown as an enlargement A simplified diagram of certain elements of oscillator 808 with a combination of periodic jitter and pseudo-random jitter, part of system 800. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. The oscillator 808 includes a jitter sequencer 1502, current sources 1504 and 1506, switches 1508 and 1510, a transconductance amplifier 1512, a capacitor 1516, comparators 1514 and 1518, inverse gates 1520 and 1522, and a buffer 1524.

According to one embodiment, the jitter sequencer 1502 receives the clock signal 826 and generates a signal 1530 to trigger a change in the charging current 1532 associated with the current source 1504 and/or the discharging current 1534 associated with the current source 1506 to the clock signal 826. The oscillation frequency and/or the ramp frequency of the ramp signal 824 provides a combination of periodic jitter and pseudo-random jitter. For example, switch 1508 is opened or closed in response to charge signal 1526, and switch 1510 is opened or closed in response to discharge signal 1528. In one example, if the charge signal 1526 is at a logic high level, the discharge signal 1528 is at a logic low level, and if the charge signal 1526 is at a logic low level, the discharge signal 1528 is at a logic high level. In another example, clock signal 826 varies between a logic high level and a logic low level, similar to discharge signal 1528.

Figure 14(b) is a simplified diagram showing certain elements of an oscillator 808 having a combination of periodic jitter and pseudo-random jitter as part of an amplification system 800, in accordance with another embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. The oscillator 808 includes a current controlled oscillating element 1302, a linear feedback shift register (LFSR) element 1304, encoder elements 1306 and 1312, current digital class converters (DAC) 1308 and 1314, and a counter. Element 1310. For example, counter element 1310, encoder element 1312, current DAC 1314, LFSR 1304, encoder element 1306, and current DAC 1308 are included in jitter sequencer 1502. In another example, a current DAC (eg, current DAC 1308 or current DAC 1314) is included in current source 1504 and/or current source 1506. In another example, current controlled oscillating element 1302 includes current sources 1504 and 1506, switches 1508 and 1510, capacitor 1516, transconductance amplifier 1512, comparators 1514 and 1518, sluice gates 1520 and 1522, and buffer 1524.

According to one embodiment, LFSR 1304 implemented for pseudo-random jitter receives clock signal 826 and generates signal 1322, which is encoded by encoder element 1306. For example, encoded signal 1324 is received by DAC 1308, which outputs current signal 1318 (eg, I _dac1 ) to current controlled oscillating element 1302. In another example, counter element 1310 implemented for periodic jitter receives clock signal 826 and generates signal 1326, which is encoded by encoder element 1312. As an example, encoded signal 1328 is received by DAC 1314, which outputs current signal 1320 (eg, I _dac2 ) to current controlled oscillating element 1302. In another example, current controlled oscillating element 1302 also receives current signal 1316 (eg, I ₀ ) and outputs clock signal 826 and ramp signal 824. In another example, current signal 1316 is fixed.

According to another embodiment, the ramp frequency of the ramp signal 824 is determined as follows: Wherein β represents a constant, I ₀ represents a current signal 1316, I _dac1 represents a current signal 1318, and I _dac2 represents a current signal 1320.

According to some embodiments, if I _dac1 + I _dac2 <<I ₀ , the ramp frequency of the ramp signal 824 is determined as follows: Based on Equation 8, the ramp frequency of ramp signal 824 is modulated by current signals 1318 and 1320. For example, the charging current 932 and the discharging current 934 satisfy the following formula: | I _charge |=| I _discharge |=| I ₀ + I _{dac 1} + I _{dac 2} | (Equation 9)

As noted above and further emphasized herein, Figures 14(a) and 14(b) are merely examples and should not unduly limit the scope of the claimed scope. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. In some embodiments, the jitter sequencer 1502 is external to the oscillator 808. In some embodiments, counter element 1310, encoder 1306, and current DAC 1308 are external to oscillator 808.

Figure 15 is a simplified diagram of an amplification system including two channels, in accordance with one embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art.

Amplification system 1800 includes two channels 1802 ₁ and 1802 ₂ . The first channel 1802 ₁ includes a loop filter 1804 ₁ , comparators 1806 ₁ and 1808 ₁ , a logic controller 1810 ₁ , drive elements 1812 ₁ and 1814 ₁ , transistors 1816 ₁ , 1818 ₁ , 1820 ₁ and 1822 ₁ , Phase control element 1819 ₁ , and low pass filter 1824 ₁ . The second channel 1802 ₂ includes: a loop filter 1804 ₂ , comparators 1806 ₂ and 1808 ₂ , a logic controller 1810 ₂ , drive elements 1812 ₂ and 1814 ₂ , transistors 1816 ₂ , 1818 ₂ , 1820 ₂ and 1822 ₂ , Phase control element 1819 ₂ , and low pass filter 1824 ₂ . For example, each of the logic controllers 1810 ₁ and 1810 ₂ includes one or more buffers. As an example, each of low pass filters 1824 ₁ and 1824 ₂ includes one or more inductors and/or one or more capacitors. In another example, each of the low pass filters 1824 ₁ and 1824 ₂ includes one or more bead cores and/or one or more capacitors.

According to some embodiments, as shown in FIG. 15, the two channels 1802 ₁ and 1802 ₂ share a common ramp signal 1828. For example, channel 1802 ₁ generates output signals 1834 ₁ and 1836 ₁ and channel 1802 ₂ generates output signals 1834 ₂ and 1836 ₂ such that the audio signals are provided to output loads 1826 ₁ and 1826 ₂ (eg, speakers), respectively. As an example, loop filter 1804 ₁ amplifies the error signal between the input differential signal and the feedback differential signal associated with the output differential signal. In another example, the input differential signal represents the difference between the input signals 1830 ₁ and 1832 ₁ and the output differential signal represents the difference between the output signals 1834 ₁ and 1836 ₁ . In another example, loop filter 1804 ₁ is a low pass filter and it has a very high gain in the low frequency range (eg, a high gain greater than 1000) and a very low gain in the high frequency range (eg, far Less than 1 low gain). In another example, if the signal includes a low frequency component and a high frequency component, the loop filter 1804 ₁ amplifies the low frequency component with a high gain and amplifies the high frequency with a low gain (eg, a low gain much smaller than 1). Component. In another example, if the high frequency component is close to the switching frequency of the amplification system 1800, the loop filter 1804 ₁ attenuates the high frequency component. In one embodiment, loop filter 1804 ₁ includes one or more analog integrator stages. In some embodiments, loop filter 1804 _{2 is the} same as loop filter 1804 ₁ .

According to one embodiment, comparator output signals 1807 ₁ and 1809 ₁ are generated by comparators 1806 ₁ and 1808 ₁ , respectively. For example, phase control component 1819 ₁ adjusts the phase of comparator output signals 1807 ₁ and 1809 ₁ to change the phase of output signals 1834 ₁ and 1836 ₁ . As an example, comparator output signals 1807 ₂ and 1809 ₂ are generated by comparators 1806 ₂ and 1808 ₂ , respectively. In another example, phase control element 1819 ₂ adjusts the phase of comparator output signals 1807 ₂ and 1809 ₂ to change the phase of output signals 1834 ₂ and 1836 ₂ . According to some embodiments, in response to the same input differential signal path of ₁₈₀₂₁ and _{18022, 18021} and ₁₈₀₂₂ of the output signal (e.g., _{18341, 18342, 18361, 18362)} of the phase of the two channels It is adjusted by phase control elements 1819 ₁ and 1819 ₂ . For example, there is a phase shift between the output signals 1834 ₁ and 1834 ₂ . In another example, there is a phase shift between the output signals 1836 ₁ and 1836 ₂ .

Figure 16 is according to one embodiment of the present invention, when the input differential signal path ₁₈₀₂₁ and ₁₈₀₂₂ are both equal to the amplification system of FIG simplified timing 1800 at 0 volts. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. Waveform 1902 represents the input differential signal (eg, INN1-INP1) of channel 1802 ₁ as a function of time, waveform 1904 represents output signal 1836 ₁ (eg, OUTN1) as a function of time, and waveform 1906 will output signal 1834 ₁ (eg, , OUTP1) is expressed as a function of time, waveform 1908 represents the input differential signal of channel 1802 ₂ (eg, INN2-INP2) as a function of time, and waveform 1910 represents output signal 1836 ₂ (eg, OUTN2) as a function of time. Waveform 1912 represents output signal 1834 ₂ (eg, OUTP2) as a function of time. For example, the input differential signals of channels 1802 ₁ and 1802 ₂ are all equal to 0 volts indicating that input signals 1830 ₁ and 1832 _{1 are} identical, and input signals 1830 ₂ and 1832 _{2 are} identical.

According to some embodiments of the present invention, the first 17 (a) figure is a simplified view of a portion when the input differential signal path ₁₈₀₂₁ is equal to 0 volts channel _18021, and section 17 (b) and is a diagram illustrating when the channel input is equal to the difference signal path ₁₈ 022 0 volts when a simplified view of a portion of _18,022. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. For example, the 17th (a) diagram also includes a low pass filter 1824 ₁ and the 17th (b) diagram further includes a low pass filter 1824 ₂ .

According to some embodiments, as shown in Figure 16, if the channel input differential signals ₁₈₀₂₁ and ₁₈₀₂₂ are equal to 0 volts, the output signal of the _{18341, 18361, 18342} and ₁₈₃₆₂ duty cycle equal to about 50% . For example, the difference between the phase of the output signal 1834 _{1 and} the phase of the output signal 1834 ₂ is approximately equal to 180 degrees. As an example, the difference between the phase of the output signal 1836 _{1 and} the phase of the output signal 1836 ₂ is approximately equal to 180 degrees.

According to some embodiments, such as section 17 (a) Diagram, 17 (b) in FIG, 16 and FIG, during the time period t _1, the channel of transistor _1802118201 and ₁₈₁₆₁ are turned on, and the passage The transistors 1822 ₂ and 1818 _{2 of} 1802 ₂ are turned on. For example, during the time period t _1, the output signal ₁₈₃₆₁ at a logic high (e.g., 1904 as shown in the waveform), and the output signal ₁₈₃₄₁ at a logic high (e.g., as shown by the waveform 1906). In another example, during time period t ₁ , output signal 1836 _{2 is} at a logic low level (eg, as shown by waveform 1910), and output signal 1834 _{2 is} at a logic low level (eg, as shown by waveform 1912). .

According to one embodiment, t ₂ period, the transistor channel _1802118221 and ₁₈₁₈₁ are turned on in the next period, and the channel of the transistor ₁₈₀₂₂ and _{18202 18162} are turned on. For example, during time period t ₂ , output signal 1836 _{1 is} at a logic low level (eg, as shown by waveform 1904), and output signal 1834 _{1 is} at a logic low level (eg, as shown by waveform 1906). In another example, during time period t ₂ , output signal 1836 _{2 is} at a logic high level (eg, as shown by waveform 1910), and output signal 1834 _{2 is} at a logic high level (eg, as shown by waveform 1912). . In some embodiments, _18,341 and _18,361 since the output signal of the same channel _18021, and therefore no current flows through the output load ₁₈ 261 (e.g., a speaker). In certain embodiments, the channel is the same as the output signal of ₁₈₃₄₂ and _{18022 18362,} so no current flows through the output load ₁₈ 262 (e.g., a speaker).

Figure 18 is according to one embodiment of the present invention, when the same channel input differential ₁₈₀₂₁ and ₁₈₀₂₂ signals and higher than 0 volts amplification system simplified timing diagram 1800. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. Waveform 2002 represents the input differential signal of channel 1802 ₁ as a function of time, waveform 2004 represents output signal 1836 ₁ as a function of time, waveform 2006 represents output signal 1834 ₁ as a function of time, and waveform 2008 inputs channel 1802 ₂ The differential signal is represented as a function of time, waveform 2010 represents output signal 1836 ₂ as a function of time, and waveform 2012 represents output signal 1834 ₂ as a function of time. For example, an input differential signal of channel 1802 ₁ above 0 volts indicates that input signal 1830 _{1 is} higher than input signal 1832 ₁ . In another example, the input differential signal of channel 1802 ₂ is above 0 volts indicating that input signal 1830 _{2 is} higher than input signal 1832 ₂ .

According to some embodiments, as shown in FIG. 18, if the channel input differential ₁₈₀₂₁ and _18022, and the same signals are above 0 volts, the output duty signal ₁₈₃₄₁ and ₁₈₃₄₂ is less than 50%, the output signal 1836 The duty cycle of ₁ and 1836 ₂ is greater than 50%. For example, the difference between the phase of the output signal 1834 _{1 and} the phase of the output signal 1834 ₂ is approximately equal to the phase angle Φ. As an example, the difference between the phase of the output signal 1836 _{1 and} the phase of the output signal 1836 ₂ is approximately equal to the phase angle Φ. In some embodiments, if the channel input differential ₁₈₀₂₁ and _18022, and the same signals are higher than zero volts, the phase difference Φ is equal to 180 degrees.

According to some embodiments of the present invention, the first 19 (a) is a diagram showing FIG when the input differential signal path is greater than 0 _18,021 volts during a simplified diagram of a portion of the _third channel ₁₈ 021 in the period t, and section 19 ( b) is a diagram showing FIG channel when the differential input signal is higher than 0 volts _{18022, 18022} simplified diagram of a portion of the channel ₃ during the period t. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. For example, the 19th (a) diagram also includes a low pass filter 1824 ₁ and the 19th (b) diagram further includes a low pass filter 1824 ₂ .

According to some embodiments, as in FIG. 18, section 19 (a) view and 19 (b) shown in FIG., The period t _3, the channel of transistor 1802 _{118 201} and ₁₈ 181 are turned on, and the passage The transistors 1820 ₂ and 1818 _{2 of} 1802 ₂ are turned on. For example, during the time period t _3, the output signal ₁₈₃₆₁ at a logic high (e.g., 2004 as shown in the waveform), and the output signal ₁₈₃₄₁ at a logic low (e.g., as shown in the waveform 2006). In another example, during the time period t _3, the output signal ₁₈₃₆₂ at a logic high (e.g., 2010 as shown in the waveform), and the output signal ₁₈₃₄₂ at a logic low (e.g., as shown in the waveform 2012) . In another example, in channel 1802 ₁ , current 2098 ₁ flows through transistor 1820 ₁ , output load 1826 ₁ (eg, a speaker), and transistor 1818 ₁ . In another example, in channel 1802 ₂ , current 2098 ₂ flows through transistor 1820 ₂ , output load 1826 ₂ (eg, a speaker), and transistor 1818 ₂ .

According to some embodiments of the present invention, the first 20 (a) is a diagram showing FIG when the input differential signal path is greater than 0 _18,021 volts, a simplified diagram of channel _{4 18} 021 during a portion of the period t, and section 20 ( b) The figure is a simplified diagram showing a portion of the channel 1802 ₂ during the time period t ₄ when the input differential signal of the channel 1802 ₂ is above 0 volts. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. For example, the 20th (a) diagram also includes a low pass filter 1824 ₁ and the 20th (b) diagram further includes a low pass filter 1824 ₂ .

According to some embodiments, as in FIG. 18, section 20 (a) view and 20 (b) shown below, during the period t _4, the channel of transistor _1802118201 and ₁₈₁₆₁ are turned on, and the passage The transistors 1822 ₂ and 1818 _{2 of} 1802 ₂ are turned on. For example, during the time period t _4, the output signal ₁₈₃₆₁ at a logic high (e.g., 2004 as shown in the waveform), and the output signal ₁₈₃₄₁ at a logic high (e.g., as shown in the waveform 2006). In another example, during time period t ₄ , output signal 1836 _{2 is} at a logic low level (eg, as shown by waveform 2010), and output signal 1834 _{2 is} at a logic low level (eg, as shown by waveform 2012). . In another example, since the output load inductance characteristic of _18,261, a current flows through the transistor ₂₀₉₆₁ 1802 ₁ channel _{18201, 18261} output load (e.g., a speaker), and the transistor _18161. In another example, since the output load inductance characteristic of _18,262, a current flows through the passage ₂₀ 962 ₁₈ 022 ₁₈ 222 in the transistor, the output load ₁₈ 262 (e.g., a speaker), and the transistor _18182.

According to some embodiments of the present invention, the first 21 (a) is a diagram showing FIG when the input differential signal path is greater than 0 volts _18021, FIG. ₅ a simplified passage during part of the period ₁₈ 021 t, and section 21 ( b) The figure is a simplified diagram showing a portion of the channel 1802 ₂ during the time period t ₅ when the input differential signal of the channel 1802 ₂ is above 0 volts. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. For example, the 21st (a) diagram also includes a low pass filter 1824 ₁ and the 21st (b) diagram further includes a low pass filter 1824 ₂ .

According to some embodiments, as in FIG. 18, section 21 (a) view and 21 (b) shown below, during the period t _5, the channel of transistor _1802118201 and ₁₈₁₈₁ are turned on, and the passage The transistors 1820 ₂ and 1818 _{2 of} 1802 ₂ are turned on. For example, during the period t _5, the output signal ₁₈₃₆₁ at a logic high (e.g., 2004 as shown in the waveform), and the output signal ₁₈₃₄₁ at a logic low (e.g., as shown in the waveform 2006). In another example, during time period t ₅ , output signal 1836 _{2 is} at a logic high level (eg, as shown by waveform 2010), and output signal 1834 _{2 is} at a logic low level (eg, as shown in waveform 2012). . In another example, in channel 1802 ₁ , current 2094 ₁ flows through transistor 1820 ₁ , output load 1826 ₁ (eg, a speaker), and transistor 1818 ₁ . In another example, in channel 1802 ₂ , current 2094 ₂ flows through transistor 1820 ₂ , output load 1826 ₂ (eg, a speaker), and transistor 1818 ₂ .

According to some embodiments of the present invention, the first 22 (a) is a diagram showing FIG when the input differential signal path is greater than 0 _18,021 volts, a simplified diagram of the channel ₆ during part of the period ₁₈ 021 t, and section 22 ( b) The figure is a simplified diagram showing a portion of the channel 1802 ₂ during the time period t ₆ when the input differential signal of the channel 1802 ₂ is above 0 volts. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. For example, the 22(a) diagram also includes a low pass filter 1824 ₁ and the 22 (b) diagram further includes a low pass filter 1824 ₂ .

According to some embodiments, as in FIG. 18, section 22 (a) in FIG, 22 and (b), FIG, during the period t _6, the transistor channel _1802118221 and ₁₈₁₈₁ are turned on, and the passage The transistors 1820 ₂ and 1816 _{2 of} 1802 ₂ are turned on. For example, during the period t _6, the output signal ₁₈₃₆₁ at a logic low (e.g., 2004 as shown in the waveform), and the output signal ₁₈₃₄₁ at a logic low (e.g., as shown in the waveform 2006). In another example, during the period t _6, the output signal ₁₈₃₆₂ at a logic high (e.g., 2010 as shown in the waveform), and the output signal ₁₈₃₄₂ at a logic high (e.g., shown as waveform 2012) . In another example, since the output load inductance characteristic of _18,261, a current flows through the transistor ₂₀₉₂₁ 1802 ₁ channel _{18221, 18261} output load (e.g., a speaker), and the transistor _18181. In another example, since the output load inductance characteristic of _18,262, a current flows through the passage ₂₀ 922 ₁₈ 022 ₁₈ 202 in the transistor, the output load ₁₈ 262 (e.g., a speaker), and the transistor _18162.

Figure 23 is according to one embodiment of the present invention, when the same channel input differential ₁₈₀₂₁ and _18022, and were lower than the signal amplification system 0 volts simplified timing diagram 1800. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. Waveform 2102 represents the input differential signal of channel 1802 ₁ as a function of time, waveform 2104 represents output signal 1836 ₁ as a function of time, waveform 2106 represents output signal 1834 ₁ as a function of time, and waveform 2108 represents the input of channel 1802 ₂ The differential signal is represented as a function of time, waveform 2110 represents output signal 1836 ₂ as a function of time, and waveform 2112 represents output signal 1834 ₂ as a function of time. For example, an input differential signal of channel 1802 ₁ below 0 volts indicates that input signal 1830 _{1 is} lower than input signal 1832 ₁ . In another example, the input differential signal of channel 1802 ₂ is below 0 volts indicating that input signal 1830 _{2 is} lower than input signal 1832 ₂ .

According to some embodiments, as shown in FIG. 23, if the channel input differential ₁₈₀₂₁ and _18022, and the same signals are lower than 0 V, the duty cycle of the output signal of the ₁₈₃₄₁ and ₁₈₃₄₂ is greater than 50%, the output signal 1836 The duty cycle of ₁ and 1836 ₂ is less than 50%. For example, the difference between the phase of the output signal 1834 _{1 and} the phase of the output signal 1834 ₂ is approximately equal to the phase angle Φ'. As an example, the difference between the phase of the output signal 1836 _{1 and} the phase of the output signal 1836 ₂ is approximately equal to the phase angle Φ'. In some embodiments, if the channel input differential ₁₈₀₂₁ and _18022, and the same signals are lower than 0 V, the phase difference Φ 'equal to 180 degrees.

According to some embodiments of the present invention, the first 24 (a) is a diagram showing FIG when the input differential signal path is less than ₁₈ 021 0 volts, t is a simplified diagram of a portion of the ₁₈₀₂₁ channel ₇ during the period, and section 24 ( b) The figure is a simplified diagram showing a portion of the channel 1802 ₂ during the time period t ₇ when the input differential signal of the channel 1802 ₂ is below 0 volts. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. For example, the 24th (a) diagram also includes a low pass filter 1824 ₁ and the 24th (b) diagram further includes a low pass filter 1824 ₂ .

According to some embodiments, as in FIG. 23, section 24 (a) view and 24 (b) shown in FIG., During the time period t _7, the transistor channel _1802118221 and ₁₈₁₆₁ are turned on, and the passage The transistors 1822 ₂ and 1816 _{2 of} 1802 ₂ are turned on. For example, during the time period t _7, the output signal ₁₈₃₆₁ at a logic low (e.g., 2104 as shown in the waveform), and the output signal ₁₈₃₄₁ at a logic high (e.g., 2106 as shown in the waveform). In another example, during the time period t _7, the output signal ₁₈₃₆₂ at a logic low (e.g., 2110 as shown in the waveform), and the output signal ₁₈₃₄₂ at a logic high (e.g., shown as waveform 2112) . In another example, in channel 1802 ₁ , current 2198 ₁ flows through transistor 1816 ₁ , output load 1826 ₁ (eg, a speaker), and transistor 1822 ₁ . In another example, in channel 1802 ₂ , current 2198 ₂ flows through transistor 1816 ₂ , output load 1826 ₂ (eg, a speaker), and transistor 1822 ₂ .

According to some embodiments of the present invention, the first 25 (a) is a diagram showing FIG when the input differential signal path is less than ₁₈ 021 0 volt, a simplified diagram of the channel ₈ during part of the period ₁₈ 021 t, and section 25 ( b) The figure is a simplified diagram showing a portion of the channel 1802 ₂ during the time period t ₈ when the input differential signal of the channel 1802 ₂ is below 0 volts. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. For example, the 25(a) diagram also includes a low pass filter 1824 ₁ and the 25th (b) diagram further includes a low pass filter 1824 ₂ .

According to some embodiments, as in FIG. 23, the 25 (a) FIG. 25 and (b) in FIG, ₈ during the period t, the channel of transistor _1802118201 and ₁₈₁₆₁ are turned on, and the passage The transistors 1822 ₂ and 1818 _{2 of} 1802 ₂ are turned on. For example, during the period t _8, the output signal ₁₈₃₆₁ at a logic high (e.g., 2104 as shown in the waveform), and the output signal ₁₈₃₄₁ at a logic high (e.g., 2106 as shown in the waveform). In another example, during the period t _8, the output signal ₁₈₃₆₂ at a logic low (e.g., 2110 as shown in the waveform), and the output signal ₁₈₃₄₂ at a logic low (e.g., as shown in the waveform 2112) . In another example, since the output load inductance characteristic of _18,261, a current flows through the transistor ₂₁₉₆₁ 1802 ₁ channel _{18161, 18261} output load (e.g., a speaker), and the transistor _18201. In another example, since the output load inductance characteristic of _18,262, a current flows through the passage ₂₁ 962 ₁₈ 022 ₁₈ 182 in the transistor, the output load ₁₈ 262 (e.g., a speaker), and the transistor _18222.

According to some embodiments of the present invention, the first 26 (a) is a diagram showing FIG when the input differential signal path is less than 0 ₁₈ 021 volts, to simplify FIG. ₉ during the passage of a portion of the period ₁₈ 021 t, and section 26 ( b) is a diagram showing FIG when the input differential signal path is less than ₁₈ 022 0 volts, t during a simplified view of a portion of the channel ₉ in a period of _18,022. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. For example, the 26(a) diagram also includes a low pass filter 1824 ₁ and the 26 (b) diagram further includes a low pass filter 1824 ₂ .

According to some embodiments, as in FIG. 23, the 26 (a) view and 26 (b) shown in FIG. ₉ during the period t, the channel of transistor _1802118221 and ₁₈₁₆₁ are turned on, and the passage The transistors 1822 ₂ and 1816 _{2 of} 1802 ₂ are turned on. For example, during the period t _9, the output signal ₁₈₃₆₁ at a logic low (e.g., 2104 as shown in the waveform), and the output signal ₁₈₃₄₁ at a logic high (e.g., 2106 as shown in the waveform). In another example, during the period t _9, the output signal ₁₈₃₆₂ at a logic low (e.g., 2110 as shown in the waveform), and the output signal ₁₈₃₄₂ at a logic high (e.g., shown as waveform 2112) . In another example, in channel 1802 ₁ , current 2194 ₁ flows through transistor 1816 ₁ , output load 1826 ₁ (eg, a speaker), and transistor 1822 ₁ . In another example, in channel 1802 ₂ , current 2194 ₂ flows through transistor 1816 ₂ , output load 1826 ₂ (eg, a speaker), and transistor 1822 ₂ .

According to some embodiments of the present invention, the first 27 (a) is a diagram showing FIG when the input differential signal path is less than ₁₈ 021 0 volt, a simplified diagram of the channel ₁₀ during part of the period ₁₈ 021 t, and section 27 ( b) is a diagram showing FIG when the input differential signal path is less than ₁₈ 022 0 volts, the channel ₁₀ during a simplified view of a portion of the period T of _18,022. This figure is only an example and should not unduly limit the scope of the patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. For example, the 27(a) diagram also includes a low pass filter 1824 ₁ and the 27 (b) diagram further includes a low pass filter 1824 ₂ .

According to some embodiments, as in FIG. 23, section 27 (a) view and 27 (b) shown in FIG, ₁₀ during the period t, the channel of transistor 1802 _{118 221} and ₁₈ 181 are turned on, and the passage The transistors 1820 ₂ and 1816 _{2 of} 1802 ₂ are turned on. For example, during the period t _10, the output signal ₁₈₃₆₁ at a logic low (e.g., 2104 as shown in the waveform), and the output signal ₁₈₃₄₁ at a logic low (e.g., as shown in the waveform 2106). In another example, during time period t ₁₀ , output signal 1836 _{2 is} at a logic high level (eg, as shown by waveform 2110), and output signal 1834 _{2 is} at a logic high level (eg, as shown by waveform 2112) . In another example, since the output load inductance characteristic of _18,261, a current flows through the transistor ₂₁₉₂₁ 1802 ₁ channel _{18181, 18261} output load (e.g., a speaker), and the transistor _18221. In another example, since the output load inductance characteristic of _18,262, a current flows through the passage ₂₁ 922 ₁₈ 022 ₁₈ 162 in the transistor, the output load ₁₈ 262 (e.g., a speaker), and the transistor _18202.

According to one embodiment, a system for amplifying a plurality of input signals to generate a plurality of output signals includes: a first channel, a second channel, and a third channel. The first channel is configured to receive one or more first input signals, process information associated with the one or more first input signals and the first ramp signal, and based at least on the one or more first input signals The information associated with the first ramp signal generates one or more first output signals. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and the second ramp signal, and based at least on the one or more second input signals The information associated with the second ramp signal generates one or more second output signals. The third channel is configured to receive one or more third input signals, process information associated with the one or more third input signals and the third ramp signal, and based at least on the one or more third input signals And the information associated with the third ramp signal generates one or more third output signals. The first ramp signal corresponds to the first phase. The second ramp signal corresponds to the second phase. The first phase is different from the second phase. For example, the system is implemented at least in accordance with Figure 5, and/or Figure 6.

In accordance with another embodiment, a system for amplifying a plurality of input signals to generate a plurality of output signals includes a first channel and a second channel. The first channel is configured to receive one or more first input signals, process information associated with the one or more first input signals and the first ramp signal, and based at least on the one or more first input signals The information associated with the first ramp signal generates one or more first output signals. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and the second ramp signal, and based at least on the one or more second input signals The information associated with the second ramp signal generates one or more second output signals. The first ramp signal corresponds to the first phase. The second ramp signal corresponds to the second phase. The difference between the first phase and the second phase is equal to 180 degrees. For example, the system is implemented at least according to Figure 7(a).

In accordance with another embodiment, a system for amplifying a plurality of input signals to generate a plurality of output signals includes a first channel and a second channel. The first channel includes a first loop filter, a first signal processing component, and a first output component, and is configured to receive one or more first input signals, process the one or more first input signals and ramp signals Associated information and generating one or more first output signals based on at least information associated with the one or more first input signals and ramp signals. The second channel includes a second loop filter, a second signal processing component, and a second output component, and is configured to receive one or more second input signals, process the one or more second input signals, and ramp signals Associated information and generating one or more second output signals based on at least information associated with the one or more second input signals and the ramp signals. The first loop filter is configured to process information associated with the one or more first input signals and to generate one or more first filtered ones based on at least information associated with the one or more first input signals signal. The first signal processing component is configured to process information associated with the one or more first filtered signals and to generate one or more first based on at least information associated with the one or more first filtered signals Processed signal. The first output component is configured to process information associated with the one or more first processed signals and to generate one or more first outputs based on at least information associated with the one or more first processed signals signal. The second loop filter is configured to process information associated with the one or more second input signals and to generate one or more second filtered ones based on at least information associated with the one or more second input signals signal. The second signal processing component is configured to process with one or more The second filtered signal is associated with information and generates one or more second processed signals based on at least information associated with the one or more second filtered signals. The second output component is configured to process information associated with the one or more second processed signals and to generate one or more second outputs based on at least information associated with the one or more second processed signals signal. One or more first processed signals are associated with the first phase. One or more second processed signals are associated with the second phase. The difference between the first phase and the second phase is equal to 180 degrees. For example, the system is implemented at least according to Figure 7(b).

In one embodiment, a system for amplifying a plurality of input signals to generate a plurality of output signals includes: a first channel and a second channel. The first channel includes a first loop filter and one or more first comparators and is configured to receive one or more first input signals, the processing being associated with the one or more first input signals and ramp signals And generating one or more first output signals based on at least information associated with the one or more first input signals and the ramp signals. The second channel includes a second loop filter and one or more second comparators and is configured to receive one or more second input signals, the processing being associated with the one or more second input signals and the ramp signals And generating one or more second output signals based on at least information associated with the one or more second input signals and the ramp signals. The first loop filter is configured to process information associated with the one or more first input signals and to generate one or more first filtered ones based on at least information associated with the one or more first input signals signal. The one or more first comparators include one or more first ends and one or more second ends, and are configured to receive one or more first filtered signals at the first end and receive at the second end And ramping the signal, and generating one or more first comparison signals based on at least information associated with the first filtered signal and the ramp signal, and outputting the one or more first comparison signals to generate one or more first outputs signal. The second loop filter is configured to process information associated with the one or more second input signals and to generate one or more second filtered ones based on at least information associated with the one or more second input signals signal. The one or more second comparators include one or more third ends and one or more fourth ends, and are configured to receive one or more second filtered signals at the third end and receive at the fourth end And ramping the signal and generating one or more second comparison signals based on at least information associated with the second filtered signal and the ramp signal, and outputting the one or more second comparison signals to generate one or more second outputs letter number. One or more second ends include one or more inverting terminals, and one or more fourth terminals include one or more non-inverting terminals, or one or more second terminals include one or more non-inverting terminals And one or more fourth ends include one or more inverting terminals. For example, the system is implemented at least according to Figure 7(c).

In another embodiment, a system for amplifying a plurality of input signals to generate a plurality of output signals includes: an oscillator component configured to generate a ramp signal associated with a ramp frequency; a loop filter component Configuring to receive one or more input signals and generate one or more filtered signals based on at least information associated with the one or more input signals; and a comparator component configured to receive the one or more The filtered signal and the ramp signal generate one or more comparison signals based on at least information associated with the one or more filtered signals and ramp signals. The oscillator element is further configured to: periodically change the ramp frequency such that one or more changes in the ramp frequency are generated in each jitter period corresponding to the jitter frequency, and outputting a ramp associated with the changed ramp frequency signal. The jitter frequency is greater than the upper limit of the predetermined audio frequency range. For example, the system is implemented at least according to Fig. 8, Fig. 9, Fig. 10(a), Fig. 10(b), Fig. 10(c), and/or Fig. 11.

In another embodiment, a system for amplifying a plurality of input signals to generate a plurality of output signals includes an oscillator component configured to generate a ramp signal associated with a ramp frequency, the ramp frequency corresponding to one or a plurality of ramp cycles; a loop filter component configured to receive one or more input signals and to generate one or more filtered signals based on at least information associated with the one or more input signals; and a comparator An element configured to receive the one or more filtered signals and ramp signals and to generate one or more comparison signals based on at least information associated with the one or more filtered signals and ramp signals. The oscillator element is further configured to: change the charging current or the discharging current at the end of the first ramp period such that the first duration of the first ramp period is different from the second duration of the second ramp period following the first ramp period . The first duration and the second duration correspond to different magnitudes of the ramp frequency. For example, the system is based at least on the eighth, ninth, tenth (a), tenth (b), tenth (c), eleventh, twelfth, thirteenth, and fourteenth (th) a) Figure, and / or Figure 14 (b) to achieve.

According to one embodiment, a method for amplifying a plurality of input signals to generate a plurality of inputs The method of signaling includes: receiving one or more first input signals; processing information associated with the one or more first input signals and the first ramp signal; and based at least on the one or more first input signals The information associated with the first ramp signal generates one or more first output signals. The method also includes receiving one or more second input signals, processing information associated with the one or more second input signals and the second ramp signal, and based at least on the one or more second input signals and The information associated with the second ramp signal generates one or more second output signals. Additionally, the method includes receiving one or more third input signals; processing information associated with the one or more third input signals and the third ramp signal; and based at least on the one or more third input signals And the information associated with the third ramp signal generates one or more third output signals. The first ramp signal corresponds to the first phase. The second ramp signal corresponds to the second phase. The first phase is different from the second phase. For example, the method is implemented at least in accordance with FIG. 5, and/or FIG.

In accordance with another embodiment, a method for amplifying a plurality of input signals to generate a plurality of output signals includes receiving one or more first input signals, processing the one or more first input signals, and first ramp signals Associated information; and generating one or more first output signals based on at least information associated with the one or more first input signals and the first ramp signal. The method also includes receiving one or more second input signals, processing information associated with the one or more second input signals and the second ramp signal, and based at least on the one or more second input signals and The information associated with the second ramp signal generates one or more second output signals. The first ramp signal corresponds to the first phase. The second ramp signal corresponds to the second phase. The difference between the first phase and the second phase is equal to 180 degrees. For example, the method is implemented at least according to Figure 7(a).

In accordance with another embodiment, a method for amplifying a plurality of input signals to generate a plurality of output signals includes receiving one or a first channel including a first loop filter, a first signal processing component, and a first output component a plurality of first input signals; processing information associated with the one or more first input signals and ramp signals; and generating one or more based at least on information associated with the one or more first input signals and ramp signals The first output signal. The method also includes receiving, by the second channel including the second loop filter, the second signal processing component, and the second output component, one or more second input signals; processing the one or more second inputs Information associated with the signal and the ramp signal; and generating one or more second output signals based on at least information associated with the one or more second input signals and the ramp signal. Processing information associated with the one or more first input signals and the ramp signals includes: processing, by the first loop filter, information associated with the one or more first input signals; based at least on the one or more first Generating information associated with the input signal to generate one or more first filtered signals; processing, by the first signal processing component, information associated with the one or more first filtered signals; and based at least on one or more The information associated with the filtered signal generates one or more first processed signals. Generating the one or more first output signals based on at least information associated with the one or more first input signals and the ramp signals includes processing, by the first output element, information associated with the one or more first processed signals And generating one or more first output signals based on at least information associated with the one or more first processed signals. Processing information associated with the one or more second input signals and the ramp signal includes: processing, by the second loop filter, information associated with the one or more second input signals; based at least on one or more second Generating information associated with the input signal to generate one or more second filtered signals; processing, by the second signal processing component, information associated with the one or more second filtered signals; and based at least on one or more The information associated with the filtered signal generates one or more second processed signals. Generating the one or more second output signals based on at least information associated with the one or more second input signals and the ramp signals includes processing, by the second output element, information associated with the one or more second processed signals And generating one or more second output signals based on at least information associated with the one or more second processed signals. One or more first processed signals are associated with the first phase. One or more second processed signals are associated with the second phase, and the difference between the first phase and the second phase is equal to 180 degrees. For example, the method is implemented at least according to Figure 7(b).

In one embodiment, a method for amplifying a plurality of input signals to generate a plurality of output signals includes receiving one or more by a first channel including a first loop filter and one or more first comparators a first input signal; processing information associated with the one or more first input signals and the ramp signal; and generating one or more based at least on information associated with the one or more first input signals and the ramp signal An output signal. The method also includes receiving one or more second input signals by a second channel comprising a second loop filter and one or more second comparators; processing the one or more second input signals and ramp signals Associated And generating one or more second output signals based on at least information associated with the one or more second input signals and the ramp signals. Processing information associated with the one or more first input signals and the ramp signals includes processing, at the first loop filter, information associated with the one or more first input signals, and based at least on one or more Information associated with an input signal generates one or more first filtered signals. Generating the one or more first output signals based on at least information associated with the one or more first input signals and the ramp signals includes receiving one or more of the one or more first ends of the one or more first comparators First filtered signals; receiving, by the one or more second ends of the one or more first comparators, a ramp signal; generating one or more based on at least information associated with the first filtered signal and the ramp signal a first comparison signal; outputting the one or more first comparison signals; and generating one or more first output signals based on at least information associated with the one or more first comparison signals. Processing information associated with the one or more second input signals and the ramp signals includes processing, by the second loop filter, information associated with the one or more second input signals, and based at least on one or more The information associated with the two input signals generates one or more second filtered signals. Generating the one or more second output signals based on at least information associated with the one or more second input signals and the ramp signals includes receiving one or more of the one or more third ends of the one or more second comparators Second filtered signals; receiving, by one or more fourth ends of the one or more second comparators, a ramp signal; generating one or more based on at least information associated with the second filtered signal and the ramp signal a second comparison signal; outputting the one or more second comparison signals; and generating one or more second output signals based on at least information associated with the one or more second comparison signals. One or more second ends include one or more inverting terminals, and one or more fourth terminals include one or more non-inverting terminals, or one or more second terminals include one or more non-inverting terminals And one or more fourth ends include one or more inverting terminals. For example, the method is implemented at least according to Figure 7(c).

In another embodiment, a method for amplifying a plurality of input signals to generate a plurality of output signals includes: generating a ramp signal associated with a ramp frequency; receiving one or more input signals; and processing the one or more The information associated with the input signal. The method also includes generating one or more filtered signals based on at least information associated with the one or more input signals; receiving the one or more filtered signals and ramp signals; processing with the one or Information associated with the plurality of filtered signals and the ramp signals; and generating one or more comparison signals based on at least information associated with the one or more filtered signals and ramp signals. Generating a ramp signal associated with the ramp frequency includes periodically varying the ramp frequency such that one or more changes in the ramp frequency are generated in each jitter period corresponding to the jitter frequency, and the output is related to the changed ramp frequency Linked ramp signal. The jitter frequency is greater than the upper limit of the predetermined audio frequency range. For example, the method is implemented at least according to Fig. 8, Fig. 9, Fig. 10(a), Fig. 10(b), Fig. 10(c), and/or Fig. 11.

In another embodiment, a method for amplifying a plurality of input signals to generate a plurality of output signals includes: generating a ramp signal associated with a ramp frequency, the ramp frequency corresponding to one or more ramp cycles; receiving one or a plurality of input signals; and processing information associated with the one or more input signals. The method also includes generating one or more filtered signals based on at least information associated with the one or more input signals; receiving the one or more filtered signals and ramp signals; and based at least on the one or The plurality of filtered signals and the information associated with the ramp signals generate one or more comparison signals. Generating a ramp signal associated with the ramp frequency includes changing a charge current or a discharge current at the end of the first ramp period such that a first duration of the first ramp period is second with a second ramp period following the first ramp period The duration is different. The first duration and the second duration correspond to different magnitudes of the ramp frequency. For example, the method is based at least on the eighth, ninth, tenth (a), tenth (b), tenth (c), eleventh, twelfth, thirteenth, and fourteenth a) Figure, and / or Figure 14 (b) to achieve.

According to one embodiment, a system for amplifying a plurality of input signals to generate a plurality of output signals includes a first channel configured to receive a first input signal and a second input signal and based at least in part on the first input signal and The second input signal generates a first output signal and a second output signal; and a second channel configured to receive the third input signal and the fourth input signal and to generate a third based at least in part on the third input signal and the fourth input signal The output signal and the fourth output signal. The first differential signal is equal to the first input signal minus the second input signal. The second differential signal is equal to the third input signal minus the fourth input signal. The first output signal corresponds to the first phase. The second output signal corresponds to the second phase. The third output signal corresponds to the third phase. The fourth output signal corresponds to the fourth phase. The first phase difference is equal to the first phase minus the third phase. First The two phase differences are equal to the second phase minus the fourth phase. The first differential signal is the same as the second differential signal. The first phase difference is not equal to zero. The second phase difference is not equal to zero. The first phase difference is the same as the second phase difference.

In accordance with another embodiment, a system for amplifying a plurality of input signals to generate a plurality of output signals includes: a first channel configured to receive one or more first input signals, and based at least in part on the one or more The first input signals generate one or more first output signals; and the second channel is configured to receive the one or more second input signals and generate one or at least a portion based on the one or more second input signals A plurality of second output signals. The first differential signal associated with the one or more first input signals is equal to the second differential signal associated with the one or more second input signals. The one or more first output signals correspond to one or more first phases. The one or more second output signals correspond to one or more second phases. Each of the one or more differences between the one or more first phases and the corresponding one or more second phases is equal to 180 degrees.

In accordance with another embodiment, a system for amplifying a plurality of input signals to generate a plurality of output signals includes a first channel configured to receive a first input signal and a second input signal and based at least in part on the first input signal And generating, by the second input signal, the first output signal and the second output signal; and a second channel configured to receive the third input signal and the fourth input signal and generate the first based at least in part on the third input signal and the fourth input signal The three output signals and the fourth output signals. The first differential signal is equal to the first input signal minus the second input signal. The second differential signal is equal to the third input signal minus the fourth input signal. When the first output signal and the second output signal both correspond to the first logic level, and the third output signal and the fourth output signal both correspond to the second logic level, the second logic level is different from the first logic level.

In one embodiment, a method for amplifying a plurality of input signals to generate a plurality of output signals includes: receiving a first input signal and a second input signal; generating a first based at least in part on the first input signal and the second input signal And outputting the third input signal and the fourth input signal; and generating the third output signal and the fourth output signal based at least in part on the third input signal and the fourth input signal. The first differential signal is equal to the first input signal minus the second input signal. The second differential signal is equal to the third input signal minus the fourth input signal. The first output signal corresponds to the first phase. The second output signal corresponds to the second phase. Third output letter The number corresponds to the third phase. The fourth output signal corresponds to the fourth phase. The first phase difference is equal to the first phase minus the third phase. The second phase difference is equal to the second phase minus the fourth phase. The first differential signal is the same as the second differential signal. The first phase difference is not equal to zero. The second phase difference is not equal to zero. The first phase difference is the same as the second phase difference.

In another embodiment, a method for amplifying a plurality of input signals to generate a plurality of output signals includes: receiving one or more first input signals; generating one or at least a portion based on the one or more first input signals a plurality of first output signals; receiving one or more second input signals; and generating one or more second output signals based at least in part on the one or more second input signals. The first differential signal associated with the one or more first input signals is equal to the second differential signal associated with the one or more second input signals. The one or more first output signals correspond to one or more first phases. The one or more second output signals correspond to one or more second phases. Each of the one or more differences between the one or more first phases and the corresponding one or more second phases is equal to 180 degrees.

In another embodiment, a method for amplifying a plurality of input signals to generate a plurality of output signals includes: receiving a first input signal and a second input signal; generating a first portion based at least in part on the first input signal and the second input signal An output signal and a second output signal; receiving the third input signal and the fourth input signal; generating the third output signal and the fourth output signal based at least in part on the third input signal and the fourth input signal. The first differential signal is equal to the first input signal minus the second input signal. The second differential signal is equal to the third input signal minus the fourth input signal. When the first output signal and the second output signal both correspond to the first logic level, and the third output signal and the fourth output signal both correspond to the second logic level, the second logic level is different from the first logic level.

For example, some or all of the various embodiments of the various embodiments of the invention may be used individually and by using one or more software elements, one or more hardware elements, and/or one or more combinations of software and hardware elements. / or implemented in combination with at least one other component. In another example, some or all of the elements of various embodiments of the invention are each implemented in one or more circuits, individually and/or in combination with at least one other element, such as one or more circuits One or more analog circuits and/or one or more digital circuits. In yet another example, various embodiments and/or examples of the invention can be combined.

Although specific embodiments of the invention have been described, Skilled artisans will appreciate that there are other embodiments that are equivalent to the described embodiments. Therefore, it is to be understood that the invention is not limited by the particular illustrated embodiment, but only by the scope of the appended claims.

300‧‧‧Amplification system

304 ₁ , 304 _N ‧‧‧ loop filter

302 ₁ ,...,302 _n ‧‧‧ channels

306 ₁ , 306 _N , 308 ₁ , 308 _N ‧ ‧ comparator

310 ₁ , 310 _N ‧‧‧Logic Controller

312 ₁ , 312 _N , 314 ₁ , 314 _N ‧‧‧ drive components

316 ₁ ,316 _N ,318 ₁ ,318 _N ,320 ₁ ,320 _N ,322 ₁ ,322 _N ‧‧‧O crystal

324 ₁ , 324 _N ‧‧‧ low pass filter

326 ₁ , 326 _N ‧‧‧Speaker load

328 ₁ ,...,328 _N ‧‧‧Ramp signal

332 ₁ , 332 _N , 330 ₁ , 330 _N ‧‧‧ Input signal

334 ₁ ,334 _N ,336 ₁ ,336 _N ‧‧‧Output signal

Claims (38)

A system for amplifying a plurality of input signals to generate a plurality of output signals, the system comprising: a first channel configured to receive a first input signal and a second input signal and based at least in part on The first input signal and the second input signal generate a first output signal and a second output signal; and a second channel configured to receive the third input signal and the fourth input signal and based at least in part on The third input signal and the fourth input signal generate a third output signal and a fourth output signal; wherein: the first differential signal is equal to the first input signal minus the second input signal; and the second differential signal Equal to the third input signal minus the fourth input signal; wherein: the first output signal corresponds to a first phase; the second output signal corresponds to a second phase; the third output signal corresponds to a third phase; and the fourth output signal corresponds to a fourth phase; wherein: the first phase difference is equal to the first phase minus the third phase; and the second a bit difference equal to the second phase minus the fourth phase; wherein: the first differential signal is the same as the second differential signal; the first phase difference is not equal to 0; the second phase difference is not Equal to 0; the first phase difference is the same as the second phase difference. The system of claim 1, wherein the first channel is further configured to: receive a ramp signal; and generate at least in part based on the first input signal, the second input signal, and the ramp signal The first output signal and the second output signal. The system of claim 1, wherein the second channel is further configured to: receive a ramp signal; and generate at least in part based on the third input signal, the fourth input signal, and the ramp signal The third output signal and the fourth output signal. The system of claim 1, wherein: the first phase difference is equal to 180 degrees; and the second phase difference is equal to 180 degrees. The system of claim 1, wherein the first channel comprises: a first loop filter, the first loop filter configured to receive the first input signal, the second An input signal, the first output signal, and the second output signal, and based at least in part on the first input signal, the second input signal, the first output signal, and the second output signal a filtered signal and a second filtered signal; a first signal processing component, the first signal processing component configured to receive the first filtered signal, the second filtered signal, and a ramp signal And generating one or more first processed signals based at least in part on the first filtered signal, the second filtered signal, and the ramp signal; and one or more first output elements, The one or more first output elements are configured to receive the one or more first processed signals and generate the first output signal based at least in part on the one or more first processed signals And the second output signal. The system of claim 5, wherein the first signal processing component comprises: a first comparator, the first comparator configured to receive the ramp signal and the first filtered signal And generating a first comparison signal based at least in part on the ramp signal and the first filtered signal; and a second comparator configured to receive the ramp signal and the second And filtering the signal and generating a second comparison signal based at least in part on the ramp signal and the second filtered signal. The system of claim 6, wherein the first signal processing component further comprises: a phase control component configured to receive the first comparison signal and the second comparison signal, And based at least in part on the first comparison signal and the second comparison Generating one or more phase control signals; and logic control elements configured to receive the one or more phase control signals and generate one or at least in part based on the one or more phase control signals Multiple logic control signals. The system of claim 7, wherein the first signal processing component further comprises: a first driver component, the first driver component being configured to be based at least in part on the one or more logic control signals, Outputting one or more first drive signals to the one or more first output elements; and a second driver element configured to be based at least in part on the one or more logic control signals, Outputting one or more second drive signals to the one or more first output elements; wherein the one or more first drive signals and the one or more second drive signals are included in the one Or among a plurality of first processed signals. The system of claim 1, wherein the second channel comprises: a first loop filter, the first loop filter configured to receive the third input signal, the fourth An input signal, the third output signal, and the fourth output signal, and based at least in part on the third input signal, the fourth input signal, the third output signal, and the fourth output signal a filtered signal and a second filtered signal; a first signal processing component, the first signal processing component configured to receive the first filtered signal, the second filtered signal, and a ramp signal And generating one or more first processed signals based at least in part on the first filtered signal, the second filtered signal, and the ramp signal; and one or more first output elements, The one or more first output elements are configured to receive the one or more first processed signals and generate the third output signal based at least in part on the one or more first processed signals And the fourth output signal. The system of claim 9, wherein the first signal processing component comprises: a first comparator, the first comparator configured to receive the ramp signal and the first filtered signal And generating a first comparison signal based at least in part on the ramp signal and the first filtered signal; a second comparator, the second comparator configured to receive the ramp signal and the second filtered signal and generate a second comparison based at least in part on the ramp signal and the second filtered signal signal. The system of claim 10, wherein the first signal processing component further comprises: a phase control component configured to receive the first comparison signal and the second comparison signal, And generating one or more phase control signals based at least in part on the first comparison signal and the second comparison signal; and a logic control element configured to receive the one or more phase control signals, And generating one or more logic control signals based at least in part on the one or more phase control signals. The system of claim 11, wherein the first signal processing component further comprises: a first driver component, the first driver component configured to be based at least in part on the one or more logic control signals, Outputting one or more first drive signals to the one or more first output elements; and a second driver element configured to be based at least in part on the one or more logic control signals, Outputting one or more second drive signals to the one or more first output elements; wherein the one or more first drive signals and the one or more second drive signals are included in the one Or among a plurality of first processed signals. A system for amplifying a plurality of input signals to generate a plurality of output signals, the system comprising: a first channel configured to receive one or more first input signals, and based at least in part on One or more first input signals generate one or more first output signals; and a second channel configured to receive one or more second input signals and based at least in part on the one or more Second input signals generate one or more second output signals; Wherein the first differential signal associated with the one or more first input signals is equal to a second differential signal associated with the one or more second input signals; wherein: the one or more first The output signal corresponds to one or more first phases; the one or more second output signals correspond to one or more second phases; and the one or more first phases are associated with one or more Each of the one or more differences between the two phases is equal to 180 degrees. The system of claim 13, wherein the first channel is further configured to: receive a ramp signal; and generate the one based at least in part on the one or more first input signals and the ramp signal Or a plurality of first output signals. The system of claim 13 wherein the second channel is further configured to: receive a ramp signal; and generate the one based at least in part on the one or more second input signals and the ramp signal Or a plurality of second output signals. The system of claim 13, wherein the first channel comprises: a first loop filter, the first loop filter configured to receive the one or more first input signals and Generating the one or more first output signals and generating one or more first filtered signals based at least in part on the one or more first input signals and the one or more first output signals; a signal processing component, the first signal processing component configured to receive the one or more first filtered signals and ramp signals, and based at least in part on the one or more first filtered signals and the The ramp signal generates one or more first processed signals; and one or more first output elements configured to receive the one or more first processed signals And generating the one or more first output signals based at least in part on the one or more first processed signals. The system of claim 16, wherein the first signal processing component comprises: one or more comparators, the one or more comparators configured to receive the ramp signal and the one or a plurality of first filtered signals, and based at least in part on the ramp signal And generating the one or more comparison signals with the one or more first filtered signals. The system of claim 17, wherein the first signal processing component further comprises: a phase control component configured to receive the one or more comparison signals, and based at least in part on Generating one or more comparison signals to generate one or more phase control signals; and logic control elements configured to receive the one or more phase control signals and based at least in part on the one or more The phase control signal generates one or more logic control signals. The system of claim 18, wherein the first signal processing component further comprises: one or more driver components, the one or more driver components being configured to be based at least in part on the one or more A logic control signal outputting one or more drive signals to the one or more first output elements; wherein the one or more drive signals are included in the one or more first processed signals. The system of claim 13, wherein the second channel comprises: a first loop filter, the first loop filter configured to receive the one or more second input signals and Generating the one or more second output signals and generating one or more first filtered signals based at least in part on the one or more second input signals and the one or more second output signals; a signal processing component, the first signal processing component configured to receive the one or more first filtered signals and ramp signals, and based at least in part on the one or more first filtered signals and the The ramp signal generates one or more first processed signals; and one or more first output elements configured to receive the one or more first processed signals And generating the one or more second output signals based at least in part on the one or more first processed signals. The system of claim 20, wherein the first signal processing component comprises: one or more comparators, the one or more comparators configured to receive the ramp letter And the one or more first filtered signals and generating one or more comparison signals based at least in part on the ramp signal and the one or more first filtered signals. The system of claim 21, wherein the first signal processing component further comprises: a phase control component configured to receive the one or more comparison signals, and based at least in part on Generating one or more comparison signals to generate one or more phase control signals; and logic control elements configured to receive the one or more phase control signals and based at least in part on the one or more The phase control signal generates one or more logic control signals. The system of claim 22, wherein the first signal processing component further comprises: one or more driver components, the one or more driver components being configured to be based at least in part on the one or more A logic control signal outputting one or more drive signals to the one or more first output elements; wherein the one or more drive signals are included in the one or more first processed signals. A system for amplifying a plurality of input signals to generate a plurality of output signals, the system comprising: a first channel configured to receive a first input signal and a second input signal and based at least in part on The first input signal and the second input signal generate a first output signal and a second output signal; and a second channel configured to receive the third input signal and the fourth input signal and based at least in part on The third input signal and the fourth input signal generate a third output signal and a fourth output signal; wherein: the first differential signal is equal to the first input signal minus the second input signal; and the second differential signal Equal to the third input signal minus the fourth input signal; Wherein, when the first output signal and the second output signal both correspond to a first logic level, and the third output signal and the fourth output signal both correspond to a second logic level, the The two logic levels are different from the first logic level. The system of claim 24, wherein the first logic level corresponds to a logic low level and the second logic level corresponds to a logic high level. The system of claim 24, wherein the first channel is further configured to: receive a ramp signal; and generate at least in part based on the first input signal, the second input signal, and the ramp signal The first output signal and the second output signal. The system of claim 24, wherein the second channel is further configured to: receive a ramp signal; and generate at least in part based on the third input signal, the fourth input signal, and the ramp signal The third output signal and the fourth output signal. The system of claim 24, wherein the first channel comprises: a first loop filter, the first loop filter configured to receive the first input signal, the second An input signal, the first output signal, and the second output signal, and based at least in part on the first input signal, the second input signal, the first output signal, and the second output signal a filtered signal and a second filtered signal; a first signal processing component, the first signal processing component configured to receive the first filtered signal, the second filtered signal, and a ramp signal And generating one or more first processed signals based at least in part on the first filtered signal, the second filtered signal, and the ramp signal; and one or more first output elements, The one or more first output elements are configured to receive the one or more first processed signals and to generate the first output based at least in part on the one or more first processed signals Number and the second output signal. The system of claim 28, wherein the first signal processing component comprises: a first comparator, the first comparator configured to receive the ramp signal and the first filtered signal And generating a first comparison signal based at least in part on the ramp signal and the first filtered signal; a second comparator, the second comparator configured to receive the ramp signal and the second filtered signal and generate a second comparison based at least in part on the ramp signal and the second filtered signal signal. The system of claim 29, wherein the first signal processing component further comprises: a phase control component configured to receive the first comparison signal and the second comparison signal, And generating one or more phase control signals based at least in part on the first comparison signal and the second comparison signal; and a logic control element configured to receive the one or more phase control signals, And generating one or more logic control signals based at least in part on the one or more phase control signals. The system of claim 30, wherein the first signal processing component further comprises: a first driver component, the first driver component being configured to be based at least in part on the one or more logic control signals, Outputting one or more first drive signals to the one or more first output elements; and a second driver element configured to be based at least in part on the one or more logic control signals, Outputting one or more second drive signals to the one or more first output elements; wherein the one or more first drive signals and the one or more second drive signals are included in the one Or among a plurality of first processed signals. The system of claim 24, wherein the second channel comprises: a first loop filter, the first loop filter configured to receive the third input signal, the fourth An input signal, the third output signal, and the fourth output signal, and based at least in part on the third input signal, the fourth input signal, the third output signal, and the fourth output signal a filtered signal and a second filtered signal; a first signal processing component, the first signal processing component configured to receive the first filtered signal, the second filtered signal, and a ramp signal And generating one or more based at least in part on the first filtered signal, the second filtered signal, and the ramp signal First processed signals; and one or more first output elements, the one or more first output elements configured to receive the one or more first processed signals, and based at least in part on The one or more first processed signals generate the third output signal and the fourth output signal. The system of claim 32, wherein the first signal processing component comprises: a first comparator, the first comparator configured to receive the ramp signal and the first filtered signal And generating a first comparison signal based at least in part on the ramp signal and the first filtered signal; and a second comparator configured to receive the ramp signal and the second And filtering the signal and generating a second comparison signal based at least in part on the ramp signal and the second filtered signal. The system of claim 33, wherein the first signal processing component further comprises: a phase control component configured to receive the first comparison signal and the second comparison signal, And generating one or more phase control signals based at least in part on the first comparison signal and the second comparison signal; and a logic control element configured to receive the one or more phase control signals, And generating one or more logic control signals based at least in part on the one or more phase control signals. The system of claim 34, wherein the first signal processing component further comprises: a first driver component, the first driver component configured to be based at least in part on the one or more logic control signals, Outputting one or more first drive signals to the one or more first output elements; and a second driver element configured to be based at least in part on the one or more logic control signals, Outputting one or more second drive signals to the one or more first output elements; wherein the one or more first drive signals and the one or more second drive signals are included in the one Or among a plurality of first processed signals. A method for amplifying a plurality of input signals to generate a plurality of output signals, the method comprising: receiving a first input signal and a second input signal; generating at least in part based on the first input signal and the second input signal a first output signal and a second output signal; receiving a third input signal and a fourth input signal; and generating a third output signal and a fourth output signal based at least in part on the third input signal and the fourth input signal; The first differential signal is equal to the first input signal minus the second input signal; and the second differential signal is equal to the third input signal minus the fourth input signal; wherein: the first output signal Corresponding to the first phase; the second output signal corresponds to the second phase; the third output signal corresponds to the third phase; and the fourth output signal corresponds to the fourth phase; wherein: the first phase difference is equal to The first phase is subtracted from the third phase; and the second phase difference is equal to the second phase minus the fourth phase; wherein: the first differential signal is The same as said second differential signal; the first phase is not equal to 0; 0 is not equal to the second phase; the first phase and the second phase of the same. A method for amplifying a plurality of input signals to generate a plurality of output signals, the method comprising: receiving one or more first input signals; generating one or more based at least in part on the one or more first input signals First output Receiving one or more second input signals; and generating one or more second output signals based at least in part on the one or more second input signals; wherein, the one or more first input signals are associated The first differential signal is equal to a second differential signal associated with the one or more second input signals; wherein: the one or more first output signals correspond to one or more first phases; One or more second output signals corresponding to one or more second phases; and each of the one or more differences between the one or more first phases and the respective one or more second phases Equal to 180 degrees. A method for amplifying a plurality of input signals to generate a plurality of output signals, the method comprising: receiving a first input signal and a second input signal; generating at least in part based on the first input signal and the second input signal a first output signal and a second output signal; receiving a third input signal and a fourth input signal; generating a third output signal and a fourth output signal based at least in part on the third input signal and the fourth input signal; wherein: a first differential signal equal to the first input signal minus the second input signal; and a second differential signal equal to the third input signal minus the fourth input signal; wherein, when the first output signal And the second output signal both correspond to a first logic level, the third output signal and the fourth output signal both correspond to a second logic level, the second logic level and the first The logic levels are different.