TW201604617A - Device substrate and aligning method thereof - Google Patents

Abstract

A device substrate including a substrate having an active region and a peripheral region, a pixel array disposed within the active region, signal pads disposed above the substrate and electrically connected to the pixel array and at least one test pad disposed within the peripheral region and electrically connected to the pixel array is provided. The test pad includes a conductive layer disposed above the peripheral region, an insulation layer covering the conductive layer and a contact pattern layer disposed above the insulation layer. The insulation layer has at least one contact opening and at least one groove. The contact opening exposes the conductive layer. The contact pattern layer is electrically connected to the conductive layer through the contact opening. A portion of the contact pattern layer is disposed within the groove. Moreover, an alignment method of the device substrate is also provided.

Description

Component substrate and alignment method thereof

The present invention relates to a substrate and an alignment method thereof, and more particularly to an element substrate and an alignment method thereof.

The display panel includes an element substrate, an opposite substrate with respect to the element substrate, and a display medium disposed between the element substrate and the opposite substrate. Taking a liquid crystal display panel as an example, the display medium is a plurality of liquid crystal molecules. When the display panel is enabled, an alignment film is usually disposed on the element substrate in order to enable the optical axis of the liquid crystal molecules to be correctly and quickly rotated to a specified direction to provide a transmittance corresponding to the pixel. Through the anchoring force provided by the alignment film, the optical axes of the plurality of liquid crystal molecules can be tilted in a specified direction when the display panel is not enabled, that is, the liquid crystal molecules have a specified pre-tilt angle. Thereby, when the display panel is enabled, the optical axes of the plurality of liquid crystal molecules can be correctly and quickly turned to a specified direction, thereby providing the user with good image quality.

However, a test pad for the tester to test the pixel array of the element substrate is provided on the peripheral portion of the element substrate. In general, the test pad has a higher height than the film layer around it, such that there is a gap between the test pad and its surrounding film layer. The height difference. When a contact alignment process is performed on the alignment film by using an alignment tool, the pressure of the alignment tool under the alignment film is affected by the height difference between the test pad and the surrounding film layer, thereby causing the active area of the element substrate. The size of the anchoring force in the vicinity of the boundary with the peripheral zone and the center of the active zone is inconsistent, that is, the problem of rubbing mura occurs.

The present invention provides an element substrate capable of improving the phenomenon of poor alignment.

The present invention provides a component substrate comprising a substrate having an active region and a peripheral region, a pixel array in the active region, a plurality of signal pads on the substrate and electrically connected to the pixel array, and a peripheral region and The pixel array is electrically connected to at least one test pad. The test pad includes a conductive layer in the peripheral region, an insulating layer covering the conductive layer, and a contact pattern layer on the insulating layer. The insulating layer has at least one contact opening and at least one groove. The contact opening exposes the conductive layer. The contact pattern layer is electrically connected to the conductive layer through the contact opening. A portion of the contact pattern layer is located within the trench.

The invention provides a method for aligning an element substrate, comprising the steps of: providing the above-mentioned element substrate; forming an alignment film on the element substrate to cover the pixel array and the test pad; and performing a contact alignment on the alignment film by using an alignment tool The program, the alignment tool first overlaps the test pads and then overlaps with the active area.

Based on the above, in the element substrate of one embodiment of the present invention, the contact pattern layer of the test pad extends toward the trench of the insulating layer such that a portion of the contact pattern layer is located in the trench of the insulating layer, and the partial contact at this time The pattern layer is laid on the sidewall of the trench Form a gentle slope. When a contact alignment process is performed on the alignment film laid on the test pad and the pixel array by using an alignment tool, the alignment tool can follow the gentle slope with a stable downforce to the vicinity of the active zone and the peripheral zone. Part of the alignment film and a portion of the alignment film near the center of the active region are aligned. As a result, the alignment films on the regions on the element substrate can have similar anchoring forces, thereby improving the poor alignment in the prior art.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧Roller

20‧‧‧布毛

100, 100A, 100C~100F‧‧‧ element substrate

110‧‧‧Substrate

110a‧‧‧active area

110b‧‧‧ surrounding area

110c‧‧‧ bearing surface

120‧‧‧ pixel array

122, 122A‧‧‧ pixel structure

122a‧‧‧Active components

122b‧‧‧ pixel electrodes

122b1‧‧‧ branches of pixel electrodes

122c‧‧‧Common electrode

122c1‧‧‧ branch of the common electrode

130‧‧‧Signal pads

140, 140C, 140F‧‧‧ test pads

142, 142D‧‧‧ conductive layer

142a‧‧‧ Body Department

142b‧‧‧Bridge electrode

142c‧‧‧ openings

144‧‧‧Insulation

144a, 144aA, 144aE‧‧‧ first insulation

144b‧‧‧Second insulation

146‧‧‧Contact pattern layer

146a‧‧‧ edge

150‧‧‧ drive circuit

160‧‧‧Soft circuit board

A-A’, D-D’‧‧‧ cut line

DL‧‧‧ data line

Hc‧‧ contact opening

Hp, HpA, HpD, HpE‧‧‧ trench

D1‧‧‧ normal direction

D2‧‧‧ direction

d3‧‧‧Predetermined alignment direction

SL‧‧‧ scan line

S1‧‧‧ first side wall

S2‧‧‧ second side wall

S3‧‧‧ bottom

R‧‧‧ Alignment tool

PI‧‧‧ alignment film

K‧‧‧ component substrate part

W1, W2, W3‧‧‧ width

1 is a top plan view of a component substrate according to an embodiment of the present invention.

2A is an enlarged schematic view showing a portion K of the element substrate of FIG. 1.

Fig. 2B is a schematic cross-sectional view showing a part of the element substrate taken along the line A-A' of Fig. 2A.

2C is a top plan view of the conductive layer of the test pad of FIG. 2A.

3 is a top plan view showing a pixel structure, a data line, and a scan line of a component substrate according to another embodiment of the present invention.

4 is a cross-sectional view showing a portion of a component substrate according to another embodiment of the present invention.

Fig. 5 is a top plan view showing a part of a component substrate according to still another embodiment of the present invention.

6A is a top plan view showing a part of a component substrate according to still another embodiment of the present invention.

Figure 6B is a partial cross-section of the element substrate depicted by the line D-D' of Figure 6A. schematic diagram.

Fig. 7 is a cross-sectional view showing a part of a component substrate according to still another embodiment of the present invention.

FIG. 8 is a top plan view of a component substrate according to an embodiment of the present invention.

1 is a top plan view of a component substrate according to an embodiment of the present invention. element The substrate 100 includes a substrate 110, a pixel array 120, a plurality of signal pads 130, and at least one test pad 140. The substrate 110 has an active area 110a and a peripheral area 110b, and the peripheral area 110b is connected to the active area 110a and surrounds the active area 110a. The pixel array 120 is located within the active region 110a of the substrate 110. A plurality of signal pads 130 are located in the peripheral region 110b of the substrate 110 and are electrically connected to the pixel array 120. At least one test pad 140 is located in the peripheral region 110b of the substrate 110 and is electrically connected to the pixel array 120. In this embodiment, the material of the substrate 110 may be glass, quartz, organic polymer, or an opaque/reflective material (eg, conductive material, metal, wafer, ceramic, etc.), or other applicable materials. . When the substrate 110 is made of a conductive material or a metal, the substrate 110 needs to have an insulating layer (not shown) to prevent short-circuiting of the components mounted on the substrate 110.

In this embodiment, the pixel array 120 includes a plurality of pixels arranged in an array. Structure 122. Each pixel structure 122 includes at least one active component 122a (eg, a thin film transistor) and at least one pixel electrode 122b electrically coupled to the active component 122a. The pixel structure 122 illustrated in FIG. 1 is exemplified by an active element 122a and a pixel electrode 122b. However, the invention is not limited to this, each pixel knot The number of active components included in the structure may be multiple; the number of pixel electrodes included in each pixel structure may be selectively multiple; the number of active components and the number of pixel electrodes in the same pixel structure may be the same or different. In short, the number of pixel electrodes and active components of each pixel structure, and the electrical connection between the pixel electrodes and the active components of each pixel structure can be appropriately designed according to actual needs.

In this embodiment, the pixel array 120 may further include multiple data lines. DL, a plurality of scanning lines SL, a driving circuit 150 (for example, a driving chip), and a flexible printed circuit (FPC) 160. The plurality of data lines DL are electrically connected to the corresponding pixel structure 122. In detail, each data line DL is electrically connected to the source of the corresponding plurality of active elements 122a. The plurality of scan lines SL are electrically connected to the corresponding pixel structure 122 and intersect the data line DL. In detail, each scan line SL is electrically connected to the gates of the corresponding plurality of active elements 122a, and the extending direction of the scan lines SL may be perpendicular to the extending direction of the data lines DL. The driving circuit 150 is located in the peripheral region 110b and between the pixel array 120 and the plurality of signal pads 130. The plurality of signal pads 130 can be electrically connected to the pixel array 120 through the driving circuit 150. The driving circuit 150 is electrically connected to at least one of the plurality of data lines DL and the plurality of scanning lines SL to drive the pixel array 120. In this embodiment, the driving circuit 150 can be electrically connected to the plurality of data lines DL and the plurality of scanning lines SL at the same time. However, the present invention is not limited thereto. In other embodiments, the driving circuit 150 may be electrically connected to the plurality of data lines DL or the plurality of scanning lines SL. The flexible circuit board 160 is for engaging with a plurality of signal pads 130. After the signal pad 130 is bonded to the flexible circuit board 160, the flexible circuit board 160 covers the plurality of signal pads 130 and is electrically connected to the signal pad 130.

The test pad 140 is located beside the signal pad 130. In this embodiment, the measurement The test pad 140 and the plurality of signal pads 130 may also be disposed on different two columns spaced apart from each other. The test pads 140 are selectively disposed at the lower left corner of the substrate 110. However, the present invention is not limited thereto, and the position at which the test pads 140 are disposed may depend on the actual layout of the element substrate 100 and the process requirements. In other embodiments, the test pads 140 may also be selectively disposed at the upper left corner, the upper right corner, the lower right corner of the substrate 110 or the sides of the substrate 110. In addition, the positional relationship between the test pad 140 and the plurality of signal pads 130 can also be other suitable designs other than that of FIG. 1, which will be exemplified in the following embodiments.

The test pad 140 is for the tester to input a test signal to the pixel array. 120 to test whether the function of the pixel array 120 is normal. In general, the tester electrically contacts the test pad 140 with the test signal by the naked eye and the hand to input the test signal to the pixel array 120. To enable the tester to easily perform the test actions described above, the test pads 140 are of comparable size. For example, the size of the test pads 140 is greater than the size of each of the signal pads 130. Furthermore, the area of each test pad 140 may be 1 to 10 times the area of each signal pad 130, but the invention is not limited thereto.

When the element substrate 100 is used as a component of the display panel, it is an alignment display The display substrate (eg, liquid crystal) in the panel, the component substrate 100 may further include an alignment film PI to cover the pixel array 120, the signal pad 130, and the test pad 140. It is worth mentioning that, since the test pad 140 has a special structural design, when using an alignment tool (for example, a roller and a cloth laid on the roller), it is performed on the alignment film PI. In the contact alignment process, even if the test pads 140 have a considerable size, the alignment film PI located at the edge or the center of the pixel array 120 can be uniformly aligned, and the display panel including the element substrate 100 is less likely to occur in the prior art. Poor alignment. The specific structure of the test pad 140 and its mechanism for improving the problem of poor alignment will be specifically described below with reference to the drawings.

2A is an enlarged schematic view showing a portion K of the element substrate of FIG. 1. Figure 2B is A schematic cross-sectional view of a portion of the element substrate according to the line A-A' of Fig. 2A. 2A and 2B, the test pad 140 includes a conductive layer 142 at the peripheral region 110b (shown in FIG. 2B), an insulating layer 144 covering the conductive layer 142, and a contact pattern layer 146 on the insulating layer 144. The conductive layer 142, the insulating layer 144, and the contact pattern layer 146 are sequentially stacked along the normal direction d1 of the bearing surface 110c of the substrate 110.

The test pad 140 receives the contact pattern layer 146 by using the conductive layer 142. The test signal is passed to the pixel array 120 (shown in Figure 1). In other words, the conductive layer 142 is electrically connected between the contact pattern layer 146 and the pixel array 120. After the contact pattern layer 146 receives the test signal, the test signal can be sequentially transferred to the pixel array 120 via the contact pattern layer 146 and the conductive layer 142. In this embodiment, in order to integrate the process of the test pad 140 with the process of the pixel array 120, the gate of the conductive layer 142 and the active component 122a of the pixel array 120 (shown in FIG. 1) may alternatively be The same film layer is formed, but the invention is not limited thereto. The conductive layer 142 is generally made of a metal material. However, the present invention is not limited thereto. According to other embodiments, the conductive layer 142 may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, and metal materials. NOx, or metal materials and other conductive materials Stack layers.

2C is a top plan view of the conductive layer 142 of the test pad of FIG. 2A. Referring to FIG. 2A, FIG. 2B and FIG. 2C, in the embodiment, the conductive layer 142 includes a body portion 142a (shown in FIG. 2C) and is electrically connected to the body portion 142a and the pixel array 120 (shown in FIG. 1). At least one bridge electrode 142b (shown in Figure 2C). The number of at least one bridging electrode 142b may be one or more. The width W1 of each of the bridge electrodes 142b in the direction d2 perpendicular to the normal direction d1 of the bearing surface 110c is smaller than the width W2 of the body portion 142a in the direction d2 perpendicular to the normal direction d1. Furthermore, the width W1 of each of the bridge electrodes 142b in the direction d2 perpendicular to the normal direction d1 of the bearing surface 110c is less than or equal to the width W3 of the signal pad 130 (drawn in FIG. 1) in the direction d2 (painted Figure 1). The body portion 142a overlaps the contact pattern layer 146 and the contact opening Hc. The body portion 142a may be in direct contact with the contact pattern layer 146. The bridge electrode 142b is electrically connected between the body portion 142a and the pixel array (shown in FIG. 1). The edge 146a of the contact pattern layer 146 (shown in Figure 2A) is located on the bridge electrode 142b. From another perspective, as shown in FIG. 2C, the conductive layer 142 can selectively have a plurality of openings 142c. The plurality of openings 142c are arranged in a ring structure. The body portion 142a of the conductive layer 142 is within a range surrounded by the plurality of openings 142c. Each of the bridge electrodes 142b is located outside the body portion 142a and between the adjacent two openings 142c and is in electrical contact with the body portion 142a.

Referring to FIGS. 2A and 2B, the insulating layer 144 has at least one contact opening Hc. The contact opening Hc exposes the body portion 142a of the conductive layer 142. The contact pattern layer 146 is filled in the contact opening Hc to be electrically connected to the body portion 142a of the conductive layer 142. In particular, the insulating layer 144 has at least one trench Hp. A portion of the contact pattern layer 146 is located within the trench Hp. As shown in FIG. 2B, the contact pattern layer 146 can shield the conductive layer 142 and beyond the body portion 142a of the conductive layer 142, that is, the contact pattern layer 146 completely shields the body portion 142a. Further, each of the trenches Hp has a first sidewall S1, a second sidewall S2 opposite to the first sidewall S1, and a bottom S3 connecting the first sidewall S1 and the second sidewall S2. The first side wall S1 is closer to the contact opening Hc than the second side wall S2. The contact pattern layer 146 extends outward from the contact opening Hc to cover the first sidewall S1 of the insulating layer 144 and at least partially cover the bottom S3 of the trench Hp, but the embodiment is not limited thereto, and the contact pattern layer 146 may also be completely Covering the bottom S3 of the groove Hp. In other words, the contact pattern layer 146 does not cover the second side wall S2 of each of the trenches Hp to partially expose the bottom portion S3 of each of the trenches Hp. The edge 146a of at least a portion of the contact pattern layer 146 is located within the trench Hp.

It is worth noting that, as shown in FIG. 2B, when the contact pattern layer 146 is insulated When the trench Hp of the layer 144 is extended such that a portion of the contact pattern layer 146 is located within the trench Hp, a portion of the contact pattern layer 146 is laid on the first sidewall S1 of the trench Hp to form a gentle slope. Thereby, when the alignment tool R is used to perform a contact alignment process on the alignment film PI (for example, the cloth 20 of the alignment tool R is rotated with the central axis of the roller 10 as a center of rotation; then, the alignment film PI and the cloth are made 20 contacting and pressing the alignment tool R; then, moving the component substrate 100 carrying the alignment film PI along a predetermined alignment direction d3, so that the alignment tool R first overlaps with the test pad 140 located in the peripheral region 110b, and then actively When the region 110a overlaps, the alignment tool R can follow the gentle slope with a steady downforce to the vicinity of the boundary between the active region 110a and the peripheral region 110b. Part of the alignment film PI and a portion of the alignment film PI near the center of the active region 110a are aligned. As a result, the alignment film PI on the edge of the pixel array 120 (shown in FIG. 1) (ie, the alignment film PI near the boundary between the active region 110a and the peripheral region 110b) and the alignment film PI near the center of the pixel array 120 (ie, close to each other) The alignment film PI) at the center of the active region 110a can have a similar anchoring force, so that the probability of occurrence of poor alignment or the severity of poor alignment can be reduced.

Please refer to FIG. 2B. In this embodiment, the test pad 140 and the drawing are integrated. The insulating layer 144 may selectively include a first insulating layer 144a and a second insulating layer 144b. The first insulating layer 144a is located on the conductive layer 142. The second insulating layer 144b is located on the first insulating layer 144a. The conductive layer 142, the first insulating layer 144a, the second insulating layer 144b, and the contact pattern layer 146 are sequentially stacked in a direction d1 away from the substrate 110. The fabrication of the first insulating layer 144a may be integrated with the fabrication of a gate insulating layer (not shown) of the active component 122a of the pixel array 120. In other words, the first insulating layer 144a is selectively the same film layer as the gate insulating layer between the gate and the channel of the active device 122a. The fabrication of the second insulating layer 144b can be integrated with the fabrication of a planar layer (not shown) between the pixel electrode 122b and the drain of the active device 122a. In other words, the second insulating layer 144b may selectively belong to the same film layer as the flat layer. It should be noted that the multilayer structure of the insulating layer 144 and the relationship between the multilayer structure and the gate insulating layer and the flat layer are used to illustrate the invention and are not intended to limit the present invention. In other embodiments, the insulating layer 144 does not have to be a multi-layer structure, and the relationship between the insulating layer 144 and the members on the active region 110a can be appropriately designed according to actual needs. In this embodiment, the first The edge layer 144a and the second insulating layer 144b are respectively patterned (for example, different etching processes) to form the trench Hp. However, the embodiment does not limit the first insulating layer 144a and the second insulating layer 144b. It can also be patterned simultaneously to form Hp.

In this embodiment, the material of the insulating layer 144 may be an inorganic material (for example: Cerium oxide, tantalum nitride, niobium oxynitride, or a stacked layer of at least two of the above materials, an organic material, or a combination thereof. The material of the contact pattern layer 146 includes a metal oxide such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide, or other suitable oxide, or at least The stacked layers of the two, but the invention is not limited thereto. In the present embodiment, the process of contacting the pattern layer 146 with the pixel electrode 122b of FIG. 1 can be selectively integrated. In other words, the contact pattern layer 146 may be formed of the same film layer as the pixel electrode 122b. However, the present invention is not limited thereto, and FIG. 3 is a top view of a pixel structure, a data line, and a scanning line of the element substrate according to another embodiment of the present invention. In the embodiment of FIG. 3, the pixel structure 122A further includes a common electrode 122c in addition to the active element 122a and the pixel electrode 122b. The branch 122c1 of the common electrode 122c and the branch 122b1 of the pixel electrode 122b are alternately arranged. The contact pattern layer 146 may also be formed by selectively forming the same film layer as the common electrode 122c or the common electrode 122c and the pixel electrode 122b. In the embodiment of FIG. 3, the common electrode 122c and the pixel electrode 122b are substantially coplanar. In short, the pixel structure 122A can be a pixel structure of an In-Plane Switching (IPS) mode. However, the present invention is not limited thereto. In other embodiments, the common electrode 122c and the pixel electrode 122b may not be coplanar. In short, the pixel structure can also be a pixel structure of the Fringe-Field Switching (FFS) mode, and The contact pattern layer 146 is selectively formed of the same film layer as one of the common electrode 122c and the largest distance between the pixel electrode 122b and the substrate 110.

Referring again to FIG. 2B, in the embodiment, the trench Hp is selectively permeable. The first and second insulating layers 144a, 144b are worn to expose the substrate 110. In other words, the first and second insulating layers 144a, 144b respectively have two openings that coincide, and the trench Hp is composed of two openings in which the first and second insulating layers 144a, 144b coincide. However, the present invention is not limited thereto, and FIG. 4 is a schematic cross-sectional view showing a part of the element substrate of another embodiment of the present invention. The element substrate 100A of FIG. 4 is similar to the element substrate 100 of FIG. 2B, and therefore the same or corresponding elements are denoted by the same or corresponding reference numerals. In the embodiment of FIG. 4, the first insulating layer 144aA may have no openings near the boundary between the active region 110a and the peripheral region 110b. The trench HpA may be constituted by a single opening of the second insulating layer 144b, and the trench HpA exposes the first insulating layer 144aA. The element substrate 100A has advantages and effects similar to those of the element substrate 100, and will not be repeated here.

Referring to FIG. 2A and FIG. 2C again, in the test pad 140, the number of at least one trench Hp may be plural. These grooves Hp may substantially constitute an annular structure to surround the contact opening Hc. The trench Hp may not substantially overlap the conductive layer 142. In other words, the trench Hp is directly above the opening 142c of the conductive layer 142. In the present embodiment, the sizes of the plurality of trenches Hp of the test pads 140 may be different. In detail, the plurality of trenches Hp located on the upper and lower sides of the body portion 142a of the conductive layer 142 have the same first area, and the plurality of trenches Hp located on the left and right sides of the body portion 142a of the conductive layer 142 have the same The second area, wherein the second area is larger than the first area. However, the type of the groove of the present invention is not limited to that shown in Fig. 2A. The type of groove can be seen as actual needs It depends. For example, FIG. 5 is a top plan view of a portion of a component substrate according to still another embodiment of the present invention. The element substrate 100C of FIG. 5 is similar to the element substrate 100 of FIG. 2A, and therefore the same or corresponding elements are denoted by the same or corresponding reference numerals. In the embodiment of FIG. 5, the plurality of grooves Hp of the test pad 140C may have the same size and uniformly surround the contact opening Hc.

6A is a top plan view showing a part of a component substrate according to still another embodiment of the present invention; Figure. Fig. 6B is a schematic cross-sectional view showing a part of the element substrate taken along the line D-D' of Fig. 6A. Referring to FIGS. 6A and 6B, the element substrate 100D is similar to the element substrate 100 of FIGS. 2A and 2B, and therefore the same or corresponding elements are denoted by the same or corresponding reference numerals. In the embodiment of FIGS. 6A and 6B, the conductive layer 142D may not have an opening 142c like the conductive layer 142 of FIG. 2C, and the conductive layer 142D may be a complete conductive pattern. The trench HpD may be a continuous annular trench to surround the contact opening Hc. The trench HpD exposes the conductive layer 142D. Similar to the embodiment of FIG. 2A and FIG. 2B, the first and second insulating layers 144a, 144b also have two openings that coincide with each other, and the continuous annular groove HpD may also be composed of the first and second insulating layers 144a, 144b. The two openings are coincident with each other. However, the present invention is not limited thereto, and FIG. 7 is a schematic cross-sectional view showing a part of the element substrate according to still another embodiment of the present invention. The element substrate 100E of FIG. 7 is similar to the element substrate 100D of FIGS. 6A and 6B, and therefore the same or corresponding elements are denoted by the same or corresponding reference numerals. In the embodiment of Figure 7, the trench HpE is also a continuous annular trench to surround the contact opening Hc. Unlike the trench HpD of FIGS. 6A and 6B, in the embodiment of FIG. 7, the first insulating layer 144aE may have no opening near the boundary between the active region 110a and the peripheral region 110b. The continuous annular groove HpE may be a second insulating layer A single opening of 144b is formed, and a continuous annular groove HpE may expose the first insulating layer 144aE. The element substrates 100D, 100E have similar advantages as the element substrate 100 and will not be repeated here.

FIG. 8 is a top plan view of a component substrate according to an embodiment of the present invention. Figure 8 The element substrate 100F is similar to the element substrate 100 of FIG. 1, and therefore the same or corresponding elements are denoted by the same or corresponding reference numerals. The element substrate 100F is different from the element substrate 100 of FIG. 1 in that the position of the test pad 140F of the element substrate 100F is different from the position of the test pad 140 of the element substrate 100. In detail, after the flexible circuit board 160 is bonded to the plurality of signal pads 130, the test pads 140F can be covered by a portion of the flexible circuit board 160 that extends beyond the signal pads 130. As a result, the user is less likely to perceive the setting of the test pad 140F, and contributes to an aesthetically pleasing appearance of the display panel including the element substrate 100F.

In summary, in the component substrate of an embodiment of the invention, the test pad The contact pattern layer extends toward the trench of the insulating layer such that a portion of the contact pattern layer is located in the trench of the insulating layer, and a portion of the contact pattern layer is laid on the sidewall of the trench to form a gentle slope. When a contact alignment process is performed on the alignment film laid on the test pad and the pixel array by using an alignment tool, the alignment tool can follow the gentle slope with a stable downforce to the vicinity of the active zone and the peripheral zone. Part of the alignment film and a portion of the alignment film near the center of the active region are aligned. As a result, the alignment films on the regions on the element substrate can have similar anchoring forces, thereby improving the poor alignment in the prior art.

Although the present invention has been disclosed above by way of example, it is not intended to limit the present invention. The scope of the present invention is defined by the scope of the appended claims, which are defined by the scope of the appended claims. quasi.

10‧‧‧Roller

20‧‧‧布毛

100‧‧‧ element substrate

110‧‧‧Substrate

110a‧‧‧active area

110b‧‧‧ surrounding area

110c‧‧‧ bearing surface

140‧‧‧Test pads

142‧‧‧ Conductive layer

142a‧‧‧ Body Department

142b‧‧‧Bridge electrode

144‧‧‧Insulation

144a‧‧‧first insulation

144b‧‧‧Second insulation

146‧‧‧Contact pattern layer

146a‧‧‧ edge

A-A’‧‧‧ cut line

Hc‧‧ contact opening

Hp‧‧‧ trench

D1‧‧‧ normal direction

d3‧‧‧Predetermined alignment direction

S1‧‧‧ first side wall

S2‧‧‧ second side wall

S3‧‧‧ bottom

R‧‧‧ Alignment tool

PI‧‧‧ alignment film

Claims (9)

An element substrate includes: a substrate having an active area and a peripheral area; a pixel array located in the active area of the substrate; a plurality of signal pads on the substrate and electrically connected to the pixel array And at least one test pad located in the peripheral region and electrically connected to the pixel array, wherein the test pad comprises: a conductive layer located in the peripheral region; an insulating layer covering the conductive layer, wherein the The insulating layer has at least one contact opening and at least one trench, the contact opening exposing the conductive layer; and a contact pattern layer on the insulating layer, wherein the contact pattern layer is electrically connected to the conductive layer through the contact opening Connected, and a portion of the contact pattern layer is located within the trench. The component substrate of claim 1, wherein the test pad has a size larger than a size of each of the signal pads. The component substrate of claim 1, further comprising: a flexible circuit board overlying the signal pads for electrically connecting to the signal pads, the flexible circuit board further covering the test pads . The component substrate of claim 1, wherein the insulating layer comprises: a first insulating layer on the conductive layer; A second insulating layer is disposed on the first insulating layer, wherein the at least one trench is an annular structure surrounding the contact opening, the trench extending through the second insulating layer to expose the first insulating layer. The device substrate of claim 1, wherein the conductive layer comprises: a body portion overlapping the contact pattern layer and the contact opening; and at least one bridge electrode electrically connected to the body portion and the drawing Between the arrays, wherein the number of the at least one trench is plural, the trenches do not substantially overlap the conductive layer, and the trenches substantially constitute an annular structure to surround the contact opening. The component substrate of claim 5, wherein the number of the at least one bridging electrode is plural, and the width of each of the bridging electrodes is smaller than a width of the body portion, wherein the insulating layer comprises: a first insulation a layer on the conductive layer; and a second insulating layer on the first insulating layer, wherein the trenches expose the first insulating layer or the substrate. The component substrate of claim 1, further comprising: an alignment film covering the pixel array, the signal pads, and the test pad. The element substrate of claim 1, wherein the pixel array comprises: a pixel electrode and a common electrode, wherein the contact pattern layer is formed by the same film layer as the pixel electrode or the common current, The material contacting the pattern layer includes transparency Metal oxide. A method for aligning an element substrate, comprising: providing the element substrate according to claim 1; forming an alignment film on the element substrate to cover the pixel array and the at least one test pad; and utilizing An alignment tool performs a contact alignment process on the alignment film, the alignment tool first overlapping the at least one test pad and overlapping the active region.