TW201533882A - Stacked flip chip package - Google Patents

Abstract

An interposer is utilized in a stacked flip chip package and is adapted to connect a first chip and a second chip. The interposer includes a first surface, a second surface opposite to the first surface and plural conductive vias which are disposed in the interposer and pass through the first surface and the second surface. A first heat dissipation metal layer is disposed on the first surface and a second heat dissipation metal layer is disposed on the second surface. The first heat dissipation metal layer and the second heat dissipation metal layer are electrically isolated from the conductive vias. On the first surface, the first heat dissipation metal layer is disposed between every two adjacent conductive vias. On the second surface, the second heat dissipation metal layer is disposed between every two adjacent conductive vias. The first chip is disposed on the first surface and the second chip is disposed on the second surface. The first chip and the second chip are electrically connected to one another by the conductive vias.

Description

Flip chip stack package

The present invention relates to a stacked package, and more particularly to a flip chip package that can improve the heat dissipation effect in a flip chip manner.

With the thinning of electronic products, the degree of integration of semiconductor wafers and the demand for high-density semiconductor packages have also increased. A stacked chip package, a system in package, can accommodate a plurality of wafers in a package to increase package density, and thus has been widely used in many electronic products in recent years. In semiconductor packaging technology, flip chip allows the contacts of the wafer to be arranged in an array, providing an excellent bonding between the high-battery wafer and the package substrate. These high-integration wafers and high-density package structures generate relatively more thermal energy during operation. Therefore, how to solve the heat dissipation problem of semiconductor packages has been an important issue.

In the heat dissipation method of the conventional semiconductor package, a heat sink is usually added outside the package. For example, a heat dissipation metal piece is disposed outside the package to meet the heat dissipation requirement. However, when the heat dissipation method is applied to the package structure of the stacked wafer, the bottom layer is used. The heat dissipation efficiency of the wafer is inferior to that of the top wafer.

One of the viewpoints of the present invention is to provide a flip chip stacked package, which directly forms a heat dissipation structure by using an interposer, and provides a heat dissipation path with low thermal resistance.

According to the above and other aspects of the present invention, a flip chip stacked package is provided, comprising: a package substrate, a first wafer, an interposer, and a second wafer. The package substrate has an inner surface and a corresponding outer surface. The inner surface has at least one inner contact, and the outer surface has at least one external contact, and the inner contact is electrically connected to the external contact. The first wafer has a first active surface and a corresponding first back surface. The first active surface has at least one first contact, and the first back has at least one second contact. The first contact and the second contact are electrically connected. The first wafer is attached to the inner surface with the first active surface such that the first contact is electrically connected to the inner contact. The interposer has a first bonding surface and a corresponding one of the second bonding surfaces. The interposer has at least one conductive via extending through the first bonding surface and the second bonding surface. The first bonding mask has a first heat dissipation metal layer, and the second layer The bonding mask has a second heat dissipation metal layer, wherein the first heat dissipation metal layer and the second heat dissipation metal layer are electrically isolated from the conductive via holes, and the first bonding surface of the interposer is bonded to the first back surface, and the conductive via holes are The second contact is electrically connected. The second wafer has a second active surface, the second active surface has at least one third contact, and the second wafer is attached to the second bonding surface by the second active surface, so that the third contact is electrically connected to the conductive via .

In one or more embodiments of the present invention, the second wafer further includes a second back surface corresponding to the second active surface, and the flip chip stacked package further includes a heat sink disposed on the second back surface, and the second heat dissipation metal Layer connection.

In one or more embodiments of the invention, the first bonding surface of the interposer is bonded to the first back surface such that the first heat dissipation metal layer is thermally conductively bonded to the first back surface.

In one or more embodiments of the present invention, the first wafer and the package substrate are flip-chip bonded, and a first underfill material is further included between the first active surface and the inner surface.

In one or more embodiments of the present invention, the second wafer and the interposer are covered The crystal is joined, and a second underfill material is further included between the second active surface and the second surface.

In one or more embodiments of the present invention, the flip chip package further includes a solder ball disposed on the external contact and electrically connected to the external contact.

In accordance with the above and other aspects of the present invention, a flip chip stacked package is provided comprising: an interposer, a first wafer, and a second wafer. The interposer has a first bonding surface and a corresponding one of the second bonding surfaces. The interposer has a plurality of conductive vias extending through the first bonding surface and the second bonding surface, and the first bonding surface has a first heat dissipation metal layer. The second bonding surface has a second heat dissipation metal layer, wherein the first bonding surface and the adjacent conductive vias respectively have a first heat dissipation metal layer and a second heat dissipation metal layer, and the first heat dissipation layer The metal layer and the second heat dissipation metal layer are electrically isolated from the conductive via holes, respectively. The first wafer has a first surface, the first surface has a plurality of first contacts, and the first wafer is attached to the first bonding surface by the first surface, so that the first contacts are electrically connected to the conductive vias, respectively, and The first surface is thermally conductively bonded to the first heat dissipation metal layer. The second wafer has a second surface, the second surface has a plurality of second contacts, and the second wafer is attached to the second bonding surface by the second surface, so that the second contacts are electrically connected to the conductive vias, respectively, and The second surface is thermally conductively bonded to the second heat dissipation metal layer.

In one or more embodiments of the present invention, the first wafer further has a third surface corresponding to the first surface, and the third surface has a plurality of third contacts, each of the third contacts respectively corresponding to the first One of the contacts is electrically connected, wherein the first wafer is bonded to the package substrate by a third surface, and the third contact is electrically connected to the package substrate.

In one or more embodiments of the present invention, the first wafer further has a third surface corresponding to the first surface, and the third surface has a plurality of third contacts, each of the third contacts respectively corresponding to the first One of the contacts is electrically connected, and the flip chip stacked package further includes: a second interposer, The third bonding surface has a plurality of first conductive vias extending through the third bonding surface and the fourth bonding surface, and the third bonding mask has a third heat dissipation metal layer. The bonding mask has a fourth heat dissipation metal layer, wherein the third heat dissipation metal layer and the fourth heat dissipation metal layer are electrically isolated from the first conductive via, and between the adjacent first conductive vias and on the third bonding surface The third heat dissipating metal layer has a fourth heat dissipating metal layer on the fourth bonding surface, and the first wafer is attached to the third bonding surface by the third surface, so that the third contact is electrically connected to the first conductive via hole respectively Connected, and the third surface is thermally conductively bonded to the third heat dissipation metal layer.

In one or more embodiments of the invention, the first wafer is bonded to a package substrate and the second wafer is bonded to another interposer.

According to the above and other aspects of the present invention, an interposer is provided for connecting a first wafer and a second wafer, the interposer comprising: a first bonding surface and a corresponding one of the second bonding surfaces; and a plurality of conductive vias a first bonding surface and a second bonding surface; a first heat dissipation metal layer disposed on the first bonding surface; and a second heat dissipation metal layer disposed on the second bonding surface. The first heat dissipation metal layer and the second heat dissipation metal layer are electrically isolated from the conductive via holes, and between the adjacent conductive via holes, have a first heat dissipation metal layer on the first bonding surface, and on the second bonding surface There is a second heat dissipation metal layer. The first wafer is disposed on the first bonding surface, and the second wafer is disposed on the second bonding surface, and the first wafer and the second wafer are electrically connected by the conductive via.

In one or more embodiments of the invention, the first wafer and the second wafer are thermally bonded to the interposer.

In the flip chip stack package of the present invention, an interposer is interposed between the stacked wafers, and a heat dissipating metal layer is formed on the interposer, and the heat dissipating structure can be directly formed by using the interposer to provide a heat dissipation path of the wafer with low thermal resistance. Thereby, the heat dissipation efficiency of the flip chip stack package can be significantly improved, and The structure is simple and can reduce manufacturing costs.

100‧‧‧Package substrate

100A‧‧‧ inner surface

100B‧‧‧ outer surface

102‧‧‧Internal points

104‧‧‧External points

122‧‧‧First heat sink metal layer

124‧‧‧Second heat dissipation metal layer

126‧‧‧ Conductive through hole

128‧‧‧Electrical bumps

130‧‧‧second chip

110‧‧‧First chip

110A‧‧‧First active surface

110B‧‧‧ first back

112‧‧‧First contact

114‧‧‧second junction

116‧‧‧Bottom filling materials

120‧‧‧Intermediary

120A‧‧‧first joint

120B‧‧‧Second joint

130A‧‧‧Second active surface

130B‧‧‧ second back

132‧‧‧ third joint

134‧‧‧ bottom material

136‧‧‧ solder balls

140‧‧‧ wafer

150‧‧‧Intermediary

160‧‧‧ Heat sink

162‧‧‧thermal adhesive

1 to FIG. 4 are schematic cross-sectional views showing respective steps of a method for fabricating a flip chip package according to an embodiment of the invention.

FIG. 5 is a cross-sectional view showing a flip chip stacked package in accordance with another embodiment of the present invention.

6 is a cross-sectional view showing a flip chip stacked package in accordance with still another embodiment of the present invention.

7 is a top plan view of an interposer of a flip chip stacked package in accordance with an embodiment of the invention.

FIG. 8 is a top plan view of an interposer of a flip chip stacked package according to an embodiment of the invention.

The advantages, spirits and features of the present invention will be described and discussed in detail by reference to the accompanying drawings. It is to be noted that, in order to make the invention more comprehensible, the appended drawings are only schematic representations, and the related dimensions are not shown in actual scale.

For the sake of the advantages and spirit of the invention, the spirit and the features may be more easily and clearly understood, and the detailed description and discussion will be made by way of example and with reference to the accompanying drawings. It is noted that the embodiments are merely representative embodiments of the present invention, and the specific methods, devices, conditions, materials, and the like are not intended to limit the invention or the corresponding embodiments.

Referring to FIG. 1 to FIG. 4 , FIG. 1 to FIG. 4 are schematic cross-sectional views showing respective steps of a method for manufacturing a flip chip package according to an embodiment of the invention. The flip chip stack package of the invention The manufacturing method includes the following steps: First, referring to FIG. 1 , a package substrate 100 is provided. The package substrate 100 has an inner surface 100A and a corresponding outer surface 100B. The inner surface 100A has a plurality of inner contacts 102 and an outer surface. The 100B has a plurality of external contacts 104, and each of the internal contacts 102 is electrically connected to one of the external contacts 104, respectively. In detail, the package substrate 100 may be a printed circuit substrate (PCB substrate), such as a plurality of layers of an epoxy insulating layer and a patterned copper foil, which are alternately laminated. A conductive via or a conductive blind via connects the patterned copper foil layers. Therefore, the internal contact 102, such as a bonding pad, can be electrically connected to the external contact 104, such as a solder ball pad, by patterning a copper foil layer, a conductive via, and a conductive via.

Referring to FIG. 2, a flip chip process is then performed to bond the first wafer 110 to the package substrate 100 in a flip chip manner. The first wafer 110 has a first active surface 110A and a corresponding first back surface 110B. The first active surface 110A has a first contact 112, and the first back surface 110B has a second contact 114. The first contact 112 and the first The first contact 110 is electrically connected to the inner surface 100A, so that the first contact 112 is electrically connected to the inner contact 102. In detail, the first wafer 110 may form a plurality of bonding pads (not shown) on the first active surface 110A, such as arrays, and respectively form conductive bumps thereon. To form the first contact 112 in FIG. The second contact 114 on the first back surface 110B, for example, the solder pad as described above, is electrically connected to the first contact 112 through a metal interconnect in the first wafer 110. In order to prevent the thermal stress caused by the difference in thermal expansion coefficient between the wafer and the package substrate, affecting the reliability of the first contact 112 (conductive bump), it is preferable to perform an under-filling step and fill in a The underfill material 116 is between the first wafer 110 and the package substrate 100 to protect the conductive bumps.

Referring to FIG. 3, bonding of the interposer 120 to the first wafer 110 is then performed. The interposer 120 has a first bonding surface 120A and a corresponding one of the second bonding surfaces 120B. The interposer 120 has at least one conductive via 126 extending through the first bonding surface 120A and the second bonding surface 120B. The first bonding surface 120A has a first heat dissipation metal layer 122, and the second bonding surface 120B has a second heat dissipation metal layer 124. The first heat dissipation metal layer 122 and the second heat dissipation metal layer 124 are electrically isolated from the conductive via 126. . The first bonding surface 120A of the interposer 120 is in contact with the first back surface 110B, and the conductive via 126 is electrically connected to the second contact 114. In detail, the material of the interposer 120 is, for example, germanium or other semiconductor or insulating material, and preferably has a thermal expansion coefficient similar to that of the wafer. The conductive via 126 can form a conductive via 126 by using a Through Silicon Via (TSV). For example, a plurality of through holes are formed in the interposer 120, and then filled with a conductive material, such as a metal material, including copper. Aluminum, tungsten, titanium, cobalt, chromium, combinations thereof, etc., to form conductive vias 126. The method in which the through holes are formed includes lithography etching, and the method of filling the conductive material includes physical vapor deposition (PVD), plating, and the like. The first heat dissipation metal layer 122 and the second heat dissipation metal layer 124 may be formed by electroplating, such as copper or iron-nickel alloy, or other metal materials, preferably metal materials having high thermal conductivity. The conductive via 126 is electrically connected to the second contact 114 of the first wafer 110 by the conductive bumps 128. Similarly, an underfilling may be performed to fill an underfill material 118 between the first wafer 110 and the interposer 120 to protect the conductive bumps 128.

Referring to FIG. 4, the second wafer 130 is then stacked on the interposer 120. The second wafer 130 has a second active surface 130A, the second active surface 130A has at least one third contact 132, and the second wafer 130 is attached to the second surface 120B with the second active surface 130A such that the third contact 132 It is electrically connected to the conductive through hole 126. In detail, the second wafer 130 is on the second active surface A plurality of bonding pads (not shown) are formed on the 130A, for example, arranged in an array, and conductive bumps are respectively formed thereon to form a third contact 132 in FIG. Similarly, an under-filling process may be performed to fill an underfill material 134 between the second wafer 130 and the interposer 120 to protect the conductive bumps. The flip chip stack package of the present invention further includes a solder ball 136 disposed on the external contact 104 and electrically connected to the external contact 104 to electrically connect the flip chip stack to the external printed circuit board (or the motherboard).

It is worth mentioning that the underfill material 118, 134 is preferably a material having better thermal conductivity, whereby the first bonding surface 120A of the interposer 120 can be thermally conductively bonded to the first back surface 110B of the first wafer 110, that is, A heat dissipating metal layer 122 is thermally conductively bonded to the first back surface 110B of the first wafer 110. Likewise, the second heat sink metal layer 124 is thermally conductively bonded to the second active surface 130A of the second wafer 130. Therefore, the heat generated by the first wafer 110 and the second wafer 130 during operation may be dissipated by the first heat dissipation metal layer 122 of the interposer 120 and the second heat dissipation metal layer 124.

Please refer to FIG. 7 simultaneously. FIG. 7 is a schematic top view of an interposer of a flip chip stacked package according to an embodiment of the invention. In the above embodiment, the first heat dissipation metal layer 122 and the second heat dissipation metal layer 124 in the interposer 120 may be arranged as shown in FIG. The second heat dissipation metal layer 124 is disposed on the periphery of the interposer 120 at an appropriate distance from the conductive via 126, and the first heat dissipation metal layer 122 is also disposed. Preferably, the first heat dissipation metal layer 122 may partially overlap the vertical projection of the first wafer 110 on the interposer 120, that is, the underfill material 118 may connect the first wafer 110 and the first heat dissipation metal layer 122 to Heat conduction. Similarly, the second heat dissipation metal layer 124 may partially overlap the vertical projection of the second wafer 130 on the interposer 120, that is, the underfill material 134 may connect the second wafer 130 and the second heat dissipation metal layer 124 to facilitate heat conduction. .

Please refer to FIG. 8 , which illustrates a flip chip stacking according to an embodiment of the invention. A top view of the interposer of the package. In the above embodiment, the first heat dissipation metal layer 122 and the second heat dissipation metal layer 124 in the interposer 120 may be arranged as shown in FIG. The second heat dissipation metal layer 124 is disposed on the entire surface of the interposer 120 (the second bonding surface 120B), and is spaced apart from each of the conductive vias 126 to form electrical isolation, and the first heat dissipation metal layer 122 is disposed. . Thereby, the first wafer 110 or the second wafer 130 is connected to the first heat dissipation metal layer 122 through the underfill materials 118, 134. The area of the second heat dissipation metal layer 124 is larger, and the heat dissipation effect can be further improved.

Referring to FIG. 5, FIG. 5 is a cross-sectional view showing a flip chip stacked package according to another embodiment of the present invention. Although the above embodiment uses only a stack of two wafers as an example, it is known to those skilled in the art that a plurality of wafers can be stacked according to actual needs. Taking FIG. 5 as an example, the wafer 110, the interposer 120, the wafer 140, the interposer 150, and the wafer 130 are sequentially stacked on the package substrate 100. The structure and the bonding manner of the wafer 110, the interposer 120, and the wafer 130 are similar to those of the above embodiment, and are not described herein again. As for the structure of the wafer 140, similar to the wafer 110, the wafer 140 is bonded to the interposer 120 in a manner similar to the manner in which the wafer 110 is bonded to the package substrate 100; the wafer 140 is bonded to the interposer 150 in a manner similar to the manner in which the wafer 110 is bonded to the interposer 120. , will not repeat them here. The structure of the interposer 150 is similar to that of the interposer 120. The manner in which the interposer 150 is bonded to the wafer 140 and the wafer 130 is similar to that of the wafer 110 and the wafer 130 in the above embodiment, and details are not described herein.

Please refer to FIG. 6. FIG. 6 is a cross-sectional view showing a flip chip stacked package according to still another embodiment of the present invention. In one or more embodiments of the present invention, the second wafer 130 further includes a second back surface 130B corresponding to the second active surface 130A, and the flip chip package further includes a heat sink 160 disposed on the second back surface 130B, and Connected to the second heat dissipation metal layer 124. The heat sink 160 can be bonded to the second back surface 130B and the second heat dissipation metal layer 124 through the heat conductive adhesive 162. In addition to providing protection for the second wafer 130, it can also contribute to heat dissipation of the second wafer 130, the interposer 120, and increase the heat dissipation performance of the integrated flip chip package. The structure and process of other parts in this embodiment are similar to those in the embodiments of FIG. 1 to FIG. 4, and thus are not described herein again.

In summary, in the flip chip stack package of the present invention, in the stacked wafer, an interposer is interposed between every two adjacent wafers, and a heat dissipating metal layer is formed on the interposer and thermally conductive with the adjacent wafer. Bonding, the wafer can directly form a heat dissipation structure by using an interposer, and provide a heat dissipation path for the low thermal resistance of the wafer. Thereby, the heat dissipation efficiency of the flip chip stack package can be significantly improved, and the structure is simple, and the manufacturing cost can be reduced.

The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed. The present invention has been disclosed in the above embodiments, and is not intended to limit the present invention. Any one skilled in the art can make various modifications and retouchings without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100‧‧‧Package substrate

100A‧‧‧ inner surface

100B‧‧‧ outer surface

102‧‧‧Internal points

104‧‧‧External points

110‧‧‧First chip

110A‧‧‧First active surface

110B‧‧‧ first back

112‧‧‧First contact

114‧‧‧second junction

116‧‧‧Bottom filling materials

120A‧‧‧first joint

120B‧‧‧Second joint

122‧‧‧First heat sink metal layer

124‧‧‧Second heat dissipation metal layer

126‧‧‧ Conductive through hole

128‧‧‧Electrical bumps

130‧‧‧second chip

130A‧‧‧Second active surface

130B‧‧‧ second back

132‧‧‧ third joint

134‧‧‧ bottom material

120‧‧‧Intermediary

136‧‧‧ solder balls

Claims (12)

A flip chip stacked package comprising: a package substrate having an inner surface and a corresponding outer surface, the inner surface having at least one inner contact, the outer surface having at least one external contact, the inner contact and the outer contact Electrically connecting; a first wafer having a first active surface and a corresponding first back surface, the first active surface having at least one first contact, the first back having at least one second contact, the first a first contact is electrically connected to the second contact, the first active surface is attached to the inner surface, such that the first contact is electrically connected to the inner contact; and an interposer has a first bonding surface and a corresponding one of the second bonding surfaces, the interposer having at least one conductive through hole penetrating the first bonding surface and the second bonding surface, the first bonding mask having a first heat dissipation metal layer, The second bonding mask has a second heat dissipation metal layer, wherein the first heat dissipation metal layer and the second heat dissipation metal layer are electrically isolated from the conductive via hole, and the first bonding surface of the interposer is pasted with the first back surface And make the conductive through hole and the second a second electrically conductive surface having a second active surface, the second active surface having at least one third contact, the second wafer being attached to the second bonding surface by the second active surface The third contact is electrically connected to the conductive via. The flip chip stack package of claim 1, wherein the second wafer further comprises a second back surface corresponding to the second active surface, the flip chip stack package further comprising a heat sink disposed on the second back surface, and Connected to the second heat dissipation metal layer. The flip chip stack package of claim 1, wherein the first bonding surface of the interposer is bonded to the first back surface such that the first heat dissipation metal layer is thermally conductively bonded to the first back surface. The flip-chip stacked package of claim 1, wherein the first wafer and the package substrate are flip-chip bonded, and a first underfill material is further included between the first active surface and the inner surface. The flip chip package of claim 1, wherein the second wafer and the interposer are flip-chip bonded, and the second active surface and the second bonding surface further comprise a second underfill material. . The flip chip package of claim 1, further comprising a solder ball disposed on the external contact and electrically connected to the external contact. A flip chip stacked package includes: an interposer having a first bonding surface and a corresponding one of the second bonding surfaces, the interposer having a plurality of conductive vias extending through the first bonding surface and the second bonding surface, The first bonding surface has a first heat dissipation metal layer, and the second bonding surface has a second heat dissipation metal layer, wherein the first bonding surface and the second bonding surface are adjacent to each of the conductive through holes The first heat dissipation metal layer and the second heat dissipation metal layer, and the first heat dissipation metal layer and the second heat dissipation metal layer are electrically isolated from the conductive via hole respectively; a first wafer has a first surface, The first surface has a plurality of first contacts, and the first surface is attached to the first bonding surface by the first surface, so that the first contacts are electrically connected to the conductive vias respectively, and the The first surface is thermally conductively bonded to the first heat dissipation metal layer; and a second wafer has a second surface having a plurality of second contacts, the second wafer being attached to the second surface The second joint surface, the second joints Respectively, with the plurality of conductive vias is electrically connected, and the second surface and the second heat dissipation metal layer thermally bonding. The flip chip stacked package of claim 7, wherein the first wafer further has a third surface corresponding to the first surface, and the third surface has a plurality of third contacts, each of the third connections point Each of the first contacts is electrically connected to one of the first contacts, wherein the first surface is bonded to the package substrate by a flip chip, and the third contacts are electrically connected to the package substrate. Sexual connection. The flip chip stacked package of claim 7, wherein the first wafer further has a third surface corresponding to the first surface, and the third surface has a plurality of third contacts, each of the third connections The flip chip is further electrically connected to one of the corresponding first contacts, and the flip chip package further includes: a second interposer having a third bonding surface and a corresponding one of the fourth bonding surfaces, the interposer Having a plurality of first conductive vias extending through the third bonding surface and the fourth bonding surface, the third bonding mask has a third heat dissipation metal layer, and the fourth bonding mask has a fourth heat dissipation metal layer, wherein the The third heat dissipation metal layer and the fourth heat dissipation metal layer are electrically isolated from the first conductive vias, and between the adjacent first conductive vias, the third heat dissipation metal is disposed on the third bonding surface The layer has a fourth heat dissipation metal layer on the fourth bonding surface, and the first wafer is attached to the third bonding surface by the third surface, so that the third contacts are respectively associated with the first conductive layers The through hole is electrically connected, and the third surface and the third heat dissipation metal layer are guided Thermal joint. The flip chip package of claim 7, wherein the first wafer is bonded to a package substrate and the second wafer is bonded to another interposer. An interposer for connecting a first wafer and a second wafer, the interposer comprising: a first bonding surface and a corresponding one of the second bonding surfaces; the plurality of conductive vias penetrating the first bonding surface and the first a first bonding surface; a first heat dissipation metal layer disposed on the first bonding surface; and a second heat dissipation metal layer disposed on the second bonding surface, wherein the first heat dissipation metal layer and the second heat dissipation metal layer The conductive vias are electrically isolated, and the adjacent conductive vias are adjacent Having the first heat dissipating metal layer on the first bonding surface and the second heat dissipating metal layer on the second bonding surface; wherein the first wafer is disposed on the first bonding surface, and the second wafer is disposed The first wafer and the second wafer are electrically connected by the conductive via holes on the second bonding surface. The interposer of claim 11, wherein the first wafer and the second wafer are thermally conductively bonded to the interposer.