TW201534058A - Spread spectrum clock generator and method for generating spread spectrum clock signal - Google Patents

Abstract

A spread spectrum clock generator for generating a spread spectrum clock signal is provided. The spread spectrum clock generator includes a phase-locked loop system and a random walk modulator. The random walk modulator generates a modulating signal according to a random walk model. Then, the phase-locked loop system generates a clock signal with spread spectrum in response to the modulating signal. A method for generating the spread spectrum clock signal using the spread spectrum clock generator is also provided.

Description

Spread spectrum clock generator and spread spectrum clock signal generation method

The present invention relates to a clock generator and a clock signal generating method, and more particularly to a spread spectrum based on a phase-locked loop system (PLL system). Clock generator and spread spectrum clock signal generation method.

In today's digital circuits, clock generators for generating accurate clock signals are extremely important, where the clock generator is typically implemented by a highly integrated phase-locked loop circuit. In high-speed data transmission applications, the clock frequency requirements are also higher; however, high-frequency signals are often accompanied by severe electromagnetic interference (EMI). In general, the electric field strength that causes electromagnetic interference is mainly concentrated at the center frequency, and electromagnetic interference may be interrupted, hindering or reducing the performance of the circuit itself and other circuits. In addition, electromagnetic interference may also have unpredictable effects on human health.

Therefore, in order to solve the above-mentioned electromagnetic interference problem, a new clock generator and a new clock signal generation method are proposed to reduce electromagnetic interference, and the main purpose of the present invention is developed.

The invention provides a clock generator and a pulse signal generating method for reducing electromagnetic interference.

In order to achieve the above advantages or other advantages, an embodiment of the present invention provides a spread spectrum clock generator comprising: a random random number modulator and a phase locked loop system. A random random number modulator is used to generate a modulated signal according to a random random number model. The phase-locked loop system is connected to a random random number modulator for receiving the modulated signal and generating a spread spectrum clock signal according to the modulated signal.

The invention further provides a spread spectrum clock generator, comprising: a phase frequency detector, a charge pump, a voltage controlled oscillator, a frequency divider and a random random number modulator. The phase frequency detector is configured to receive and compare the reference clock signal and the feedback signal, and generate a control signal according to a phase difference between the reference clock signal and the feedback signal. The charge pump is connected to the phase frequency detector for generating a control voltage in response to a control signal output by the phase frequency detector. The voltage controlled oscillator is connected to the charge pump for generating a clock signal according to a control voltage output by the charge pump. The frequency divider is connected to the voltage controlled oscillator and the phase frequency detector for receiving the clock signal output by the voltage controlled oscillator, and processing the clock signal in a down conversion manner according to the frequency divisor to generate the feedback signal. Number and output the feedback signal to the phase frequency detector. A random random number modulator is connected to the frequency divider for modulating the frequency divisor according to the modulation signal generated by the random random number model.

The invention further provides a method for generating a spread-spectrum clock signal by a clock generator, comprising: generating a modulation signal according to a random random number model; a phase-locked loop system for outputting a modulated signal to a clock generator; and a phase-locked loop The system generates a spread spectrum clock signal in response to the modulated signal.

In summary, the present invention employs a spread spectrum technique to overcome the electromagnetic interference problem; in particular, the present invention uses a random random number model to modulate the clock signal. Therefore, the electric field strength is not concentrated in a center frequency or a small frequency range. Conversely, in the present invention, the electric field intensity can be uniformly dispersed in the spectrum without causing a large frequency hopping or frequency attenuating phenomenon.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1‧‧‧ phase-locked loop system

10‧‧‧ Spread spectrum clock generator

11‧‧‧ phase frequency detector

12‧‧‧Charging pump

13‧‧‧ Loop Filter

14‧‧‧Voltage Controlled Oscillator

15‧‧‧Delephone

16‧‧‧ phase interpolator

2‧‧‧ Random random number modulator

31‧‧‧Binary pseudo-noise generator

32, 33, 34‧‧‧ squares

41‧‧‧Linear feedback shift register

42‧‧‧Brown counter

43‧‧‧D type trigger

61, 62, 63, 64, 65, 66, 67 ‧ ‧ steps

F _out ‧‧‧ clock signal

F _ref ‧‧‧Reference clock signal

F _fb ‧‧‧Return signal

V _ctrl ‧‧‧ control voltage

S ₁ , S ₂ ‧‧ ‧ switch

Up, Dn‧‧‧ control signals

V _ctrl ‧‧‧ control voltage

Clk‧‧‧ clock

PFD‧‧‧ phase frequency detector

CP‧‧‧Charging pump

LF‧‧‧ loop filter

VCO‧‧‧Voltage Controlled Oscillator

FD‧‧‧Densator

LFSR‧‧·linear feedback shift register

Q, D‧‧‧ signal end

1 is a simplified schematic diagram of a spread spectrum clock generator based on a phase locked loop system in accordance with an embodiment of the present invention.

2 is a schematic diagram of the spread spectrum clock generator circuit shown in FIG. 1.

FIG. 3 is a schematic diagram of the main operation principle of the random random number modulator of the present invention.

4 is a schematic diagram of a random random number modulator in the spread spectrum clock generator shown in FIGS.

5A-5C are schematic diagrams of a spread spectrum clock generator circuit according to another embodiment of the present invention.

FIG. 6 is a schematic flow chart of a method for generating a clock signal according to an embodiment of the present invention.

When the electric filed strength is concentrated at a specific center frequency or a small frequency range, electromagnetic interference (EMI) phenomenon may occur. Therefore, in order to reduce the influence of electromagnetic interference, the present invention utilizes a spread spectrum technique to modulate a clock signal, for example, to reduce a spectral peak or to expand the shape of a flat spread spectrum. However, it should be specifically noted here that the clock signal should not be over-spread so that it exceeds an acceptable tolerance.

1 is a simplified schematic diagram of a spread spectrum clock generator based on a phase-locked loop system (PLL system) according to an embodiment of the present invention. In the present embodiment, the spread spectrum clock generator 10 includes, but is not limited to, a phase locked loop system 1 and a random walk modulator 2. The random random number modulator 2 is used to generate a modulated signal according to a random walk model. The modulation signal is used to modulate at least one signal in the phase-locked loop system 1 such that the clock signal F _out generated by the phase-locked loop system 1 is tunable to have a spread spectrum characteristic.

2 is a schematic diagram of the spread spectrum clock generator circuit shown in FIG. 1. The phase locked loop system 1 includes a phase-frequency detector (PFD) 11, a charge pump (CP) 12, a loop filter (LF) 13, and a voltage-controlled oscillator (voltage-controlled). Oscillator, VCO) 14 and frequency divider (FD) 15. The phase frequency detector 11, the charge pump 12, the loop filter 13, and the voltage controlled oscillator 14 are connected in series. The connection between any two of the above elements is not limited to electrical connection; that is, the connection between any two of the above elements can be achieved by any type of direct or indirect signal transmission. The frequency divider 15 is located on a feedback path from the voltage controlled oscillator 14 to the phase frequency detector 11. As shown in FIG. 2, the spread spectrum clock generator 10 further includes a random random number modulator 2.

The phase frequency detector 11 can be implemented by a digital circuit. The phase frequency detector 11 is configured to receive and compare a reference clock F _ref and a feedback signal F _fb according to a phase between the reference clock signal F _ref and the feedback signal F _fb or The frequency difference generates a control signal Up or Dn; wherein the feedback signal F _fb is output from the frequency divider 15. For example, if the reference clock signal F _ref leads the feedback signal F _fb , the phase frequency detector 11 outputs a control signal Up. On the other hand, if the feedback signal F _fb leads the reference clock signal F _ref , the phase frequency detector 11 outputs the control signal Dn. Control signals Up and Dn corresponding to the switch S ₁ is controlled and S _2, and further directing current flow into or out (i.e., charging or discharging) within the loop filter capacitor 13 to establish a high level or low level of the control voltage V _ctrl. In each cycle, the time when the switch S ₁ or S ₂ is turned on is proportional to the phase difference between the reference clock signal F _ref and the feedback signal F _fb and is determined by the corresponding control signal Up or Dn . Therefore, the charge/discharge amount of the charge is related to the phase/frequency difference between the reference clock signal F _ref and the feedback signal F _fb . Subsequently, a loop filter 13 (typically a low pass filter) filters out the high frequency portion of the control voltage V _ctrl to reduce jitter, thereby providing a stable control voltage V _ctrl to the voltage controlled oscillator 14. Although the loop filter 13 is exemplified by a second-order non-active loop filter in FIG. 2, the present invention does not limit the order or type of the loop filter 13. Finally, a stable control voltage V _{ctrl is} used to drive the voltage controlled oscillator 14 to generate a clock signal F _{out having} a particular frequency. In another embodiment, the loop filter 13 can be integrated into the charge pump 12, that is, the loop filter 13 and the charge pump 12 are a single integrated component rather than two separate components. Moreover, in another embodiment, the charge pump 12 can also be integrated into the phase frequency detector 11.

Before the feedback signal F _fb is compared with the reference clock signal F _ref , the frequency divider 15 is used to process the clock signal F _out in a down-conversion manner to generate the feedback signal F _fb . If the clock signal F _out is detected to have a phase drift, the phase frequency detector 11 can react in time, so that the spread spectrum clock generator 10 can provide a stable clock signal F _{out in time} . In an embodiment, the frequency divider 15 may be an integer divider; and after the down conversion process, the frequency of the feedback signal F _fb will be 1/N of the frequency of the clock signal F _out .

In order to make the clock signal _Fout output by the spread spectrum clock generator 10 have a spread spectrum characteristic, in the present invention, the random random number modulator 2 is introduced to the spread spectrum clock generator 10 for dynamically adjusting the frequency conversion. Rate divisor N. In an embodiment, the random random number modulator 2 may be a digital circuit for generating a modulated signal (eg, a one-dimensional random random number sequence) to modulate the frequency divisor N. For example, the one-dimensional random random number sequence {S _n } may be {-1, -1, 1, 1, 1, 1, 1, 1, -1, 1, ...}, where one dimension Each random random number in the random random number sequence {S _n } is +1 or -1. In another random random number sequence, the random random number may be other positive/negative integers having the same absolute value. Correspondingly, the frequency divisor N _i (i is an integer) generated by the frequency divider 15 based on the timing of the clock pulse clk is adjusted to {N ₀ -1, N ₁ -1, N ₂ +1, N ₃ +1, N ₄ +1, N ₅ +1, N ₆ +1, N ₇ +1, N ₈ -1, N ₉ +1, ....}, where N ₀ is The initial frequency divisor produced by the frequency converter 15. The main operating principle of the random random number modulator 2 is shown in Fig. 3. First, a binary pseudo noise generator 31 generates a pseudo random number; wherein each virtual random number can be 0 or 1, and the two virtual random numbers 0 or 1 are generated. The probability is the same (ie 50%). If the virtual random number is 1 (block 32), the frequency divisor of the frequency divider 15 is increased by a certain smaller value, such as 1 (block 33). Conversely, if the virtual random number is 0 (block 32), the frequency divisor is reduced by a certain smaller value, such as 1 (block 34). In summary, the frequency divider 15 is configured to dynamically adjust the frequency divisor N in response to the random random number sequence generated by the random random number modulator 2.

4 is a schematic diagram of a random random number modulator in a spread spectrum clock generator. In the present embodiment, the binary pseudo noise generator 31 is implemented by a linear feedback shift register (LFSR) 41 for providing a virtual random random number. The output value of the brownian counter 42 is latched in a D flip-flop 43. If the virtual random number is 0, the value latched in the D-type flip-flop 43 will be reduced by the Brown counter 42 by a certain smaller value, such as one. If the virtual random number is 1, the value latched in the D-type flip-flop 43 will be increased by the Brown counter 42 by the same value, for example 1. It should be noted here that the circuit of the random random number modulator 2 shown in FIG. 4 is only an example and is not intended to limit the present invention.

Compared to the conventional statistical random number sequence, there is a small deviation between two consecutive frequency divisors generated according to the random random number model. In addition, according to the random random number model, since the probability of generating random random numbers with positive and negative numbers is the same, each value in a certain integer set will be selected after a certain number of times. Therefore, the frequency of the feedback signal F _fb is only slightly changed and the electric field intensity can be uniformly dispersed in the spectrum with time without causing a large frequency hopping or frequency attenuation phenomenon. Therefore, the frequency of the clock signal F _out is correspondingly modulated over time by the operation of the phase frequency detector 11, the charge pump 12, the loop filter 13, and the voltage controlled oscillator 14, so that the peaks follow Spreading frequency is reduced. The upper boundary and the lower boundary may be set by the frequency divisor N such that the frequency of the clock signal F _out may vary within an allowable range; wherein the upper and lower boundaries may be according to system standards or specifications Make settings.

In addition to being connected to the frequency divider 15, in other embodiments, the random random number modulator 2 can also be coupled to other components of the phase locked loop system 1. 5A-5C are schematic diagrams of a spread spectrum clock generator circuit according to another embodiment of the present invention. As shown in FIG. 5A, in one embodiment, random random number modulator 2 is coupled to voltage controlled oscillator 14 and used to adjust the input signal of voltage controlled oscillator 14. As shown in FIG. 5B, in an embodiment, the random random number modulator 2 is used to establish an appropriate output phase with a phase interpolator 16; wherein the phase interpolator 16 is disposed in the voltage controlled oscillator 14. Between the frequency divider 15 and the frequency divider 15. As shown in FIG. 5C, in an embodiment, the random random number modulator 2 is used to adjust the reference clock signal F _ref to be sent to the phase frequency detector 11. In summary, by introducing the random random number modulator 2 to the spread spectrum clock generator 10, the clock signal F _out generated by the voltage controlled oscillator 14 can be gradually adjusted, thereby making the clock signal F _out With spread spectrum characteristics.

In addition, the structure of the phase-locked loop system 1 shown in FIG. 2 is merely an example, and is not intended to define the structure of the phase-locked loop system 1. In fact, there are a variety of phase-locked loop systems with different circuit configurations that can be applied to the spread spectrum clock generator 10 of the present invention; For example, a linear phase-locked loop, a digital phase-locked loop (DPLL), and an all-digital phase-locked loop (ADPLL). Variations and modifications of the phase locked loop system 1 can be derived from the description in this specification as those skilled in the art will not be described herein.

The present invention further provides a method for generating a spread spectrum clock signal. The method mainly includes, but is not limited to, the following steps: generating a modulated signal according to a random random number model; and generating a spread spectrum clock signal according to the modulated signal. The following is a detailed description of the above steps.

FIG. 6 is a schematic flow chart of a method for generating a clock signal according to an embodiment of the present invention. First, the reference clock signal and the feedback signal are received and compared, and a control signal is generated based on the phase/or frequency difference between the reference clock signal and the feedback signal (step 61). Then, a control voltage is generated in response to the control signal (step 62). Then, a clock signal is generated based on the level of the control voltage (step 63). Then, the current pulse signal is output (step 64). In addition, in order to maintain the frequency of the clock signal within an acceptable tolerance range, before the two signals are compared in step 61, the clock signal may be processed in a down conversion manner according to the frequency divisor to generate a feedback signal. (Step 65). Moreover, prior to downconversion, a modulated signal can be generated based on the random random number model (step 66) to modulate the frequency divisor based on the modulated signal (step 67).

The modulated signal can be a random random number sequence, and each random random number in the random random number sequence can be generated or triggered according to the timing of the clock pulse. The process of adjusting the frequency divisor according to the random random number sequence may include the steps of: providing a random random number sequence according to Brownian motion, wherein each random random number in the random random number sequence may be selected from two a positive/negative integer of the same absolute value, and the probability that the two positive/negative integers having the same absolute value are selected is the same; then, if the selected random random number is a positive integer, the new frequency divisor can be added This absolute value is derived from the previous frequency divisor; or, if the selected random random number is a negative integer, the new frequency divisor can be subtracted from this absolute value to the previous The frequency is divisible. In another embodiment, the frequency divisor with the boundary may be generated by providing a set of integers, wherein the interval between each successive two integers in the set of integers is a fixed value (eg, {950, 951, 952, ..., 1000, 1001, 1002, ..., 1050} and the interval is 1); selecting an integer in the integer set at the first time as a frequency divisor (for example, 1004); The time selects the previous or last integer of the aforementioned selected integer as the next frequency divisor (for example, 1003 or 1005). Repeat the above steps to get a series of frequency divisors. According to the aforementioned random number model, the probability of selecting one larger and smaller next frequency divisor is the same each time (for example, 50%).

As shown in FIGS. 5A to 5C, the clock signal generating method of the present invention is not limited to being generated via the frequency divisor of the modulation frequency divider. For example, in one embodiment, the spread spectrum purpose of the present invention can be achieved by modulating the control voltage V _ctrl used to drive the voltage controlled oscillator 14. In another embodiment, the spread spectrum purpose of the present invention can be achieved by having the frequency divider 15 be used to receive a clock signal _Fout having a slight phase modulation. In another embodiment, the spread spectrum purpose of the present invention can be achieved by adjusting the reference clock signal F _ref prior to comparison with the feedback signal F _fb . Since variations and modifications of the spread spectrum clock signal can be derived from the description in this specification by those skilled in the art, no further details will be described herein.

In summary, the present invention employs a spread spectrum technique to overcome the electromagnetic interference problem; in particular, the present invention uses a random random number model to modulate the clock signal. Therefore, the electric field strength is not concentrated in a center frequency or a small frequency range. Conversely, in the present invention, the electric field intensity can be uniformly dispersed in the spectrum without causing a large frequency hopping or frequency attenuating phenomenon.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. Scope of protection The scope defined in the patent application is subject to change.

2‧‧‧ Random random number modulator

11‧‧‧ phase frequency detector

12‧‧‧Charging pump

13‧‧‧ Loop Filter

14‧‧‧Voltage Controlled Oscillator

15‧‧‧Delephone

S ₁ , S ₂ ‧‧ ‧ switch

F _out ‧‧‧ clock signal

F _ref ‧‧‧Reference clock signal

F _fb ‧‧‧Return signal

Up, Dn‧‧‧ control signals

V _ctrl ‧‧‧ control voltage

Clk‧‧‧ clock

PFD‧‧‧ phase frequency detector

CP‧‧‧Charging pump

LF‧‧‧ loop filter

VCO‧‧‧Voltage Controlled Oscillator

FD‧‧‧Densator

Claims (20)

A spread spectrum clock generator, comprising: a random random number modulator for generating a modulation signal according to a random random number model; and a phase locked loop system connected to the random random number modulator It is used for receiving the modulated signal and generating a spread-spectrum clock signal according to the modulated signal. The spread spectrum clock generator of claim 1, wherein the phase locked loop system comprises: a phase frequency detector for receiving and comparing a reference clock signal and a feedback signal according to the a phase difference between the reference clock signal and the feedback signal generates a control signal; a charge pump for generating a control voltage according to the control signal output by the phase frequency detector; a voltage controlled oscillator, connected The charge pump is configured to generate the clock signal according to the control voltage output by the charge pump; and a frequency divider connected to the voltage control oscillator and the phase frequency detector for receiving the voltage control The clock signal output by the oscillator processes the clock signal in a down conversion manner according to a frequency divisor to generate the feedback signal, and outputs the feedback signal to the phase frequency detector. The spread spectrum clock generator according to claim 2, wherein the phase locked loop system further comprises a loop filter connected to the charge pump and the voltage controlled oscillator for filtering out the control voltage A high frequency part. The spread spectrum clock generator of claim 2, wherein the charge pump is further configured to filter out a high frequency portion of the control voltage. The spread spectrum clock generator of claim 2, wherein the charge pump is integrated in the phase frequency detector. The spread spectrum clock generator according to claim 2, wherein the random random number modulator is connected to the frequency divider and configured to dynamically adjust the frequency of the frequency divider by increasing or decreasing an integer. divisor. A spread spectrum clock generator as described in claim 6 wherein the integer is one. The spread spectrum clock generator according to claim 2, wherein the random random number modulator is connected to the frequency divider and is used for dynamically adjusting one of the clock signals to be received by the frequency divider. Phase. The spread spectrum clock generator of claim 2, wherein the random random number modulator is coupled to the voltage controlled oscillator and configured to dynamically adjust the control voltage to be received by the voltage controlled oscillator. The spread spectrum clock generator of claim 1, wherein the modulation signal is a random random number sequence generated according to the random random number model. A spread spectrum clock generator includes: a phase frequency detector for receiving and comparing a reference clock signal and a feedback signal and according to a phase difference between the reference clock signal and the feedback signal Generate a control a signal pump; a charge pump connected to the phase frequency detector for generating a control voltage according to the control signal output by the phase frequency detector; a voltage controlled oscillator connected to the charge pump for Generating a clock signal according to the control voltage outputted by the charge pump; a frequency divider connected to the voltage controlled oscillator and the phase frequency detector for receiving the clock signal output by the voltage controlled oscillator And processing the clock signal in a down conversion manner according to a frequency divisor to generate the feedback signal, and outputting the feedback signal to the phase frequency detector; and a random random number modulator, connecting The frequency divider is configured to modulate the frequency divisor by generating a modulation signal according to a random random number model. The spread spectrum clock generator according to claim 11, further comprising a loop filter connected to the charge pump and the voltage controlled oscillator for filtering out a high frequency portion of the control voltage. A method for generating a spread spectrum clock signal by a clock generator, comprising the steps of: generating a modulation signal according to a random random number model; and outputting the modulation signal to a phase locked loop system of the clock generator And the phase-locked loop system generates a spread-spectrum clock signal due to the modulated signal. The method for generating a spread spectrum clock signal for a clock generator according to claim 13 , wherein the step of generating the spread spectrum clock signal comprises: receiving and comparing a reference clock signal and a feedback signal. And generating a control signal according to a phase difference between the reference clock signal and the feedback signal; Generating a control voltage according to the control signal; generating the clock signal according to the control voltage; and processing the clock signal in a down conversion manner according to a frequency divisor to generate the feedback signal. The method for generating a spread-spectrum clock signal for a clock generator according to claim 14, wherein the frequency divisor is adjusted according to the modulation signal by increasing or decreasing an integer. The method for generating a spread spectrum clock signal for a clock generator according to claim 14, wherein the step of adjusting the frequency divisor comprises: providing a set of integers, wherein each successive set in the set of integers One of the two integers is spaced apart by a fixed value; one of the first integers selected in the set of integers is a first frequency divisor at a first time; and one of the set of integers is selected at a second time The second integer is a second frequency divisor, wherein the second integer is an integer of one or the last of the first integer. The method for generating a spread spectrum clock signal for a clock generator according to claim 16 , wherein the second integer is 50% of an integer before the first integer, and the second integer is The probability of an integer after the first integer is 50%. The method for generating a spread-spectrum clock signal for a clock generator according to claim 14, wherein the modulation signal is a random random number sequence and the frequency divisor is adjusted according to the random random number sequence. The step includes: generating the random random number sequence according to the Brownian motion, wherein the random random number sequence Each random random number is selected from a positive integer having one and the same absolute value and a negative integer, and the probability that the positive integer and the negative integer are selected is the same; and corresponding to the random number sequence in the random number The random chaotic value is added to the previous frequency divisor to derive the current frequency divisor. The method for generating a spread spectrum clock signal for a clock generator according to claim 14, wherein the clock signal is modulated according to the modulation signal before the feedback signal is generated in a down conversion manner. One phase of the signal. The method for generating a spread spectrum clock signal for a clock generator according to claim 14, wherein the control voltage is modulated according to the modulation signal after the control voltage is generated.