TW201443656A - Improving a rate of transfer of data within a plasma system - Google Patents

Abstract

A bus interconnect interfaces a host system to a radio frequency (RF) generator that is coupled to a plasma chamber. The bus interconnect includes a first set of host ports, which are used to provide a power component setting and a frequency component setting to the RF generator. The ports of the first set of host ports are used to receive distinct variables that change over time. The bus interconnect further includes a second set of generator ports used to send a power read back value and a frequency read back value to the host system. The bus interconnect includes a sampler circuit integrated with the host system. The sampler circuit is configured to sample signals at the ports of the first set at selected clock edges to capture operating state data of the plasma chamber and the RF generator.

Description

Improve the transfer rate of data in the plasma system

The present invention relates to systems and structures for improving data transfer rates within a plasma system.

A master device of a communication system and a slave device follow the agreement to transfer information to each other. For example, in an industry standard serial parallel interface (SPI), data is transmitted through a single wire train from the master device to the slave device. As another example, a clock signal is transmitted from the master device to the slave device.

However, serial transmission of data has a number of disadvantages, one of which is a low data rate. When one bit is transmitted by wire each time, a large amount of time is required to transfer information between the master device and the slave device.

The disclosure relates to improving the data transfer rate within a plasma system. It should be appreciated that the embodiments described in this disclosure can be implemented in many ways, such as a process, a device, a system, a device, a method of computer readable media, and the like. Various embodiments of the disclosure are described below.

In several embodiments, a busbar interconnect structure is provided for interfacing a host system to a radio frequency (RF) generator coupled to a plasma chamber. The bus interconnect structure contains a plurality of host ports. The first and second links of the host system are used to provide a power component setting and a frequency component setting to the RF generator. In addition, the third, fourth, and third of the host system The fifth and sixth lines are used to receive four different variables that change over time. The bus interconnect structure further includes a plurality of generators. The first and second axes of the RF generator are used to communicate a power back reading and a frequency back reading to the host system. The busbar interconnect structure includes a sampler circuit that is integrated with the host system. The sampler circuit is configured to form the third, fourth, fifth, and sixth sampling signals of the selected clock edge at the host system to capture the operating state of the RF generator and the plasma chamber data.

In several embodiments, a busbar interconnect structure is provided for interfacing a host system to an RF generator coupled to a plasma chamber. The bus interconnect structure includes a first set of host ports for providing a power component setting and a frequency component setting to the RF generator. The first set of host systems is used to receive a plurality of different variables that vary over time. The busbar interconnect structure further includes a second set of generators 传送 for transmitting a power back reading value and a frequency back reading value to the host system. The busbar interconnect structure includes a sampler circuit that is integrated with the host system. The sampler circuit is configured to sample signals at the first set of host ports at selected clock edges to retrieve operational status data of the RF generator and the plasma chamber.

In various embodiments, a plasma system is provided. The plasma system includes a host system for providing data signals. The plasma system further includes an RF generator coupled to the host system. The RF generator is configured to generate an RF signal based on the data signals. The plasma system includes an impedance matching circuit for matching the impedance of the RF generator to the impedance of a plasma chamber. The plasma system also includes an RF transmission line connecting the impedance matching circuit to the plasma chamber. The plasma system includes a bus interface that connects the host system to the RF generator. The bus interface includes a first set of host ports. The first set of host computers is used to provide a power component setting and a frequency component setting to the RF generator. The first set of host systems is used to receive a plurality of different variables that vary over time. The busbar interconnect structure includes a second set of generators 传送 for transmitting a power back reading value and a frequency back reading value to the host system. The busbar interconnect structure includes a sampler circuit that is integrated with the host system. The sampler circuit is configured to sample signals at the first set of host ports at selected clock edges to retrieve operational status data of the RF generator and the plasma chamber.

In various embodiments, a data rate transmission system is provided. Data rate transmission system The system includes a plurality of ports between a host system and an RF generator to allow data to be transmitted at a higher rate than when a single wire is used. For example, several (eg, three, four, five, etc.) variables are transferred between the host system and the RF generator over a period of time (eg, one second, one microsecond, etc.). These variables can include power, frequency, real part of the load impedance, and the imaginary part of the load impedance. As another example, the variables may include frequency, amount of voltage, amount of current, and phase between voltage and current.

Also, in some embodiments, the number of variables transmitted between the host system and the RF generator is limited, such as to three variables, five variables, six variables, and the like. The number of variables is limited to reduce the number of communication channels between the host system and the RF generator. For example, the number of communication channels between the host system and the RF generator used to transmit the variables is less than 32, 64, 128, and the like. The reduction in the number of communication channels reduces the number of turns on the parallel serial parallel interface (PSPI) of the host system connected to the communication channel and reduces the number of turns on the PSPI of the RF generator connected to the communication channel. The reduction in the number of turns and the number of communication channels reduces the effective area on a wafer (e.g., a wafer containing the host system, a wafer containing an RF controller, etc.). In addition, the reduction in the number of communication channels reduces interference in the signals transmitted over the communication channel and reduces the chance of signal integrity loss of the signals. When the signal is transmitted via the limited number of communication channels, it may not be necessary to check the signal integrity. This number of variables allows for the determination of whether a plasma chamber is functioning properly, such as determining that the plasma is not confined, arcing, and the like.

Moreover, in several embodiments, the host system and the host system are compared to the use of a packetization protocol (e.g., an Ethernet protocol, an Ethernet for Control Automation Technology (EtherCAT) protocol, etc.) It takes less time to transfer this variable between RF generators. It should be noted that in various embodiments, the EtherCAT protocol is slower, such as having a lower operating frequency, than the PSPI protocol applied by PSPI. For example, EtherCAT's data rate is 1 kilohertz (kHz), which is lower than the data rate applied by the PSPI protocol. As another example, fewer data bit numbers are transmitted via EtherCAT® than the number of data bits transmitted via the PSPI. The packetization protocol is used to generate data packets from the data to be transmitted between the master device and the slave device. Can be based on the connection to the packetization protocol interface (example) The bandwidth of the network, such as Ethernet, EtherCAT, etc., limits the packetization. In some embodiments, the encapsulation is not performed on the transfer variable between the host system and the RF generator.

Moreover, in several embodiments, statistics such as average, median, mode, maximum, minimum, rolling variance, standard deviation, interquartile range, etc. are These variables are determined and the remaining values of the variables are deleted. For example, the variables during a time window are averaged and the values used to determine the average are deleted by the storage device of the host system.

Determining the statistic and deleting the values saves memory space and provides the possibility of determining a fault within the plasma system. For example, when all values are stored within the host system, above the cloud, etc., the number of such values is substantial and can be a hindrance to transmitting such values between devices such as network devices. When the statistical values are stored in more than one storage device of the host system, the statistical values occupy less memory space than all of the values. Moreover, it is easier to transmit such statistics over a network (eg, the Internet, an internal network, etc.) than to transmit all values. Less network bandwidth is used when transmitting statistics than the bandwidth used to transmit all values.

Some of the advantages of the above embodiments include faster data transfer between the host system and the RF generator than those provided by the serial communication of a single wire; savings in effective area on the semiconductor wafer; elimination of check signal integrity Demand; and the need to transmit data without the use of a packetization agreement.

Other embodiments will be apparent from the following detailed description and drawings.

100‧‧‧ system

102‧‧‧Host system

104‧‧‧SDD module

106‧‧‧VME module

108‧‧‧RF (RF) generator

110‧‧‧Communication chain

112‧‧‧RF generator

114‧‧‧Communication chain

116‧‧‧RF generator

118‧‧‧Communication chain

120‧‧‧impedance (Z) matching circuit

122‧‧‧Communication media

124‧‧‧Communication media

126‧‧‧Communication media

128‧‧‧The plasma chamber

130‧‧‧RF transmission line

132‧‧‧Connect

134‧‧‧Connect

136‧‧‧Connect

138‧‧‧Connect

200‧‧‧ system

202‧‧‧ Controller

203‧‧‧PSPI

204‧‧‧ Controller

205‧‧‧PSPI

206‧‧‧ Controller

207‧‧‧PSPI

208‧‧‧ controller

210‧‧‧PSPI

212‧‧‧PSPI

214‧‧‧PSPI

250‧‧‧ system

252‧‧‧ Controller

254‧‧‧ Bus Bar Interconnect Structure

254‧‧‧Sampling circuit

300‧‧‧ Timing diagram

302‧‧‧clock signal

304‧‧‧SDI signal

306‧‧‧SDI signal

308‧‧‧SDI signal

310‧‧‧SDI signal

312‧‧‧ rising edge

314‧‧‧ rising edge

352‧‧‧Parallel chain

400‧‧‧Host system

402‧‧‧FPGA

404‧‧‧Microprocessor

406‧‧‧MSPI

408‧‧‧Soft Core DSP

410‧‧‧High speed aircraft

412‧‧‧High speed bus

415‧‧‧High speed 埠

416‧‧‧SDD logic block

418‧‧‧Offset Compensation Module

420‧‧‧Event/Fault Detection Module

422‧‧‧VME communication block

450‧‧‧Host system

452‧‧‧Microprocessor

454‧‧‧Variable Module

502, 504, 506‧‧‧ charts

The various embodiments of the present disclosure are best understood by referring to the following description and the accompanying drawings.

1 is a block diagram of a system for improving data transfer rates in accordance with various embodiments of the present disclosure.

2A is a block diagram of a system in accordance with several embodiments of the present disclosure. The system is used to improve the data transfer rate between the host system of the system of Figure 1 and the radio frequency (RF) generator of the system of Figure 1.

In accordance with several embodiments of the present disclosure, FIG. 2B is a block diagram of an embodiment of a system for improving data transfer rates between a host system and an RF generator.

In accordance with several embodiments of the present disclosure, FIG. 3A is a timing diagram depicting sampling of variables synchronized with a clock signal of the system of FIG. 2A.

In accordance with several embodiments of the present disclosure, FIG. 3B depicts the difference between parallel transmission of data and parallel transmission of data in parallel.

4A is a block diagram of an embodiment of a host system in accordance with various embodiments of the present disclosure.

4B is a block diagram of an embodiment of a host system in accordance with several embodiments of the present disclosure.

In accordance with several embodiments of the present disclosure, FIG. 5 is a diagram of a plurality of diagrams of an embodiment to illustrate variables that facilitate determining a plasma event within the plasma chamber of the system of FIG.

The following embodiments describe systems and methods for improving data transfer rates.

In accordance with several embodiments described in this disclosure, FIG. 1 is a block diagram of a system 100 for improving data transfer rates. A host system 102 includes a statistical data decimation (SDD) module and a VME module 106. As used herein, a host system includes a controller that includes more than one processor and more than one storage device. In various embodiments, the operations performed by a controller described herein are performed by more than one processor of the controller.

As used herein, a processor can be a central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a programmable logic element (PLD), and the like. Examples of storage devices include read only memory (ROM), random access memory (RAM), or a combination thereof. The storage device can be a flash memory, a fault tolerant disk array (RAID), a hard disk, or the like.

When used herein, a module includes hardware, software, or a combination thereof. Example In this case, a module is implemented as an integrated circuit, such as a field programmable logic gate array (FPGA), an ASIC, etc., which processes the data. As another example, a module is a computer software program that is executed by a microprocessor. As another example, a portion of a module is implemented as an integrated circuit, and another portion of the module is implemented by a microprocessor.

The SDD module 104 includes a 2 MHz parallel serial parallel interface (PSPI) that is coupled to the PSPI of the 2 MHz radio frequency (RF) generator 108 via a communications link 110 (e.g., a cable). The SDD module 104 further includes a 27 MHz PSPI that is coupled to the PSPI of the 27 MHz RF generator 112 via a communications link 114 (e.g., a cable). In addition, the SDD module 104 includes a 60 MHz PSPI that is coupled to the PSPI of the 60 MHz RF generator 116 via a communications link 118 (e.g., a cable). A cable that connects a PSPI to another PSPI can transmit signals using a protocol such as the RS-232 protocol, the Universal Serial Bus (USB) protocol, and the like.

The RF generators 108, 112, and 116 are coupled to an impedance (Z) matching circuit 120. For example, RF generator 108 is coupled to impedance matching circuit 120 via a communication medium 122 (eg, a cable), RF generator 112 is coupled to impedance matching circuit 120 via communication medium 124, and RF generator 116 is coupled via communication medium 126 is coupled to impedance matching circuit 120.

In some embodiments, an impedance matching circuit matches the impedance of a load coupled to the impedance matching circuit to an impedance of a source also coupled to the impedance matching circuit. For example, the impedance matching circuit 120 matches the impedance of the plasma chamber 128 connected to the impedance matching circuit 120 via the RF transmission line 130 to the impedance of the RF generators 108, 112, and 116. In some embodiments, impedance matching circuit 120 includes electrical components, such as capacitors, inductors, etc., to match the impedance. In various embodiments, an RF transmission line includes an RF tunnel coupled to an RF band that is coupled to an RF pole.

The PSPI of the SDD module 104 transmits power set points (e.g., power, etc.) and frequency set points (e.g., frequency, etc.) to the PSPIs of the RF generators 108, 112, and 116 via the communication chains 110, 114, and 118. For example, the 2 MHz PSPI of the SDD module 104 transmits the power set point and frequency set point to the PSPI, SDD of the RF generator 108 via the communication link 110. The 27 MHz PSPI of module 104 transmits the power set point and frequency set point to the PSPI of RF generator 112 via communication link 114, and the 60 MHz PSPI of SDD module 104 transmits the power set point and frequency set point to RF via communication link 118. The PSPI of generator 116.

A digital signal processor (DSP) of an RF generator receives a power set point and provides the power set point to a driver of the RF generator, such as more than one transistor or the like. The driver generates an RF signal having a power indicated within the power set point. An amplifier coupled to the driver amplifies the RF signal and provides the amplified RF signal to the impedance matching circuit 120. The impedance matching circuit 120 transmits the amplified RF signal having the power to the plasma chamber 128 via the RF transmission line 130.

Similarly, the RF generator's DSP receives a frequency set point and provides the frequency set point to the driver of the RF generator. The driver generates an RF signal having a frequency indicated within the frequency set point. An amplifier coupled to the driver amplifies the RF signal and provides an amplified RF signal to the impedance matching circuit 120. The impedance matching circuit 120 transmits the amplified RF signal having the frequency to the plasma chamber 128 via the RF transmission line 130.

The plasma chamber 128 includes an electrostatic chuck (ESC), an upper electrode, and other components (not shown), such as an upper dielectric ring surrounding the upper electrode and an upper electrode extension surrounding the upper dielectric ring. a lower dielectric ring surrounding the lower electrode of the ESC, a lower electrode extension surrounding the lower dielectric ring, a plasma exclusion zone (PEZ) ring, a lower PEZ ring, and the like. The upper electrode is located opposite the ESC and faces the ESC. The ESC contains a lower electrode. A workpiece (eg, a semiconductor wafer, etc.) is supported on the upper surface of the ESC. For example, an integrated circuit of a specific-purpose integrated circuit (ASIC), a programmable logic element (PLD), or the like is formed on the workpiece, and the integrated circuit is used for various electronic devices such as a mobile phone, a tablet, Smart phones, computers, laptops, networking devices, and more. The upper and lower electrodes are each composed of a metal such as aluminum, aluminum alloy, copper, or the like.

In one embodiment, the upper electrode includes an opening that is coupled to a central gas feed (not shown). The central gas feedthrough receives more than one process gas from a gas supply (not shown). Examples of process gases include oxygen-containing gases such as O ₂ . Other examples of process gases include fluorine-containing gases such as tetrafluoromethane (CF ₄ ), sulfur hexafluoride (SF ₆ ), hexafluoroethane (C ₂ F ₆ ), and the like. The upper electrode is grounded. The ESC is connected to the RF generators 108, 112, and 116 via an impedance matching circuit 120.

When the process gas is supplied between the upper electrode and the ESC, and when the RF generators 108, 112, and/or 116 supply the RF signal to the lower electrode of the ESC via the impedance matching circuit 120, the process gas is ignited in the plasma chamber Plasma is generated within chamber 128.

A sensor within an RF generator that measures a plurality of variables based on RF signals transmitted on a communication medium (e.g., communication medium 122, 124, 126, etc.) coupled to the sensor, such as Forward power, reflected power, complex voltage, complex current, etc. For example, a sensor of the RF generator 108 measures the complex voltage and the complex current based on the RF signal transmitted over the communication medium 122 between the RF generator 108 and the impedance matching circuit 120.

A DSP within an RF generator can determine (eg, calculate, estimate, etc.) other variables based on variables measured by a sensor of the generator, such as delivered power, complex voltage and current (complex V&I), Γ (gamma), load impedance, etc. For example, a DSP of RF generator 108 calculates complex V&I based on complex voltage and complex current. The complex V&I includes: a voltage amount which is the same as the complex voltage; a current amount which is the same as the complex current; and a phase which is a phase difference between the phase of the complex voltage and the phase of the complex current.

In some embodiments, the variables measured by the DSP of the RF generator or measured by the sensors of the generator are transmitted to the PSPI of the SDD module 104 via a corresponding communication link. For example, the variables measured by the DSP of the RF generator 108 or measured by the sensors of the RF generator 108 are transmitted from the PSPI of the RF generator 108 to the SDD module 104 via the communication chain 110. 2MHz PSPI.

In various embodiments, a transistor-transistor (TTL) signal is provided by the sync output RF of the RF generator 108 to the sync input RF of the RF generator 112 to operate the RF generator 112 with the RF generator. 108 synchronization (such as changing the state of the RF signal, etc.). In several embodiments, the TTL signal is provided by the sync output of the RF generator 112 to the sync input port of the RF generator 116 to synchronize the operation of the RF generators 112 and 116. Moreover, in some embodiments, the TTL signal is provided by the sync output of the RF generator 116 to the sync input port of the SDD module 104 to notify the SDD module 104 by the RF generators 108, 112 and The state of the RF signal generated by 116, such as a high state, a low state, a high power state, a low power state, and the like. It should be noted that the high state or high power state is a state of the RF signal that has a higher amount of power than the low state or low power state. In some embodiments, an RF signal switches between a high state and a low state.

In some embodiments, data generated in the SDD module 104, stored within the SDD module 104, and/or received by the PSPI of the SDD module 104 from the RF generator (eg, variables, etc.) Etc., the SDD output from the SDD module is provided to the SDD input of the VME module 106 via a connection 132, such as an Ethernet connection, an EtherCAT connection, a USB connection, a serial connection, a parallel connection. and many more. The received data via the SDD input can be stored in the VME module 106.

In some embodiments, the 2 MHz transmit/receive (Tx/Rx) of the VME module 106 is used to connect setpoints (eg, temperature set points, etc.) other than power and frequency via a connection 134 (eg, an Ethernet connection). An EtherCAT connection, a USB connection, a serial connection, a parallel connection, etc.) is transmitted to one of the RF generators 108 (e.g., Ethernet, EtherCAT, etc.). In addition, the 27 MHz transmit/receive (Tx/Rx) of the VME module 106 is used to transmit setpoints other than power and frequency to a port of the RF generator 112 via a connection 136 (eg, Ethernet, EtherCAT埠). and many more). Moreover, the 60 MHz transmit/receive (Tx/Rx) of the VME module 106 is used to transmit a set point other than power and frequency to a port of the RF generator 116 via a connection 138 (eg, Ethernet, EtherCAT埠). and many more). In some embodiments, the Tx/Rx of the VME module 106 transmits data (eg, variables, etc.) received from the SDD module 104 to the RF generators 108, 112, and 116 (eg, Ethernet, EtherCAT). Hey, etc.). In various embodiments, connections 134, 136, and 138 assist VME module 106 in receiving data from RF generators 108, 112, and 116.

It should be noted that while the above embodiments have been described in terms of 2 MHz, 27 MHz, and 60 MHz generators, any other frequencies are used in several embodiments. For example, instead of 2MHz, a 4MHz generator is used.

It should be noted that any number of RF generators can be used. For example, one or two RF generators are used instead of three RF generators.

2A is a block diagram of an embodiment of a system 200 for improving data transfer rates between host system 102 and RF generators 108, 112, and 116 (FIG. 1).

An RF generator contains a controller. For example, RF generator 108 includes a controller 202 that includes PSPI 203. In addition, RF generator '112 includes a controller 204 that includes a PSPI 205. The RF generator 116 includes a controller 206 that includes a PSPI 207.

The host system 102 includes a VMAP (virtual methodology for advanced process control) controller 208. The VMAP controller 208 includes a PSPI 210, which is an example of a 2 MHz PSPI of the SDD 104 (FIG. 1). The VMAP controller 208 includes a PSPI 212, which is an example of a 27 MHz PSPI of the SDD 104, and the VMAP controller 208 includes a PSPI 214, which is an example of a 60 MHz PSPI of the SDD 104.

The 2MHz power setpoint serial data output (SDO) of the PSPI 210 transmits a power set point to a 2MHz power setpoint serial data input of the PSPI 203 via a communication channel C2 (SDI, serial data) Input)埠. Examples of communication channels include more than one wire, etc., which follow an agreement, such as a serial protocol, a differential agreement, and the like. For example, in the example of a differential signal, a communication channel includes two wires. When using the differential signal method, the data used to transmit data signals (such as set points, readback data, variables, etc.) compared to the method of not using the differential signal (set point, readback, etc.) The number of pins is increased (for example, doubled) and the immunity of the data signal is improved. Otherwise, in this example, a communication channel contains a wire. Moreover, in some embodiments, the 2 MHz frequency set point SDO of the PSPI 210 transmits a frequency set point to a 2 MHz frequency set point SDI P of the PSPI 203 via a communication channel C4.

In addition, the power of the PSPI 203 is read back to the SDO, and a power reading is sent via the communication channel C1 to the power readback SDI of the PSPI 210, which is measured, for example, by the sensor of the RF generator 108 (FIG. 1). The resulting forward power, the reflected power measured by the sensor of the RF generator 108, the delivered power determined by the DSP of the RF generator 108, and the like. It should be noted that the delivered power is the difference between the forward power and the reflected power. It should be noted that in several embodiments, the forward power is included by the RF generator to the plasma chamber 128 (Fig. 1) The RF power, and the reflected power, includes RF power that is reflected back from the plasma chamber 128 toward the RF generator.

Moreover, in various embodiments, the frequency of the PSPI 203 is read back to the SDO, and a frequency reading is sent via the communication channel C3 to the frequency readback SDI of the PSPI 210, such as by the RF generator 108 (FIG. 1). The frequency of the forward power measured by the sensor, the frequency of the reflected power measured by the sensor of the RF generator 108, the frequency of the delivered power determined by the DSP of the RF generator 108, and the like.

Also, in some embodiments, the real impedance of PSPI 203 is read back to SDO, and the real part of the load impedance of a load (eg, a resistor, etc.) is sent via communication channel C5 to the 2 MHz real impedance SDI of PSPI 210. Examples of loads include more than one communication medium 122, 124, and 126, impedance matching circuit 120, RF transmission line 130, plasma chamber 128, or a combination thereof. In various embodiments, the imaginary impedance of PSPI 203 is read back to SDO, and the imaginary part of the load impedance (eg, reactance, etc.) is sent via communication channel C6 to the 2 MHz imaginary impedance SDI of PSPI 210.

The PSPI 210 slave select (SS, slave select) signal is sent from the 2MHz SS埠 to the 2MHz SS埠 of the PSPI 203 via a communication channel C7 to select a semiconductor chip, and the RF controller 202 and the PSPI 203 are implemented on the semiconductor chip. on. An SS signal determines which of the PSPIs 203, 205, and/or 207 are listening (e.g., reading, etc.) data from the VMAP controller 208 and/or transmitting data to the VMAP controller 208. For example, to select PSPI 203, an SS signal is transmitted via communication channel C7. When PSPI 203 is selected, a set point can be sent to PSPI 203 and/or readback from PSPI 203 is performed. As another example, to select the semiconductor chip on which the RF controller 204 and PSPI 205 are implemented, an SS signal is sent from the 27 MHz SS of the PSPI 212 to the 27 MHz SS of the PSPI 205 via the communication channel C16. In addition, in order to select the semiconductor chip on which the RF controller 206 and the PSPI 207 are implemented, an SS signal is sent from the 60 MHz SS of the PSPI 214 to the 60 MHz SS of the PSPI 207 via the communication channel C25.

The one-time signal is sent by the RF control (CTRL)-CLK of the PSPI 210 to the RF CTRL-CLK of the PSPI 203 via the communication channel C8. And, a ground signal (example For example, the reference signal, zero voltage signal, etc. is transmitted between the RF CTRL-ground (GND) of the PSPI 210 and the RF CTRL-GND of the PSPI 203. The local signal establishes a reference to all signals transmitted between the VMAP controller 208 and the PSPIs 203, 205, and 207 in addition to a clock signal.

Similarly, a signal similar to that transmitted between PSPI 210 and PSPI 203 is transmitted between PSPI 212 and PSPI 205 via communication channels C10 through C18. In addition, a signal similar to that transmitted between PSPI 210 and PSPI 203 is transmitted between PSPI 214 and PSPI 207 via communication channels C19 through C27. In some embodiments, the communication channels C1 to C9 are included in a cable, such as an RS-232 cable, etc., and the communication channels C10 to C18 are included in another cable, such as an RS-232 cable, etc., and Communication channels C19 through C27 are contained within yet another cable, such as an RS-232 cable.

In addition, a TTL signal is sent by the TTL output of the RF controller 206 to the TTL input port of the VMAP controller 208. It should be noted that the TTL output of the RF controller 206 is the same as the synchronous output of the 60 MHz RF generator 116 (FIG. 1), and the TTL input of the PSPI 210 is the same as the sync input of the SDD 104 (FIG. 1). .

In various embodiments, the communication between the PSPIs 210, 212, and 214 of the host system 102 and the PSPIs 203, 205, and 207 of the RF controllers 202, 204, and 206 is point-to-point. For example, PSPI 210 is not connected to PSPI 203 via a network (eg, internet, internal network, etc.) that includes network devices (eg, routers, switches, bridges, etc.). As another example, PSPI 212 is not connected to PSPI 205 via a network, and PSPI 214 is not connected to PSPI 207 via a network. The point-to-point communication reduces the length of more than one of the communication channels C1 through C27 between the host system 102 and the RF generators 202, 204, and 206 as compared to the length of the cable network used in the network.

In several embodiments, there is no packetization performed by a PSPI, such as generating an Ethernet packet, generating an EtherCAT packet, and the like. In various embodiments, fewer than 32 parallel channels are used to transfer data signals between the PSPI of the VMAP controller 208 and the PSPI of the RF generator controller. For example, less than 32 parallel channels are used to transmit power readback signals, power setpoint signals, frequency readback signals, frequencies between PSPI 210 and PSPI 203. Set point signal, real impedance signal, and imaginary impedance signal.

In several embodiments, the PSPI of the RF controller is implemented on a wafer that is independent of a wafer on which the PSPI of another RF controller is implemented. For example, PSPI 203 is implemented within a semiconductor wafer, PSPI 205 is implemented within another semiconductor wafer, and PSPI 207 is implemented within yet another semiconductor wafer. In some embodiments, the VMAP controller 208 is implemented within a single semiconductor wafer or within a plurality of semiconductor wafers. For example, PSPI 210 is implemented within a semiconductor wafer, PSPI 212 is implemented within another semiconductor wafer, and PSPI 214 is implemented within yet another semiconductor wafer.

In various embodiments, the readback of the variables is performed in synchronization with (e.g., simultaneous, etc.) the transfer of a set point. For example, the power readback is synchronized with the transmit power setpoint via communication channel C2 and is performed via communication channel C1. As another example, the frequency readback is synchronized with the transmit power setpoint via communication channel C2 and/or synchronized with the transmit frequency setpoint via communication channel C4, via communication channel C3. As yet another example, the variable signals transmitted via channels C1, C3, C5, and C6 and transmitted via channels C2 and C4 are transmitted (eg, read, transmitted, etc.) in synchronization with the clock signal transmitted via communication channel C8. Set point signal.

In some embodiments, the readback signal is an example of a data signal, such as a power readback signal, a frequency readback signal, a load impedance real readback signal, a load impedance imaginary readback signal, and the like. In addition, the set point signal is an example of a data signal, such as a frequency set point signal, a power set point signal, and the like. Also, the slave select signal is an example of a control signal.

In various embodiments, host system 102 is implemented within more than one integrated circuit, such as an FPGA, ASIC, and the like. Moreover, in some embodiments, one or more of the RF controllers 202, 204, and 206 are implemented within more than one integrated circuit.

In some embodiments, the variable transmissions of all RF generators are synchronized with a clock signal, such as concurrent with a clock signal, performed at the edge of the clock, and the like. For example, the variables transmitted on channels C1, C3, C5, C6, C10, C12, C14, C15, C19, C21, C23, and C24 are the same as the RF CTRL-CLK buffer sent from PSPI 210. Pulse Number synchronization. As another example, multiple clock signals transmitted from RF CTRL-CLK of PSPI 210, 212, and 214 are synchronized with each other, and also with channels C1, C3, C5, C6, C10, C12, C14, C15. The variables transmitted on C19, C21, C23, and C24 are synchronized. As another example, the variables transmitted on channels C1, C3, C5, C6, C10, C12, C14, C15, C19, C21, C23, and C24, as well as in channels C2, C4, C11, C13, C20, And the variable setpoint transmitted on C22 is synchronized with a clock signal sent from RF CTRL-CLK of PSPI 210. As another example, multiple clock signals transmitted from RF CTRL-CLK of PSPI 210, 212, and 214 are synchronized with each other, and also with channels C1, C2, C3, C4, C5, C6, C9, C10. Synchronization of variables transmitted on C11, C12, C13, C14, C15, C19, C20, C21, C22, C23, and C24.

In various embodiments, the PSPI of the VMAP controller 208 operates in a setpoint only mode or in a read only mode. For example, when the 2MHz power setpoint SDO埠 of the PSPI 210 and the 2MHz frequency setpoint SDO are set to transmit the setpoint, the PSPI 210's 2MHz power readback SDI, 2MHz frequency readback SDI, 2MHz real impedance SDI埠, and 2MHz imaginary impedance SDI埠 are not set to read back from PSPI 203. As another example, when the 2 MHz power readback SDI, 2 MHz frequency readback SDI, 2 MHz real impedance SDI, and 2 MHz imaginary impedance SDI of the PSPI 210 are set to read back from the PSPI 203, the PSPI 210 The 2MHz power setpoint SDO埠 and the 2MHz frequency setpoint SDO埠 are not set to transmit setpoints to PSPI 203.

In several embodiments, the PSPI of the RF controller, such as RF controller 202, RF controller 204, F controller 206, etc., operates in a setpoint only mode or a read only read mode. For example, when the 2MHz power setpoint SDI埠 and 2MHz frequency setpoint SDI of the PSPI 203 are set to read (eg, receive, access, etc.) setpoints, the 2MHz power of the PSPI 203 is read back to SDO, 2MHz. The frequency readback SDO, the 2 MHz real impedance SDO埠, and the 2 MHz imaginary impedance SDO埠 are not set to transmit variables to the PSPI 210. As another example, when PSPI 203's 2MHz power readback SDO, 2MHz frequency readback SDO, 2MHz real impedance SDO埠, and 2MHz imaginary impedance SDO are set to transmit variables to PSPI 210, 2MHz of PSPI 203 Power set point SDI埠 and 2MHz frequency set point SDI埠 are not set to PSPI 210 receives the set point.

In various embodiments, the PSPI (eg, PSPI 210, 212, 214, etc.) of the host system 102 is configured to operate at a data rate that is a PSPI connected to an RF generator of the host system 102. support. For example, when the RF controller 202 is implemented on a fast FPGA, the RF CTRL-CLK of the PSPI 210 operates at a frequency greater than or equal to 1 megahertz (MHz) to transmit the clock signal to RF controller 202. In this example, when another RF controller (not shown) is implemented over a slow FPGA instead of the RF controller 202, the RF CTRL-CLK of the PSPI 210 is set to operate at frequencies below 1 MHz. To transmit the clock signal to the other RF controller. It should be noted that 1 MHz is an example, and the frequency is not limited to 1 MHz. For example, instead of 1 MHz, another frequency, such as 2 MHz, 3 MHz, etc., can be used to illustrate the difference between fast and slow FPGAs.

2B is a block diagram of an embodiment of a system 250 for improving data transfer rates between a host system 102 and an RF controller 252, an RF controller 252 being an RF controller 202, an RF controller 204, Or an example of RF controller 206 (Fig. 2A). The system 250 includes a host system 102, an RF controller 252, and a busbar interconnect structure 254.

Busbar interconnect structure 254 interfaces (e.g., provides one or more communication channels, provides a communication protocol, etc.) between host system 102 and RF controller 252. Busbar interconnect structure 254 includes a PSPI that is mounted within host system 102 and includes a plurality of hosts 埠 HP1 through HP6. In addition, busbar interconnect structure 254 includes a PSPI mounted within RF controller 252 that includes a plurality of generators 埠GP1 through GP6.

It should be noted that although six turns are shown, in several embodiments, RF controller 252 or host system 102 includes any number (e.g., nine, ten, eight, etc.). For example, the PSPI installed within host system 102 includes an HP7 that transmits a slave select signal to select a PSPI that is installed within RF controller 252 to allow for data (eg, power setpoint, frequency setting). Point, etc.) to PSPI installed within the RF controller 252, or PSPI readback data (eg, variables VR1 through VR4, etc.) that are installed within the RF controller 252. As another example, the PSPI of host system 102 includes a port of HP8 that transmits a clock signal to PSPI installed within RF controller 252. As yet another example, the host system The PSPI of 102 includes an HP9 that transmits a signal to or receives a PSPI installed in the RF controller 252. As another example, the PSPI installed within the RF controller 252 includes a GP7 that receives a slave select signal from the 埠HP7 to initiate transmission of data to the PSPI installed within the host system 102 or to initiate reception from the installation. Information about the PSPI within the host system 102. As another example, the PSPI installed in the RF controller 252 includes a GP 8 that receives a clock signal from a PSPI installed within the host system 102. As yet another example, the PSPI installed within the RF controller 252 includes a GP9 that transmits a signal to or receives a PSPI installed in the host system.

In some embodiments, 埠HP1 is a power setpoint serial data output 埠, 埠HP2 is a frequency set point serial data output 埠, 埠HP3 is a power readback ship data input 埠, 埠HP4 system a frequency Read back the serial data input 埠, 埠 HP5 is a load impedance real part serial data input 埠, 埠 HP6 series load impedance imaginary serial data input 埠, 埠 HP7 series driven selection signal 埠, 埠 HP8 series one clock signal Hey, and 埠 HP9 is the signal number.

In various embodiments, the 埠GP1 system power set point serial data input 埠, 埠 GP2 system frequency set point serial data input 埠, 埠 GP3 system power readback serial data output 埠, 埠 GP4 series frequency readback serial Data output 埠, 埠 GP5 system load impedance real part serial data output 埠, 埠 GP6 system load impedance imaginary serial data output 埠, 埠 GP7 system slave selection signal 埠, 埠 GP8 system clock signal 埠, and 埠 GP9 The ground signal is 埠.

The HP1 transmits a power component setting (eg, power amount, etc.) to the 埠GP1. In addition, 埠HP2 transmits a frequency component setting (such as frequency, etc.) to 埠GP2. In addition, 埠HP2 to HP6 receive (eg, read back, access, etc.) four different variables VR1 through VR4 that change over time. For example, complex load impedance, complex V&I, complex voltage, complex current, complex power, retracement, etc. have positive frequencies. As another example, in reality, the frequency is not constant. For example, a frequency has a standard deviation, a variation, and the like that change frequency over time. In several embodiments, the frequency is maintained constant.

埠 GP3 transmits a power readback value (eg, power amount, etc.) to 埠HP3. In addition, the 埠GP4 transmits a frequency readback value (e.g., frequency, etc.) to the host system 102.

The PSPI of host system 102 includes a sampler circuit 254. Sampler circuit The 254 is integrated with the host system 102, such as within an integrated circuit of the host system 102. In some embodiments, each of the samples sampled by a signal includes a sampler circuit. For example, 埠HP3 includes a sampler circuit, 埠HP4 includes a sampler circuit, 埠HP5 includes a sampler circuit, and 埠HP6 includes a sampler circuit, 埠GP1 includes a sampler circuit, and 埠GP2 includes a sampler circuit Sampler circuit.

Sampler circuit 254 samples the signals (e.g., variables VR1 through VR4, etc.) received at 埠HP3 through HP6 at selected clock edges (e.g., rising clock edges, falling clock edges, etc.). Sampler circuit 254 samples the signal to retrieve operational status data, such as plasma chamber 128 (FIG. 1), and RF generators 108, 112, and/or 116 (FIG. 1), frequency, load impedance, variable V1. To V4, complex voltage, complex current, complex V&I. Plasma chamber 128 is provided by a sensor (eg, a voltage and current sensor, a voltage sensor, a current sensor, a power sensor, etc.) that includes an RF generator of RF generator controller 252 The operational status data is detected, such as measurement, sensing, and the like. In several embodiments, the operational status data (e.g., retracement, complex delivery power, etc.) of the plasma chamber 128 is determined by the DSP of the RF generator including the RF controller 252. In various embodiments, the operational status data of the RF generator includes the frequency, power, etc. set by the RF generator. It should be noted that host system 102 provides a set point (e.g., frequency set point, power set point, etc.) to an RF generator. When the RF generator receives a set point, the RF generator sets the power and/or frequency based on the set point. For example, the RF generator queries a set point in a storage device of the RF generator to determine the drive power and/or frequency associated with the set point (eg, a link, etc.). The set power and/or frequency (eg, drive power and/or frequency, etc.) is provided to a driver of the RF generator to generate an RF signal having the power and/or frequency.

In an embodiment in which five variables are transmitted via a communication channel between the host system 102 and the RF controller 252, examples of the five variables include frequency, complex forward power, and complex reflected power. Complex power includes power and power phase. Another example of five variables includes frequency, complex voltage, and complex current. The complex voltage includes the voltage amount and the voltage phase. The complex current contains the amount of current and the phase of the current. In these embodiments, five communication channels are used between the PSPI of the host system 102 and the PSPI of the RF controller 252 to read back five from the PSPI of the RF controller 252. variable.

3A is a timing diagram 300 of an embodiment depicting sampling of four variables VR1, VR2, VR3, and VR4 synchronized with a clock signal, such as reading, accessing, and the like. The variable VR1 is represented as SDI signal 304, the variable VR2 is represented as SDI signal 306, the variable VR3 is represented as SDI signal 308, and the variable VR4 is represented as SDI signal 310. Examples of variables VR1 through VR4 include frequency, power, real part of load impedance, and imaginary part of load impedance. Another example of the variables VR1 through VR4 includes frequency, amount of voltage, amount of current, and phase between voltage and current. Yet another example of the variables VR1 through VR4 includes frequency, amount of power delivered, and retracement. Another example of variables VR1 through VR4 includes frequency, amount of power delivered, and complex load impedance. Another example of variables VR1 through VR4 includes frequency and complex forward power, which includes the amount of voltage, the amount of current, and the phase between voltage and current. Yet another example of variables VR1 through VR4 includes frequency and complex reflection power, which includes the amount of voltage, the amount of current, and the phase between voltage and current. Another example of variables VR1 through VR4 includes frequency and complex V&I, which include the amount of current, the amount of voltage, and the phase between current and voltage.

In some embodiments, variables VR1 through VR4 are communicated between the PSPI of VMAP controller 208 and the PSPI of the RF generator controller. For example, four variables VR1 through VR4 are transmitted to PSPI 210 (FIG. 2A) and PSPI 203 via communication channels C1, C3, C5, and C6 and/or via communication channels C2, C4, C5, and C6. 2A) between. In addition, as another example, four variables VR1 through VR4 are transmitted to PSPI 212 (FIG. 2A) and PSPI via communication channels C10, C12, C14, and C15 and/or via communication channels C11, C13, C14, and C15. Between 205 (Fig. 2A).

The clock signal 302 is an example of a clock signal transmitted from the RF CTRL-CLK of a PSPI. For example, the clock signal 302 is transmitted from the RF CTRL-CLK of the PSPI 210 (FIG. 2A). As another example, the clock signal 302 is transmitted from the RF CTRL-CLK of the PSPI 212 (Fig. 2A).

In some embodiments, the PSPI of the VMAP controller 208 samples the SDI signals 304, 306, 308, and 310 at the rising edge of each clock cycle of the clock signal 302. For example, the bits of the SDI signals 304, 306, 308, and 310 are at the clock signal 302. The rising edge 312 of a clock cycle is sampled at the 2 MHz power readback SDI埠, 2MHz frequency readback SDI埠, 2MHz-Z real SDI埠, and 2MHz-Z imaginary SDI埠 of the PSPI 210 (Fig. 2A). And other bits of SDI signals 304, 306, 308, and 310 are sampled during the rising edge 314 of a clock cycle of subsequent clock signal 302. In some embodiments, instead of sampling the bits of SDI signals 304, 306, 308, and 310 at rising edge 312, PSPI of VMAP controller 208 samples SDI at the falling edge of each clock cycle of clock signal 302. Bits of signals 304, 306, 308, and 310.

In some embodiments, the PSPI of the RF controller transmits the bits of the SDI signals 304, 306, 308, and 310 at the rising edge of each clock cycle of the clock signal 302. For example, the bits of SDI signals 304, 306, 308, and 310 are transmitted from PSPI 203 (FIG. 2A) during 2 MHz-power readback SDO埠, 2 MHz during the rising edge 312 of a clock cycle of clock signal 302. - Frequency readback SDO埠, 2MHz-Z real readback SDO埠, and 2MHz-Z imaginary readback SDO埠. In some embodiments, instead of transmitting the bits of SDI signals 304, 306, 308, and 310 at rising edge 312, PSPI 203 transmits SDI signals 304, 306 at the falling edge of each clock cycle of clock signal 302, 308, and 310.

The sampling or transmission of SDI signals 304, 306, 308, and 310 synchronized with the clock signal 302 (e.g., simultaneous, etc.) is more efficient than sampling or transmitting a variable with a clock signal.

In various embodiments, a one-bit element of a variable (eg, bit B1, bit B2, bit B3, etc.) is mounted on the RF controller during a falling edge of a clock cycle of the clock signal 302. The PSPI of 252 (Fig. 2B) is set (e.g., transmitted, etc.), and during the rising edge of the clock cycle, the bit is latched (e.g., read, etc.) by the PSPI of host system 102. For example, during the falling edge of a clock cycle of the clock signal 302, a bit of a variable is set by a 埠 of the PSPI 203 (FIG. 2A), and during the rising edge of the clock cycle, This bit is latched by a 埠 of the PSPI 210.

In some embodiments, during a rising edge of a clock cycle of the clock signal 302, a bit of a variable is set by a 埠 of a PSPI mounted within the RF controller 252 (FIG. 2B). And during the falling edge of the clock cycle, the bit is hosted by the host A bit of a PSPI of system 102 is latched.

In some embodiments, during a previous edge (eg, rising edge, falling edge, etc.) of a clock cycle of the clock signal 302, a bit of a set point is installed in the host system 102 (FIG. 2A). A PSPI is set (e.g., transmitted, etc.) and is latched by a PSPI of the RF controller 252 during the next edge (e.g., falling edge, rising edge, etc.). For example, during the falling edge of a clock cycle of the clock signal 302, a bit of a variable is set by a bit of the PSPI 210 (FIG. 2A), and during the rising edge of the clock cycle, This bit is latched by a single bit of PSPI 203. The previous edge is before the next edge.

It should be noted that although FIG. 3A is described using SDI signals 304, 306, 308, and 310, in some embodiments, SDO signals transmitted via channels C2, C4, C11, and C13 (FIG. 1) are utilized. The clock signal 302 is sampled.

It should be further noted that although four variables are depicted in FIG. 3A, in some embodiments any other number of variables may be used, such as three, five, six, and the like.

Moreover, in several embodiments, each variable is an n-bit variable, where n is an integer, such as 12, 13, 14, and the like. In various embodiments, the frequency of data transmission of a variable is a fraction of the clock frequency of the clock signal 302, such as one-half, one-third, one-quarter, and the like. For example, the clock pulse of each of the two clock signals 302 transmits a data bit of a variable. As another example, to transmit 13 data bits of a variable, 26 clock pulses (eg, edges, etc.) are used. One clock edge is used to set a data bit, and another clock edge is used to latch the data bit. In some embodiments, the clock signal 302 is a 1 MHz clock signal, a 2 MHz clock signal, and the like. In various embodiments, the clock signal 302 has a frequency below 500 MHz.

Figure 3B depicts the difference between full parallel data transfer and PSP data transfer. As shown in the parallel chain 352, the data is transmitted completely in parallel, with each data bit being transmitted over a different communication channel. For example, when a variable has 13 bits and four variables are transferred between the host system 102 and the RF controller 252, 52 communication channels are required to transfer between the host system 102 and the RF controller 252. Variables VR1 to VR4. This full parallel Sending on the host system 102 and the RF controller 252 increases the real estate, such as the surface area of the semiconductor wafer, germanium, etc., and also increases the effective area between the host system 102 and the RF controller 252, such as wiring, etc. Wait. Also, full parallel transmission increases interference, signal integrity loss, etc. of signals transmitted on parallel chains 352. When the 52 bits of the four variables VR1 through VR4 are transmitted by the RF generator 252 to the host system 102 once (e.g., at a single clock edge, etc.), a fully parallel data set is transmitted.

In contrast, when four variables are transmitted on the communication channel at less than 52 bits at a time (e.g., 4 bits per clock edge, etc.), a smaller number of channels are used than for full parallel transmission. For example, four channels are used at a time to transfer four bits. In full parallel transmission, 52 channels are used to transmit 52 bits at a time. The reduced number of communication channels reduces the effective area used on host system 102 and RF controller 252 and also reduces the effective area between host system 102 and RF controller 252. In addition, the reduced number of communication channels reduces the probability of signal integrity loss of signals in the communication channel, the probability of interference, and the like.

It should be noted that when the variables VR1 through VR4 are transmitted through the four communication channels, the bits of the variables (e.g., variables VR1 through VR4) are sampled 13 times to capture all 52 bits of the variables VR1 through VR4. For example, four bits are sampled at one edge of the clock, one bit per variable, and four bits are sampled 13 times at 13 clock edges to sample 52 bits. When four bits are sampled at a clock edge, the sampled data is less than 52 bits, which is a fully parallel data set containing variables VR1 through VR4.

It should be noted that the quantities used herein, such as 13, 52, etc., are for illustrative purposes only and are not to be construed as limiting. For example, instead of 13, another number can be used, such as 10, 11, 12, 14, 15, 16, and the like.

4A is a block diagram of an embodiment of a host system 400 that is an example of a host system 102 (FIGS. 1 and 2). Host system 400 includes an FPGA 402 and a microprocessor 404. It should be noted that instead of FPGA 402, any other integrated circuit, such as an ASIC or the like, can be used. Moreover, instead of microprocessor 404, any other integrated circuit, such as an FPGA, ASIC, etc., can be used.

FPGA 402 includes a multi-SPI (MSPI, multiple SPI) 406, which is here Also known as PSPI. The MSPI 406 contains 27 pins, which contain 9 pins per PSPI. For example, MSPI 406 includes PSPI 210, PSPI 212, and PSPI 214 (Fig. 2A). MSPI 406 receives data from PSPI 203, 205, and 206 (Fig. 3A), such as power readback from an SDO, frequency readback from an SDO, real read back from a SDO, and from a The SDO埠 load impedance imaginary part is read back, variables, etc., and the data is transferred to the soft core DSP 408 and/or to the high speed buffer 410.

Soft core DSP 408 includes an RF transmission model that is a computer generated model of RF transmission line 130 (Fig. 1). For example, FPGA 402 implements an electronic circuit that includes components that are electronic components of RF transmission line 130, such as capacitors, inductors, and the like. To illustrate, when the RF transmission line 130 includes an inductor having an inductance L Henry and a capacitor having a capacitance C-farad, the soft core DSP 408 includes an inductor having an inductance L Henry and a capacitor having a capacitance C-farad. In addition, the FPGA 402 connects the components within the electronic circuit in the same manner as the electronic components are connected, such as in series, in parallel, and the like. For example, when an inductor is connected in parallel with a capacitor within RF transmission line 130, soft core DSP 408 includes an inductor in parallel with a capacitor.

In several embodiments, instead of the RF transmission model, an impedance matching model, or a combination of an impedance matching model and an RF transmission model, is included within the soft core DSP 408. The impedance matching model is implemented within the FPGA 402 based on the impedance matching circuit 120 (FIG. 1) in a manner similar to the RF transmission model generated from the RF transmission line 130.

The variables received by MSPI 406 are transmitted from MSPI 406 via high speed buffer 410 and high speed bus 412 to high speed port 415 of microprocessor 404. An example of a high speed bus includes a bus that transmits data at 500 MHz, 400 MHz, 300 MHz, 600 MHz, between 5 MHz and 500 MHz, and the like. These variables are passed to the SDD logic block 416 via the high speed port 415. A logic block is a computer program that is executed by more than one processor, such as SDD logic block 416, which is executed by microprocessor 404. In some embodiments, a logic block is implemented within an integrated circuit.

The SDD logic block 416 performs a statistical transformation on the variables received via the cache 415 during a time window (eg, 2 microseconds, 10 seconds, 5 seconds, 5 microseconds, etc.) to generate a system. Data. For example, SDD logic block 416 generates average, rolling variance, median, mode, standard deviation, maximum, minimum, and interquartile range (IQR, interquartile) from variables received via high speed 埠415. Range) and so on to generate statistics. To illustrate, SDD logic block 416 produces an average of a plurality of power values received via communication channel C10. In this example, the plurality of power values are received during a ten microsecond time window. As another example, SDD logic block 16 generates a median of a plurality of load impedance real value values received via communication channel C5. In this example, the plurality of load impedance values are received during a five microsecond time window.

As another example, a first weight is assigned to a first variance of a first variable value (eg, power amount, phase, etc.) received in a first time window. In this example, a second weighting is assigned to the second variance of the second variable received within the first time window, and so on until the Nth weight is assigned to the first time window. The Nth variation of the Nth variable, where N is an integer greater than zero. Moreover, in this example, the first rolling variance of the first time window is determined as a sum, the sum being the first product of the first weighting and the first variance, and the second weighting and the second variation The product of the two products, and so on, until the sum of the Nth product of the Nth weight and the Nth variance. It should be noted that in this example, a PSPI from the PSPI of the host system 102 receives the N-1th variable value from a PSPI of the RF controller 252, from the PSPI of the host system 102 from the PSPI of the RF controller 252. Before receiving the Nth variable. Similarly, the second rolling variance of a second time window is determined as the (NM) product of the (NM)th weighting and the (NM)th variance, and so on until the (N+P)th weighting and the (N+P) The sum of the (N+P) products of the variance, where P is an integer greater than zero. Also, in this example, the second time window overlaps the first time window. Various other examples of determining statistical data to implement SDD are described in U.S. Patent Provisional Application No. 61/737,623, filed on December 14, 2012, entitled "METHODS FOR COMPUTATION OF STATISTICS FOR STATISTICAL DATA DECIMATION", The entire contents of this disclosure are incorporated by reference in its entirety herein.

In several embodiments, SDD logic block 416 deletes any value of a variable received during the time window other than the statistical value of the variable. For example, SDD logic block 416 removes the imaginary part of the load impedance from the storage device within host system 400 except the median The value outside. As another example, SDD logic block 416 clears values of the frequency other than the mode from the storage device within host system 400. As yet another example, after determining the first rolling variance, the first through the N-M-1 variable values are deleted from more than one storage device of the host system 400, where M is an integer less than N. As another example, after determining the second rolling variance, the first rolling variance may be deleted from more than one storage device. In several embodiments, no decimation is performed in host system 102 (Figs. 1 and 2). In these embodiments, all of the variable values are stored within one or more storage devices of the host system 102, within the virtual machine, and the like.

The deviation compensation module 418 determines the amount of deviation based on the statistics to compensate for the deviation. For example, when it is determined that the statistical value is outside of the predetermined range, the deviation compensation module 418 adjusts the statistical value to within the range.

In some embodiments, the bias compensation module 418 determines a power and frequency based on the adjusted statistical values, and via a high speed 埠 415 for transmitting set points to the RF controllers 202, 204, and 206 (FIG. 2A), High speed bus 412, high speed 埠 410, MSPI 406, and communication channels (e.g., C2, C4, C11, C13, etc. (Fig. 2A)) for immediate control of system 100 (Fig. 1). In various embodiments, the offset compensation module 418 provides the power and frequency based on the adjusted statistics to a set of RF generators via the VME communication block 422, such as Ethernet, EtherCAT, USB. Parallel, parallel, and so on.

The microprocessor 404 includes an event/fault detection module 420 that is within the instant detection system 100 (FIG. 1) (eg, plasma chamber 128, impedance matching circuit 120, RF transmission line 130, RF generators 108, 112, 116, etc.) An event, such as a failure. For example, when the determined statistical value is outside of a predetermined range, the event/fault detection module 420 determines that an event has occurred within the system 100. The event occurs from the event/fault detection module 420 via the VME communication block 422 (eg, Ethernet communication block, EtherCAT communication block, USB port, network interface controller, serial port, parallel port, 2MHz Tx/Rx, 27MHz Tx/Rx, 60MHz Tx/Rx (FIG. 1), etc.) are transmitted to more than one device, such as RF generator 108, RF generator 112, RF generator 116, a remote computer system, etc. . Examples of remote computer systems include computers, servers, processors, mobile phones, smart phones, tablets, etc., which are added by a user. To operate. The user views the indication on a display device of the remote computer system (eg, a cathode ray tube display, a liquid crystal display device, a light emitting diode display device, a plasma display device, etc.), and may decide to take action to eliminate The fault.

4B is a block diagram of an embodiment of a host system 450 that is another example of a host system 102 (FIG. 1). Host system 450 is similar to host system 400 (FIG. 4A) except that host system 450 includes a microprocessor 452. Microprocessor 452 is similar to microprocessor 404 (FIG. 4A) except that microprocessor 452 includes a variable module 454.

The variable module 454 receives the RF transmission model via the high speed port 410, the high speed bus bar 412, and the high speed port 415, and receives variables from the MSPI 406 via the high speed port 410, the high speed bus bar 412, and the high speed port 415, such as load impedance, complex V&I. , complex voltage, complex current and so on. Variable module 454 determines variables at the output of soft core DSP 408 based on variables received from MSPI 406 and characteristics of the RF transmission model (eg, capacitance, impedance, etc.), such as complex V&I, complex voltage, wafer bias, Ion energy, plasma potential, complex current, load impedance, etc. For example, when the load impedance Z1 is received via communication channels C5 and C6 (FIG. 2A) and the impedance of the component of the RF transmission model is Z2, the variable module 454 determines the impedance system at the output of the RF transmission model. Directional sum of Z1 and Z2. As another example, when a complex V&I system is received via three communication channels and the complex V&I system of the RF transmission model is complex V&I2, the variable module 454 determines the complex V&I system V&I1 at the output of the RF transmission model. Orientation and orientation of V&I2.

The SDD logic block 416 receives the variables from the variable module 454 and determines a statistical value during the time window from the variables in a manner similar to that described above. In addition, the offset compensation module 418 receives the statistical values from the SDD logic block 416 and determines the offsets applicable to the plasma chamber 128 (FIG. 1) based on the statistical values. For example, when it is determined that the statistical value is outside a predetermined threshold, the deviation compensation module 418 adjusts the statistical value to be within the threshold. The offset compensation module 418 transmits the power and frequency derived from the adjusted statistics to more than one PSPI (FIG. 2A) of the one or more RF generator controllers 202, 204, and 206 in a manner similar to that described above. For example, the deviation compensation module 418 determines a power and frequency based on the adjusted statistical value, and passes the power and frequency via the high speed 埠415, the high speed bus 412, and the high speed. 埠 410, MSPI 406, and communication channels (eg, C2, C4, etc.) are provided to RF controller 202. As another example, the offset compensation module 418 provides the power and frequency based on the adjusted statistical value to the RF generator via the VME communication block 422, such as Ethernet, EtherCAT, USB. Parallel, parallel, and so on.

The event/fault detection module 420 detects an event within the system 100 (FIG. 1) based on the statistics received from the SDD logic block 416. For example, when it is determined that the statistical value is outside a predetermined threshold, the event/fault detection module 420 determines that an event has occurred within the system 100. The indication of the occurrence of the event is transmitted from the event/fault detection module 420 to more than one device via the VME communication block 422, such as the remote computer system, the RF generator 202, the RF generator 204, and the RF generator 206 (FIG. 2A). )and many more. The user views the indication on the display device of the remote computer system and may decide to take action to eliminate the failure.

5 is a diagram of graphs 502, 504, and 506 of an embodiment to illustrate that the variables help determine an event, such as a plasma unrestricted state within plasma chamber 128 (FIG. 1). Examples of other events include arcing, changes in load impedance, changes in the condition of the plasma chamber 128, and the like.

Graph 502 depicts a graph of wafer bias versus time, which is biased at the ESC. Graph 502 includes a curve 508 of wafer bias based on a model, such as an RF transmission model, an impedance matching model, and the like. Additionally, chart 502 includes a plot 510 of wafer bias measured by a sensor. It should be noted that a potential plasma unconstrained state is visible at the discontinuities in curves 508 and 510 in graph 502.

Graph 504 depicts when 2 MHz RF generator 108 (FIG. 1) is operating (eg, powered, etc.) and other RF generators (eg, 27 MHz RF generator 112 (FIG. 1), 60 MHz RF generator 116 (FIG. 1), etc. The graph of the root mean square (RMS) voltage versus time determined at the output of a model when it is not operational (eg, a power outage). In the graph 504, the discontinuity of the curve 505 is visible until there is a potential plasma unconstrained state.

Graph 506 depicts the amount of impedance at the output of soft core DSP 408 (Fig. 4A) with respect to time, depicts the amount of complex current (e.g., root mean square, etc.), and depicts the amount of power. Graph 506 includes a curve 512 depicting the amount of impedance at the output of soft core DSP 408 with respect to time. The graph 506 further includes a curve 514 that depicts the amount of complex current determined at the output of the soft core DSP 408 with respect to time. In addition, chart 506 includes a curve 516 that depicts the amount of power determined at the output of soft core DSP 408 with respect to time. Based on changes in the three RF parameters, such as an increase in the amount of impedance at the output of the soft core DSP 408, an increase in the amount of power, and a decrease in the amount of current, an event is determined, such as plasma is not limited. This event occurs when the three RF parameters are changed in the manner described above.

It has been noted that while the above embodiments are described in terms of parallel plate plasma chambers, in one embodiment, the above embodiments are applicable to other types of plasma chambers, such as inductively coupled plasma (ICP) reactors. a plasma chamber, a plasma chamber containing an electron cyclotron resonance (ECR) reactor, and the like. For example, RF generator 108 and RF generator 112 are coupled to an inductor within the ICP plasma chamber.

It should be noted that while the above embodiments relate to providing an RF signal to the lower electrode of the ESC and grounding the upper electrode, in several embodiments, the RF signal is provided to the upper electrode and the lower electrode of the ESC is grounded.

The embodiments described herein can be implemented in a variety of computer system configurations, including hand-held hardware units, microprocessor systems, microprocessor-based or programmable consumer electronic devices, mini computers, host computers, and the like. The embodiments can also be practiced in a distributed computing environment where multiple operations are performed by processing the hardware unit through the remote end of the network link.

In view of the above-described embodiments, it should be understood that the embodiments can be implemented using a variety of computers involved in the data stored in the computer system. These operations are physical operators that use physical quantities. Any of the operations described herein that form part of the embodiments are useful mechanical operations. These embodiments are also directed to hardware units or devices that perform these operations. The device can be specially constructed for special purpose computers. When defined as a special purpose computer, the computer may also perform other processing, program execution or routines that are not part of the special purpose and still be able to operate for that particular purpose. In some embodiments, such operations can be handled by a general purpose computer selectively activated or set using one or more computer programs stored in computer memory, cache memory, or one or more computer programs. When data is obtained over the Internet, it can be processed by other computers on the network, such as cloud computing resources.

One or more embodiments can also be fabricated as computer readable code on a non-transitory computer readable medium (eg, a storage device). The non-transitory computer readable medium is any data storage hardware unit that can store data, which can then be read by a computer system. Examples of non-transitory computer readable media include hard disk, network attached storage (NAS), ROM, RAM, compact disk read only memory (CD-ROM), recordable CD (CD-R), rewritable CD (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. The non-transitory computer readable medium can include computer readable tangible media distributed over a network connected computer system such that the computer readable code is stored and executed in a distributed fashion.

Although the above operations are described in a particular order, it should be understood that other housekeeping operations may be performed between the operations, or that the operations may be adjusted such that the operations occur at a different time, or may be distributed in a system. The system allows for the occurrence of processing operations at various time intervals associated with processing as long as the processing of the overlapping operations is performed in the desired manner.

One or more features from any of the embodiments can be combined with one or more of the features of any other embodiment without departing from the scope of the various embodiments of the present disclosure.

While the foregoing embodiments have been described in detail, the embodiments of the invention Therefore, the present embodiments are to be considered as illustrative and not restrictive,

102‧‧‧Host system

250‧‧‧ system

252‧‧‧ Controller

254‧‧‧ Bus Bar Interconnect Structure

254‧‧‧Sampling circuit

Claims (23)

A bus bar interconnect structure for interfacing a host system to a radio frequency (RF) generator connected to a plasma chamber, the bus bar interconnect structure comprising: a plurality of host ports, wherein the host system The first and second links are used to provide a power component setting and a frequency component setting to the RF generator, and the third, fourth, fifth, and sixth links of the host system are used to receive Four different variables of time variation; a plurality of generators, wherein the first and second axes of the RF generator are used to transmit a power back reading and a frequency back reading to the host system; and a sampler circuit integrated with the host system, the sampler circuit being configured to sample the third, fourth, fifth, and sixth sampling signals of the selected clock edge at the host system to capture The RF generator and operational status data of the plasma chamber. The busbar interconnection structure of claim 1, wherein the signals sampled by the third, fourth, fifth, and sixth ports of the host system are resampled a set number of times, Take a fully parallel data set. The busbar interconnect structure of claim 1, wherein the signals sampled at a clock edge are less than a fully parallel data set. The busbar interconnection structure of claim 1, wherein the seventh system of the host system is configured to provide a slave selection signal for selecting the RF generator to provide data to the RF generator or from the The RF generator reads the data, wherein the eighth system of the host system is configured to provide a clock signal to the RF generator, wherein the ninth node of the host system is used to connect a signal to the RF generator. The bus bar interconnection structure of claim 1, wherein the first system of the host system is a power set point serial data output port, wherein the second system of the host system is a frequency set point series Data output port, wherein the third system of the host system is a power readback serial data input port, wherein the fourth system of the host system is a frequency readback serial data input port, wherein the host system The fifth line is a load impedance real part serial data input port, and wherein the host The sixth line of the system is a load impedance imaginary part of the data input port. The busbar interconnect structure of claim 1, wherein the power component setting comprises a power amount, and the frequency component setting comprises a frequency value. For example, the busbar interconnection structure of claim 1 wherein the variables include: frequency, power, real part of the load impedance, and imaginary part of the load impedance; or frequency, voltage amount, current amount, and voltage and current Phase; or frequency, amount of power delivered, and gamma; or frequency, amount of power delivered, and complex load impedance; or frequency, and complex forward power; or frequency, and complex reflected power; or frequency And complex voltage and current. The busbar interconnect structure of claim 1, wherein the power back reading value comprises a power amount, and the frequency back reading value comprises a frequency amount. The busbar interconnect structure of claim 1, wherein the sampler circuit is located within the host system. A busbar interconnect structure as claimed in claim 1, wherein the selected clock edges comprise rising clock edges or falling clock edges. A busbar interconnect structure as claimed in claim 1, wherein a bit of a signal of one of the variables is set during a falling clock edge and latched during a rising edge. The busbar interconnect structure of claim 1, wherein the operational status data includes: data indicating whether there is a plasma unconstrained state within the plasma chamber, indicating whether there is an arc in the plasma chamber Information, or a combination thereof. The busbar interconnection structure of claim 1, wherein the operational status data is detected by a sensor of the RF generator. For example, the busbar interconnect structure of claim 1 further includes a plurality of communication channels, the RF generator and two additional RF generators are connected to the host system, and the RF generators are connected via nine communication channels. To the host system. A bus bar interconnect structure for interfacing a host system to a radio frequency (RF) generator coupled to a plasma chamber, the bus bar interconnect structure comprising: a first group of host ports, the first group The host system is configured to provide a power component setting and a frequency component setting to the RF generator, and the first group of hosts is configured to receive a plurality of different variables that change with time; a second group of generators Transmitting a power back reading value and a frequency back reading value to the host system; and a sampler circuit integrated with the host system, the sampler circuit being constructed at the selected clock edge at the A set of host sampling signals are taken to retrieve operational status data of the RF generator and the plasma chamber. For example, in the busbar interconnection structure of claim 15, wherein the signals sampled at the first group of host ports are resampled a set number of times to capture a fully parallel data set. A busbar interconnect structure as claimed in claim 15 wherein the signals sampled at a clock edge are less than a fully parallel data set. For example, the busbar interconnection structure of claim 15 wherein the variables include: frequency, power, real part of the load impedance, and imaginary part of the load impedance; or frequency, voltage amount, current amount, and voltage and current Phase; or frequency, amount of power delivered, and retracement; or frequency, amount of power delivered, and complex load impedance; or Frequency, and complex forward power; or frequency, and complex reflection power; or frequency, and complex voltage and current; or frequency, complex forward power, and complex reflection power; or frequency, complex voltage, and complex current. A plasma system comprising: a host system for providing a data signal; a radio frequency (RF) generator coupled to the host system, the RF generator for generating an RF signal based on the data signals; a matching circuit for matching the impedance of the RF generator with an impedance of a plasma chamber; an RF transmission line connecting the impedance matching circuit to the plasma chamber; and a bus interface for connecting the host system to The RF generator, the bus interface includes: a first group of hosts, the first group of hosts is configured to provide a power component setting and a frequency component setting to the RF generator, and the first group of hosts The tether is configured to receive a plurality of different variables that vary over time; a second set of generators 传送 for transmitting a power back reading value and a frequency back reading value to the host system; and a sampler circuit In conjunction with the host system, the sampler circuit is configured to sample signals at the first set of host ports at selected clock edges to retrieve operational status data of the RF generator and the plasma chamber. The plasma system of claim 19, wherein the signals sampled at the first group of host ports are resampled a set number of times to capture a fully parallel data set. A plasma system as claimed in claim 19, wherein the signals sampled at a clock edge are less than a fully parallel data set. For example, the plasma system of claim 19, wherein the variables include: Frequency, power, real part of load impedance, and imaginary part of load impedance; or frequency, amount of voltage, amount of current, and phase between voltage and current; or frequency, amount of power delivered, and gamma; or frequency , the amount of power delivered, and complex load impedance; or frequency and complex forward power; or frequency and complex reflected power; or frequency, and complex voltage and current; or frequency, complex forward power, and complex reflected power; or frequency , complex voltage, and complex current. The plasma system of claim 19, wherein the host system comprises a statistical data extraction module, wherein the statistical data extraction module is configured to calculate statistical data based on the variables, and the statistical data extraction module deletes the data. Variable data for statistics.