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TW201444296A - Frequency synthesis using a phase locked loop - Google Patents

Frequency synthesis using a phase locked loop Download PDF

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Publication number
TW201444296A
TW201444296A TW102141222A TW102141222A TW201444296A TW 201444296 A TW201444296 A TW 201444296A TW 102141222 A TW102141222 A TW 102141222A TW 102141222 A TW102141222 A TW 102141222A TW 201444296 A TW201444296 A TW 201444296A
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TW
Taiwan
Prior art keywords
frequency
circuit
phase
signal
local oscillator
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TW102141222A
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Chinese (zh)
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TWI650948B (en
Inventor
Ismail Lakkis
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Adeptence Llc
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B25/00Simultaneous generation by a free-running oscillator of oscillations having different frequencies
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B19/00Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A phase locked loop circuit comprises a phase/frequency detector, a voltage-controlled oscillator (VCO), and a divider chain in a feedback path coupling the VCO output to the phase/frequency detector. The divider chain comprises a plurality of sequentially connected divider circuits and a plurality of local oscillator outputs interspersed at different locations within the divider chain, which enables the circuit to simultaneously output multiple oscillator signals having different frequencies.

Description

使用鎖相迴路之頻率合成 Frequency synthesis using phase-locked loops

本發明之實施例係相關於鎖相迴路(PLL),特別是可以使用於無線電接收機和發送機之本地振盪器之鎖相迴路。 Embodiments of the present invention are related to phase-locked loops (PLLs), particularly phase-locked loops that can be used in local oscillators for radio receivers and transmitters.

本申請案主張於2012年11月14日申請美國專利申請案號61/726,166之優先權。 The present application claims priority to U.S. Patent Application Serial No. 61/726,166, filed on Nov. 14, 2012.

一鎖相迴路是一控制系統,其產生一具有與一輸入參考信號相關之固定相位的振盪器信號。鎖相迴路被廣泛用於各種應用中,例如,無線電、電信通訊、計算機、和其它電子應用。一鎖相迴路包含一電壓控制振盪器,其基於一控制電壓產生該振盪器信號,以及一相位檢測器,其用於比較該振盪器信號和該輸入參考信號之相位,並基於該檢測相位差產生一誤差信號。 A phase locked loop is a control system that produces an oscillator signal having a fixed phase associated with an input reference signal. Phase-locked loops are widely used in a variety of applications, such as radio, telecommunications, computers, and other electronic applications. A phase locked loop includes a voltage controlled oscillator that generates the oscillator signal based on a control voltage, and a phase detector for comparing phases of the oscillator signal and the input reference signal, and based on the detected phase difference An error signal is generated.

該鎖相迴路還包括一迴路濾波器,其用於過濾該誤差信號,並產生被該電壓控制振盪器使用之控制電壓。該鎖相迴路之迴路濾波器,其可將通過頻帶外之頻率衰減,被選定用於將來自該相位檢測器之高頻分量之輸出衰減。 The phase locked loop also includes a loop filter for filtering the error signal and generating a control voltage for use by the voltage controlled oscillator. A loop filter of the phase locked loop that attenuates frequencies outside the outband and is selected to attenuate the output of the high frequency components from the phase detector.

一鎖相迴路可以被用於輸出一振盪信號,以驅動在一無線電通信系統中之發送器或接收器中所使用之頻率混合器。例如,該頻率混合 器可被用於將一傳送鏈中之信號做升頻轉換,及/或將一接收鏈中之信號做降頻轉換。在無線電通信中,在不同頻帶中進行操作通常是有利的。因為它可以不需要實際地為每一個所需要之頻帶採用不同的無線電前端(radio front end),可編程之振盪器通常被採用於發送器中。 A phase locked loop can be used to output an oscillating signal to drive a frequency mixer used in a transmitter or receiver in a radio communication system. For example, the frequency mix The device can be used to upconvert the signals in a transmission chain and/or downconvert the signals in a receive chain. In radio communications, it is often advantageous to operate in different frequency bands. Because it does not require the actual use of a different radio front end for each of the required frequency bands, a programmable oscillator is typically employed in the transmitter.

由該鎖相迴路輸出之該訊號頻率,其可藉由改變該參考信號之頻率而改變。然而,由於該參考信號通常是由一非常穩定之振盪器產生,且其頻率可以不被改變,可在該回授迴路中,至少提供一個除頻器,因此可以在不改變該參考信號之頻率下,將該鎖相迴路之輸出的頻率改變。 The signal frequency output by the phase locked loop can be changed by changing the frequency of the reference signal. However, since the reference signal is usually generated by a very stable oscillator and its frequency may not be changed, at least one frequency divider may be provided in the feedback loop, so the frequency of the reference signal may not be changed. Next, the frequency of the output of the phase locked loop is changed.

在其他系統中,該迴路濾波器是一可編程之數位濾波器,其濾波係數可以由軟體控制而改變。在一第一射頻通信頻帶中,一第一組濾波器係數將產生一本地振盪器信號,而且,如果在一第二射頻通信頻帶中,一本地振盪器信號是必需的,則一第二組濾波器係數將被使用。 In other systems, the loop filter is a programmable digital filter whose filter coefficients can be changed by software control. In a first RF communication band, a first set of filter coefficients will produce a local oscillator signal, and if a local oscillator signal is required in a second RF communication band, then a second set The filter coefficients will be used.

該無線電收發機除了需要對頻率靈敏外,通常還需要同時提供數個具有不同頻率之時序信號。例如,類比-數位轉換通常需要一不同於該振盪器頻率之時脈頻率,以用於做降頻轉換。另外,該些其他之時脈頻率可能依附於該發送器所使用之頻帶而改變。在該領域中,這些和其它之需求,可透過本發明之各觀點而解決之。 In addition to being sensitive to frequency, the transceiver typically also needs to provide several timing signals with different frequencies. For example, an analog-to-digital conversion typically requires a clock frequency different from the oscillator frequency for down conversion. Additionally, the other clock frequencies may vary depending on the frequency band used by the transmitter. These and other needs in the art can be solved by the various aspects of the present invention.

前述為一總結,所以包含簡化,概括及省略細節。因此,熟習該項技術者將理解,該總結僅為說明性,而非意圖以任何方式限制之。於此所描述之其它觀點、發明之特徵、與該裝置及/或方法之優點,其如在申請專利範圍中單獨之定義,將被列舉於此之非限制性的詳細描述而變得 顯而易見。 The foregoing is a summary, so includes simplifications, generalizations, and omit details. Therefore, it will be understood by those skilled in the art that the summary is merely illustrative and is not intended to be limiting in any way. Other aspects, features of the invention, and advantages of the device and/or method described herein, as defined in the scope of the claims, are hereby incorporated by reference. Obvious.

根據本發明之各個觀點,提供之系統及方法用於一鎖相迴路,其能同時輸出多個振盪信號,而且每一個振盪信號都具有不同之頻率。 In accordance with various aspects of the present invention, systems and methods are provided for a phase locked loop that can simultaneously output a plurality of oscillating signals, each having a different frequency.

在本發明的一個觀點,一鎖相迴路電路包括一相位/頻率檢測器,一電荷泵,一迴路濾波器,一電壓控制振盪器,一在將該電壓控制振盪器之輸出端與該相位/頻率檢測器耦合之回授路徑中的序列連接之除頻器鏈。該除頻器鏈包括多個除頻器電路,以及多個分佈在該除頻器鏈中,不同位置之本地振盪器的輸出端。該除頻器鏈至少包括一第一除頻器電路和一第二除頻器電路。一第一本地振盪器之輸出端,被耦合在該第一除頻器電路之前,而且一第二本地振盪器之輸出端,被耦合在該第二除頻器電路之前。該除頻器電路可包括一固定除頻器與可變除頻器之組合。 In one aspect of the invention, a phase locked loop circuit includes a phase/frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and an output of the voltage controlled oscillator and the phase/ A sequence-connected divider chain in the feedback path coupled to the frequency detector. The frequency divider chain includes a plurality of frequency divider circuits, and a plurality of output terminals of the local oscillator distributed in different positions of the frequency divider chain. The frequency divider chain includes at least a first frequency divider circuit and a second frequency divider circuit. An output of a first local oscillator is coupled in front of the first frequency divider circuit, and an output of a second local oscillator is coupled in front of the second frequency divider circuit. The frequency divider circuit can include a combination of a fixed frequency divider and a variable frequency divider.

在本發明的另一個觀點,提供一種方法,可由一鎖相迴路同時產生多個參考頻率。該方法包括將一參考信號插入至該鎖相迴路,在該鎖相迴路產生一電壓控制振盪信號,輸出一具有一第一頻率之第一本地振盪器信號,在該鎖相迴路之一回授路徑中,將該第一本地振盪器信號之頻率除頻,以產生一具有一第二頻率之第二本地振盪器信號,該第二頻率不同於該第一頻率,以及由該回授路徑輸出該第二本地振盪器信號。將該本地振盪器信號除頻可以包括使用一固定除頻器和可選擇或可變除頻器之組合。一個或多個該本地振盪器信號可被使用於升頻轉換及/或降頻轉換過程中之混合。一個或多個該本地振盪器信號可被用於其它發送器之操作,例如一使用於一類比至數位轉換中之時脈信號。但應當理解,在一個觀點或實施例中所描述之特徵可以被其它所描述之觀點和實施例中採用。 In another aspect of the invention, a method is provided for simultaneously generating a plurality of reference frequencies from a phase locked loop. The method includes inserting a reference signal into the phase locked loop, generating a voltage controlled oscillating signal in the phase locked loop, outputting a first local oscillator signal having a first frequency, and feeding back one of the phase locked loops In the path, the frequency of the first local oscillator signal is divided to generate a second local oscillator signal having a second frequency different from the first frequency and output by the feedback path The second local oscillator signal. Dividing the local oscillator signal can include using a combination of a fixed frequency divider and a selectable or variable frequency divider. One or more of the local oscillator signals can be used in a mix of up-conversion and/or down-conversion processes. One or more of the local oscillator signals can be used for operation of other transmitters, such as a clock signal for use in a analog to digital conversion. It should be understood, however, that features described in one aspect or embodiment may be employed in other described aspects and embodiments.

本發明其它之特徵和優點,都將在下面的描述及各部分闡明,而且從該描述中或者透過本發明之實施而學習,將會是顯而易見的。本發明之特徵和優點可以藉由附屬之申請專利範圍中所特別指出之工具和組合而被實現和獲得。本發明之這些和其它特徵,從下面的描述和附屬之申請專利範圍中將會變得更加顯而易見,或者透過如本發明之實施而學習。 Other features and advantages of the invention will be set forth in the description and in the description which The features and advantages of the invention are realized and attained by the <RTIgt; These and other features of the present invention will become more apparent from the following description and appended claims.

102‧‧‧天線 102‧‧‧Antenna

103‧‧‧射頻收發機 103‧‧‧RF Transceiver

104‧‧‧基頻處理器 104‧‧‧Baseband processor

105‧‧‧接收鏈 105‧‧‧Receiving chain

108‧‧‧雙工器 108‧‧‧Duplexer

109‧‧‧匹配網路 109‧‧‧matching network

110‧‧‧低雜訊放大器 110‧‧‧Low noise amplifier

111、118‧‧‧混合器 111, 118‧‧‧ Mixer

112‧‧‧基頻濾波器 112‧‧‧ fundamental frequency filter

113‧‧‧類比/數位轉換器 113‧‧‧ Analog/Digital Converter

114‧‧‧本地振盪器 114‧‧‧Local Oscillator

115‧‧‧數位/類比轉換器 115‧‧‧Digital/Analog Converter

116‧‧‧傳送鏈 116‧‧‧Transport chain

117‧‧‧基頻濾波器 117‧‧‧ fundamental frequency filter

119‧‧‧本地振盪器 119‧‧‧Local Oscillator

120‧‧‧驅動放大器 120‧‧‧Drive Amplifier

121‧‧‧外部功率放大器 121‧‧‧External Power Amplifier

125‧‧‧匯流排介面 125‧‧‧ bus interface

200‧‧‧參考訊號產生器/晶體振盪器電路 200‧‧‧Reference signal generator/crystal oscillator circuit

201‧‧‧相位/頻率檢測器 201‧‧‧ phase/frequency detector

202‧‧‧電荷泵 202‧‧‧Charge pump

203‧‧‧迴路濾波器 203‧‧‧ Loop Filter

204‧‧‧電壓控制振盪器 204‧‧‧Voltage Controlled Oscillator

205、206、207‧‧‧除2除頻器電路 205, 206, 207‧‧‧ except 2 frequency divider circuit

208‧‧‧可變除頻器電路 208‧‧‧Variable frequency divider circuit

209‧‧‧數位/類比轉換器、類比/數位轉換器 209‧‧‧Digital/analog converters, analog/digital converters

210‧‧‧除頻器電路 210‧‧‧Densor circuit

218‧‧‧控制介面 218‧‧‧Control interface

401‧‧‧晶體振盪器 401‧‧‧ crystal oscillator

402‧‧‧除頻器電路 402‧‧‧Deleber circuit

為了描述可以獲取本發明上述之列舉、其它特徵及優點之方法,一更具體對本發明以上簡述之說明,將參照特定觀點而被呈現,其將被說明於附圖中。該些附圖僅描述了本發明之典型觀點,但不因此而被認為是對其範圍的限制。本發明之各個觀點將透過使用該些附圖而進行特定而詳細之說明。 The description of the above summary of the present invention is set forth with particular reference The drawings merely depict typical aspects of the invention, but are not to be construed as limiting the scope thereof. The various aspects of the present invention will be described in detail and by way of the drawings.

圖1是一採用本發明之觀點的射頻收發機之方塊圖。 1 is a block diagram of a radio frequency transceiver employing the perspective of the present invention.

圖2是一根據本發明之一個觀點的一本地振盪器電路之方塊圖。 2 is a block diagram of a local oscillator circuit in accordance with an aspect of the present invention.

圖3是一根據本發明之觀點,相對應於一配置之鎖相迴路功能的操作值表。 3 is an operational value table corresponding to a configuration of a phase locked loop function in accordance with the teachings of the present invention.

圖4是一根據本發明之一個觀點的一本地振盪器電路之方塊圖。 4 is a block diagram of a local oscillator circuit in accordance with an aspect of the present invention.

圖5是一根據本發明之一個觀點的方法流程圖。 Figure 5 is a flow diagram of a method in accordance with one aspect of the present invention.

本發明之各個觀點描述如下。顯而易見的,本文於此之教導可以廣泛之各種不同形式被實施,而且於此所公開之任何特定結構,功能或兩者,僅為代表性之實施例。基於本文於此之教導,熟習該項技術者應當理解,本文於此揭露之一觀點可以單獨地被實現且與其他任何其它之觀 點無關,而且其中兩個或兩個以上之該些觀點,可以各種方式進行組合。例如,使用本文所述之任一數量的觀點,一裝置可以被實現或一方法可以被實施。相對於一個觀點中所描述的任何特徵,可以被採用於本發明之任一其他之觀點中。此外,使用其它結構,功能,或者結構外加功能,或一個或多個以上於此所闡述之觀點,一裝置可以被實現或一方法可以被實施。 The various aspects of the invention are described below. It is apparent that the teachings herein may be embodied in a wide variety of different forms, and any particular structure, function, or both disclosed herein are merely representative embodiments. Based on the teachings herein, those skilled in the art will appreciate that one aspect of the disclosure herein can be implemented separately and in any other context. Points are irrelevant, and two or more of these views can be combined in various ways. For example, a device may be implemented or a method may be implemented using any number of the aspects described herein. Any of the features described in relation to one aspect may be employed in any other aspect of the invention. In addition, a device may be implemented or a method may be implemented using other structures, functions, or structural additional functions, or one or more of the aspects set forth herein.

為解釋之目的,在下面的描述中,提出許多具體的細節以便於提供對本發明的徹底理解。然而應當理解,於此所示出和描述之特定觀點,並非意圖去限制本發明於任何特定形式,相反的,本發明係為涵蓋所有落入該申請專利範圍內之所有修改,等同物和替代物。 In the following description, numerous specific details are set forth in the It should be understood, however, that the invention is not intended to be limited to the specific scope of the invention. Things.

本發明針對無線通信裝置所需之頻率合成的技術。將更詳細地描述如下,該合成器電路提供了一彈性且可編程之振盪器,其可提供給一典型之無線通信裝置所需之一寬懬範圍的頻率。 The present invention is directed to techniques for frequency synthesis required by wireless communication devices. As will be described in more detail below, the synthesizer circuit provides a resilient and programmable oscillator that provides a wide range of frequencies required for a typical wireless communication device.

圖1是一採用本發明之觀點的射頻收發機之方塊圖。該收發機包括一接收鏈105,一第一本地振盪器114,一傳送鏈116,以及一第二本地振盪器119。在本發明之另一觀點中,一單一之本地振盪器(未示出)可同時該供應接收鏈105和該傳送鏈116兩者。 1 is a block diagram of a radio frequency transceiver employing the perspective of the present invention. The transceiver includes a receive chain 105, a first local oscillator 114, a transmit chain 116, and a second local oscillator 119. In another aspect of the invention, a single local oscillator (not shown) can simultaneously supply both the receive chain 105 and the transmit chain 116.

在接收模式中,一無線電信號由一天線102接收。該接收信號通過一雙工器108,一匹配網絡109,和該接收鏈105。在該接收鏈105中,該接收之信號由一低雜訊放大器(LNA)110放大,並由一混合器111將頻率做降頻轉換。該所得之降頻轉換信號經由一基頻濾波器112濾波,並傳遞至一基頻處理器104,例如一數位基頻集成電路。在基頻處理器104中,一類比-數位轉換器113將該信號轉換成數位之形式,並將該所得之 數位訊息,由該基頻處理器104中之數位電路(未示出)處理。該基頻處理器104,可以藉由控制提供給該混合器111之該本地振盪器114之信號的頻率來調整接收器。 In the receive mode, a radio signal is received by an antenna 102. The received signal passes through a duplexer 108, a matching network 109, and the receive chain 105. In the receive chain 105, the received signal is amplified by a low noise amplifier (LNA) 110 and the frequency is downconverted by a mixer 111. The resulting downconverted signal is filtered by a baseband filter 112 and passed to a baseband processor 104, such as a digital baseband integrated circuit. In the baseband processor 104, an analog-to-digital converter 113 converts the signal into a digital form and the resulting The digital message is processed by a digital circuit (not shown) in the baseband processor 104. The baseband processor 104 can adjust the receiver by controlling the frequency of the signal provided to the local oscillator 114 of the mixer 111.

在傳送模式中,傳送之數位訊息將由該基頻處理器104中之一數位-類比轉換器(DAC)115轉換成類比形式,並提供至該傳送鏈116。一基頻濾波器117將過濾出來自於該數位-類比轉換過程中之雜訊。一耦合至該本地振盪器119之混合器方塊118,將該濾波信號做升頻轉換成一高頻信號。驅動放大器(DA)120和一外部功率放大器(PA)121放大該高頻信號以驅動天線102,因此使得一無線電信號由天線102傳送。該基頻處理器104還可以控制由該本地振盪器119提供之一本地振盪信號的頻率至該混合器118。例如,該基頻處理器104可以藉由發送控制信號控制該本地振盪器114和119,而該控制信號經由與該本地振盪器114和119耦合之一匯流排介面125。 In the transmit mode, the transmitted digital message will be converted to an analog form by a digital-to-analog converter (DAC) 115 in the baseband processor 104 and provided to the transport chain 116. A fundamental frequency filter 117 will filter out the noise from the digital-to-analog conversion process. A mixer block 118 coupled to the local oscillator 119 converts the filtered signal into a high frequency signal. A driver amplifier (DA) 120 and an external power amplifier (PA) 121 amplify the high frequency signal to drive the antenna 102, thereby causing a radio signal to be transmitted by the antenna 102. The baseband processor 104 can also control the frequency of one of the local oscillator signals provided by the local oscillator 119 to the mixer 118. For example, the baseband processor 104 can control the local oscillators 114 and 119 by transmitting control signals that are coupled to one of the busbar interfaces 125 via the local oscillators 114 and 119.

圖2是一根據本發明之一個觀點的一本地振盪器電路之方塊圖,可被應用於該本地振盪器114與119中。該本地振盪器電路可以包括一參考信號產生器200(如一晶體振盪器電路)和一鎖相迴路(PLL)電路。該鎖相迴路包括一相位/頻率檢測器201,一電荷泵202,一迴路濾波器203,一電壓控制振盪器(VCO)204,以及一包括一序列連接之除頻器鏈的回授路徑,其耦合該電壓控制振盪器204之輸出端至該相位/頻率檢測器(PFD)201。 2 is a block diagram of a local oscillator circuit that can be applied to the local oscillators 114 and 119 in accordance with an aspect of the present invention. The local oscillator circuit can include a reference signal generator 200 (such as a crystal oscillator circuit) and a phase locked loop (PLL) circuit. The phase locked loop includes a phase/frequency detector 201, a charge pump 202, a loop filter 203, a voltage controlled oscillator (VCO) 204, and a feedback path including a sequence of connected frequency divider chains. It couples the output of the voltage controlled oscillator 204 to the phase/frequency detector (PFD) 201.

在本發明之一個觀點,該除頻器鏈包括除2之除頻器電路205,206,和207,其中每一個皆提供一固定的除數2。該除頻器鏈還包括 一可變除頻器電路208,其基於來自一控制介面218之控制訊號,而提供了一可選擇之除數21,25,或29。在本發明之其它觀點中之除頻器鏈,可包括其它除頻器電路之組合。 In one aspect of the invention, the frequency divider chain includes divide by two circuit breaker circuits 205, 206, and 207, each of which provides a fixed divisor of two. The frequency divider chain also includes A variable frequency divider circuit 208 provides a selectable divisor 21, 25, or 29 based on control signals from a control interface 218. The frequency divider chain in other aspects of the invention may include a combination of other frequency divider circuits.

該晶體振盪器電路200輸出一穩定和固定之參考時脈信號SREF,其被耦合至一相位/頻率檢測器201之第一輸入端。除此之外,從該鎖相迴路之回授迴路的一回授信號SFB被耦合至一該相位/頻率檢測器201的第二輸入端。 The crystal oscillator circuit 200 outputs a stable and fixed reference clock signal S REF that is coupled to a first input of a phase/frequency detector 201. In addition to this, a feedback signal S FB from the feedback loop of the phase locked loop is coupled to a second input of the phase/frequency detector 201.

該相位/頻率檢測器201將輸出一信號,該信號代表介於該參考信號SREF和該回授信號SFB間之相位及/或頻率之差值。該相位/頻率檢測器201之輸出信號通過該電荷泵202,並且在它被耦合至該電壓控制震盪器204作為控制信號之前,由該迴路濾波器203濾波。該控制信號被該電壓控制振盪器204用以調制該電壓控制震盪器204之輸出信號的頻率。 The phase/frequency detector 201 will output a signal representative of the difference between the phase and/or frequency between the reference signal S REF and the feedback signal S FB . The output signal of the phase/frequency detector 201 passes through the charge pump 202 and is filtered by the loop filter 203 before it is coupled to the voltage controlled oscillator 204 as a control signal. The control signal is used by the voltage controlled oscillator 204 to modulate the frequency of the output signal of the voltage controlled oscillator 204.

在一個觀點中,由該電壓控制震盪器204所輸出之第一本地振盪器信號SLO1,可以被提供至一混合器,如混合器111或118。該第一本地振盪器信號SLO1被耦合至該回授迴路之該除頻器鏈,並由固定除頻器電路205進行第一次除頻。除頻器電路205產生一輸出信號,其可包括一第二本地振盪器信號SL02。該信號SL02可視需要地被提供至一混合器,如混合器111或118。該固定除頻器電路206的頻率將來自該除頻器電路205之輸出信號除頻,以產生一時序信號,其可被使用於一類比數位轉換器和一數位類比轉換器兩者或兩者之一,如一ADC/DAC電路209。例如,該時序信號,被標記為SADC,可被使用於基頻取樣處理中,如在該ADC/DAC 209中之一類比-數位轉換。該ADC/DAC 209可以是在圖1中所示之該基頻處理器104 中的該ADC 113和該DAC 115。 In one aspect, the first local oscillator signal S LO1 output by the voltage controlled oscillator 204 can be provided to a mixer, such as mixer 111 or 118. The first local oscillator signal S LO1 is coupled to the divider chain of the feedback loop and is first divided by the fixed frequency divider circuit 205. The frequency divider circuit 205 produces an output signal that can include a second local oscillator signal S L02 . This signal S L02 can optionally be supplied to a mixer, such as mixer 111 or 118. The frequency of the fixed frequency divider circuit 206 divides the output signal from the frequency divider circuit 205 to generate a timing signal that can be used for both or an analog converter and a digital analog converter. One, such as an ADC/DAC circuit 209. For example, the timing signal, labeled S ADC , can be used in the baseband sampling process, such as analog-to-digital conversion in the ADC/DAC 209. The ADC/DAC 209 can be the ADC 113 and the DAC 115 in the baseband processor 104 shown in FIG.

藉由在一鎖相迴路之回授迴路中提供一除頻器鏈,並且提供穿插於除頻器鏈中(如在除頻器電路205及/或除頻器電路206之前或之後)不同位置之多個輸出端,該無線電發送器使用之不同的時序信號,即可透過一單一之鎖相迴路而同時產生。此外,一來自該回授迴路之輸出信號可以通過該除頻器鏈外部之一除頻器產生其它之時序信號。例如,由固定除頻器電路210除頻之信號SADC,可產生一時脈信號SCLK,其可被用於該收發機中其它數位信號之處理操作。 A divider chain is provided in a feedback loop of a phase locked loop and is provided in various locations interspersed in the frequency divider chain (e.g., before or after the frequency divider circuit 205 and/or the frequency divider circuit 206) The plurality of outputs, the different timing signals used by the radio transmitter can be simultaneously generated through a single phase-locked loop. In addition, an output signal from the feedback loop can generate other timing signals through a divider external to the divider chain. For example, the signal S ADC , which is divided by the fixed frequency divider circuit 210, can generate a clock signal S CLK that can be used for processing operations of other digital signals in the transceiver.

由除頻器206所輸出之該信號SADC之頻率,在被可變除頻器電路208除頻之前,先被固定除頻器207除頻。該控制介面218由多個整數除頻值(例如其值為21,25,和29)選擇用於選取該回授信號SFB之頻率。其結果是,由該電壓控制振盪器所輸出之信號SLO1頻率,經由選擇一不同之整數除頻值至該可變除頻器電路208而將被改變。同樣地,該回授迴路中之其他輸出信號SLO2和SADC以及SCLK之頻率,藉由選取除頻器208所採用之該整數值,是可以被選擇的。但應理解,本發明之其它觀點可以採用其他替代之除頻值,並且在一些觀點,該除頻器鏈可以包括多個可變除頻器電路。 The frequency of the signal S ADC output by the frequency divider 206 is first divided by the fixed frequency divider 207 before being divided by the variable frequency divider circuit 208. The control interface 218 is selected by a plurality of integer divide values (e.g., values 21, 25, and 29) for selecting the frequency of the feedback signal S FB . As a result, the frequency of the signal S LO1 output by the voltage controlled oscillator will be changed by selecting a different integer divide value to the variable frequency divider circuit 208. Similarly, the frequency of the other output signals S LO2 and S ADC and S CLK in the feedback loop can be selected by selecting the integer value used by the frequency divider 208. However, it should be understood that other alternatives of the frequency division values may be employed in other aspects of the invention, and in some aspects the frequency divider chain may include a plurality of variable frequency divider circuits.

在本發明的一個觀點,在該回授迴路中之該除頻器鏈可被配置成一收發機在不同之頻帶中進行操作(例如,在不同的載波頻率,fC),其中一部分之該頻譜被劃分成相等頻寬之頻道。例如,該可變除頻器電路208可以包括除頻值及/或可選擇之該除頻器鏈中該本地振盪器的輸出位置,而產生一組具有不同頻率之第一本地振盪訊號SLO1,以及具有與其配對 之一組大致相同之第二本地振盪器信號SLO2,SCLK及/或SADCIn one aspect of the invention, the frequency divider chain in the feedback loop can be configured such that a transceiver operates in a different frequency band (e.g., at a different carrier frequency, f C ), a portion of which spectrum Channels that are divided into equal bandwidths. For example, the variable frequency divider circuit 208 can include a frequency division value and/or an optional output position of the local oscillator in the frequency divider chain to generate a set of first local oscillation signals S LO1 having different frequencies. And a second local oscillator signal S LO2 , S CLK and/or S ADC having substantially the same group as its pair.

圖3是一相對應於圖2中所示之裝置功能的操作值表。在該表中的所有值是基於一參考信號SREF之40MHz頻率,而且固定除頻器205-207之除頻值等於2。第一列(標示為“BW”)使用MHz顯示頻寬值,其對應於信號SADC頻率值之一半。第二列(標示為“CLK”)使用MHz顯示時脈頻率值,其為該信號SCLK之頻率。該第四列(標示為“fC”)顯示在該收發機中所處理之一無線電信號的中心頻率。第四列中之前三行的值是電壓控制振盪器204之輸出信號SLO1頻率,而第四列之第四行中是在固定除頻器205之後的該信號SL02之頻率。第二列(標示為“fmin”)和第四列(標示為“fmax”)是在該發送器中被處理之信號的最低和最高頻率。該最小和最大頻率係相關於頻寬及中心頻率。第六列(標示為“N”)是在該回授迴路中之所有除頻器鏈的總整數除頻值,其是由該除頻器鏈中之該除頻器205-208所產生。該值可由該可變除頻器208提供不同之除頻值的結果而不同。第七列(標示為“M”)是介於該電壓控制振盪器204之輸出與該時脈訊號SCLK輸出之間的一序列除頻器205、206和210之總整數除頻值。由於該些除頻器205,206,和210為相對於除頻整數值為2、2和8之固定除頻器,所以在第七列中之值皆為32。 Figure 3 is a table of operational values corresponding to the function of the apparatus shown in Figure 2. All values in the table are based on a 40 MHz frequency of a reference signal S REF , and the demultiplexer values of the fixed frequency dividers 205-207 are equal to two. The first column (labeled "BW") uses the MHz display bandwidth value, which corresponds to one-half of the signal S ADC frequency value. The second column (labeled "CLK") uses MHz to display the clock frequency value, which is the frequency of the signal S CLK . The fourth column (labeled "f C ") shows the center frequency of one of the radio signals processed in the transceiver. The values of the first three rows in the fourth column are the output signal S LO1 frequency of the voltage controlled oscillator 204, and the fourth row of the fourth column is the frequency of the signal S L02 after the fixed frequency divider 205. The second column (labeled "f min ") and the fourth column (labeled "f max ") are the lowest and highest frequencies of the signal being processed in the transmitter. The minimum and maximum frequencies are related to the bandwidth and center frequency. The sixth column (labeled "N") is the total integer divide value of all the divider chains in the feedback loop, which is generated by the frequency dividers 205-208 in the divider chain. This value may be different as a result of the variable frequency divider 208 providing different frequency division values. The seventh column (labeled "M") is the total integer divide value of a sequence of frequency dividers 205, 206, and 210 between the output of the voltage controlled oscillator 204 and the output of the clock signal S CLK . Since the frequency dividers 205, 206, and 210 are fixed frequency dividers with respect to the divided integer values of 2, 2, and 8, the values in the seventh column are all 32.

在根據本發明的一個觀點,一40MHz之參考信號SREF頻率是由該參考信號產生器200提供至該相位/頻率檢測器201。該可變除頻器208提供一為21之除頻值。因此,該除頻器鏈之總除頻值N為168,而且在該該電壓控制振盪器204輸出之SLO1的頻率該為中心頻率fc=6720MHz。被提供至該ADC/DAC 209之該SADC之頻率為1680MHz。該ADC/DAC 209 具有一為2之過採樣率,所以該頻寬BW=840MHz。因此,fmin=6300MHz,而fmax=7140MHz。該時脈信號SCLK則具有一CLK=210MHz之頻率。 In one aspect in accordance with the present invention, a 40 MHz reference signal S REF frequency is provided by the reference signal generator 200 to the phase/frequency detector 201. The variable frequency divider 208 provides a divide value of 21. Therefore, the total frequency division value N of the frequency divider chain is 168, and the frequency of S LO1 outputted by the voltage control oscillator 204 is the center frequency f c = 6720 MHz. The frequency of the S ADC supplied to the ADC/DAC 209 is 1680 MHz. The ADC/DAC 209 has an oversampling rate of 2, so the bandwidth BW = 840 MHz. Therefore, f min = 6300 MHz and f max = 7140 MHz. The clock signal S CLK has a frequency of CLK = 210 MHz.

如第二行中所示,改變該可變除頻器208之除頻值至25時,該總除頻值將變為N=200,該中心頻率為fc=8000MHz,該頻寬BW=1000MHz,時脈頻率CLK=250MHz,fmin=7500MHz而fmax=8500MHz。因此,改變該除頻器鏈之總除頻值不僅改變該電壓控制振盪器204用於頻率混合之輸出的頻率,也改變了其它迴路之頻率值,如該SADC之頻率。同時也造成該頻寬BW和該時脈CLK之頻率是不同的結果。 As shown in the second row, when the frequency division value of the variable frequency divider 208 is changed to 25, the total frequency division value will become N=200, and the center frequency is f c = 8000 MHz, and the bandwidth BW= 1000 MHz, clock frequency CLK = 250 MHz, f min = 7500 MHz and f max = 8500 MHz. Thus, changing the total divide value of the divider chain not only changes the frequency at which the voltage controlled oscillator 204 is used for frequency mixing, but also changes the frequency values of other loops, such as the frequency of the S ADC . At the same time, the frequency BW and the frequency of the clock CLK are different.

第三行描述了當該可變除頻器208選擇了一除頻值為29時,其相關之組合值。在這種情況下,N=232,該中心頻率為fc=9280MHz,該頻寬BW=1160MHz,該時脈頻率CLK=290MHz,fmin=8700MHz而fmax=9860MHz。 The third row describes the associated combined value when the variable frequency divider 208 selects a divide value of 29. In this case, N = 232, the center frequency is f c = 9280 MHz, the bandwidth BW = 1160 MHz, the clock frequency CLK = 290 MHz, f min = 8700 MHz and f max = 9860 MHz.

根據本發明之一個觀點,其將參照第四行而被描述,從該除頻器鏈之不同位置中,取用被使用於混合之該電壓控制振盪器204的輸出,用以處理一不同之中心頻率fc。具體地說,在該除頻器鏈之第一固定除頻器電路205後面之該信號SL02,被用於提供該中心頻率fc=4000MHz。因為該可變除頻器208被選定之除頻值為25(因此,N=200),該頻寬BW和該時脈信號CLK與描述於第二行中之情況是相同的。僅有該中心頻率fc,該最小頻率fmin和最大頻率fmax不同。 According to one aspect of the present invention, it will be described with reference to the fourth row, from which the output of the voltage controlled oscillator 204 used for mixing is taken to handle a different one. Center frequency f c . Specifically, the signal S L02 following the first fixed frequency divider circuit 205 of the frequency divider chain is used to provide the center frequency f c = 4000 MHz. Since the variable frequency divider 208 is selected to have a divide value of 25 (hence, N = 200), the bandwidth BW and the clock signal CLK are the same as described in the second row. Only the center frequency f c, the minimum frequency f min and a maximum frequency f max different.

根據在本發明之一個觀點,在圖3所示之表是一用於超寬頻帶(UWB)之收發機及/或接收機的頻率-頻帶計畫。UWB是無線電通訊之一種型式之總稱,其發射之射頻能量分佈超過500MHz頻譜,而且其頻率 範圍介於3.1GHz至10.6GHz,並由FCC在2002年2月所制定公開之UWB定義。例如,在UWB可以採用頻譜的兩個部分包括3.1-5.15GHz和5.8-10.6GHz。 According to one aspect of the invention, the table shown in Figure 3 is a frequency-band scheme for a super wideband (UWB) transceiver and/or receiver. UWB is a general term for a type of radio communication. The transmitted RF energy distribution exceeds the 500MHz spectrum, and its frequency. The range is from 3.1 GHz to 10.6 GHz and is defined by the FCC's published UWB in February 2002. For example, the two parts of the spectrum that can be used in UWB include 3.1-5.15 GHz and 5.8-10.6 GHz.

具體地說,在圖2所示之該本地振盪器電路可用於產生如圖3之表中所示之具有中心頻率之本地振盪器信號。該些本地振盪器信號隨後被用於該接收鏈105中,將接收之射頻信號做降頻轉換,及/或在該傳送鏈116中,將一信號做升頻轉換並傳送。因此,該本地振盪器電路114及/或119可以產生及/或接收一個或多個如圖3所示之表描述之四個頻帶之訊號。 Specifically, the local oscillator circuit shown in Figure 2 can be used to generate a local oscillator signal having a center frequency as shown in the table of Figure 3. The local oscillator signals are then used in the receive chain 105 to downconvert the received RF signals, and/or in the transmit chain 116, a signal is upconverted and transmitted. Thus, the local oscillator circuit 114 and/or 119 can generate and/or receive signals of one or more of the four frequency bands described in the table of FIG.

在本發明的一些觀點,不同之參考頻率可被提供至鎖相迴路。例如,圖4之描述,一晶體振盪器(XTAL)401產生一穩定之參考頻率,其由一耦合至該控制介面218之可編程除頻器電路402除頻。該除頻器電路402基於從該控制介面218接收之指令而選擇不同之除頻值。因此,一可選擇之參考頻率和可選擇之除頻器值N的組合,可被採用於選取該中心頻率fc,該頻寬BW,該時脈頻率CLK,及/或其它由該鎖相迴路輸出之信號頻率。在本發明之一個觀點,該參考信號SREF頻率和該總除頻值N的數個組合可被產生,而用於提供了本質相同的ADC之頻率(例如,頻帶寬BW)至不同的中心頻率fcIn some aspects of the invention, different reference frequencies can be provided to the phase locked loop. For example, as depicted in FIG. 4, a crystal oscillator (XTAL) 401 produces a stable reference frequency that is divided by a programmable frequency divider circuit 402 coupled to the control interface 218. The frequency divider circuit 402 selects different frequency division values based on instructions received from the control interface 218. Thus, a combination of an optional reference frequency and a selectable divider value N can be employed to select the center frequency f c , the bandwidth BW, the clock frequency CLK, and/or other phase locks. The signal frequency of the loop output. In one aspect of the invention, several combinations of the reference signal S REF frequency and the total divide value N can be generated to provide a substantially identical ADC frequency (eg, frequency bandwidth BW) to a different center. Frequency f c .

圖5是一根據本發明之一個觀點的方法流程圖。為了由一鎖相迴路同時產生多個參考頻率,一參考信號,如一穩定且固定之參考時脈信號,被插入至該鎖相迴路501。例如,該參考信號可以由一晶體振盪器產生,並被耦合至該鎖相迴路中之一相位/頻率檢測器。 Figure 5 is a flow diagram of a method in accordance with one aspect of the present invention. In order to simultaneously generate a plurality of reference frequencies from a phase locked loop, a reference signal, such as a stable and fixed reference clock signal, is inserted into the phase locked loop 501. For example, the reference signal can be generated by a crystal oscillator and coupled to one of the phase/frequency detectors in the phase locked loop.

該鎖相迴路包含一電壓控制振盪器,其基於一控制電壓而產 生一振盪信號502,和一相位/頻率檢測器,其用於比較該振盪器信號與該輸入之參考信號的相位,並基於所檢測之相位差而產生一誤差信號。該鎖相迴路包含一迴路濾波器,其用於濾除該誤差信號和產生該電壓控制振盪器使用之控制電壓。因此,該電壓控制振盪器信號之頻率可以藉由改變該參考信號之頻率而改變,及/或在將該電壓控制振盪器輸出端耦合至該相位/頻率檢測器之該回授路徑中之一可變除頻器可被用來改變該電壓控制振盪器信號之頻率。 The phase locked loop includes a voltage controlled oscillator that is based on a control voltage An oscillating signal 502 is generated, and a phase/frequency detector for comparing the phase of the oscillator signal with the input reference signal and generating an error signal based on the detected phase difference. The phase locked loop includes a loop filter for filtering the error signal and generating a control voltage for use by the voltage controlled oscillator. Thus, the frequency of the voltage controlled oscillator signal can be varied by changing the frequency of the reference signal and/or one of the feedback paths coupling the output of the voltage controlled oscillator to the phase/frequency detector. A variable frequency divider can be used to vary the frequency of the voltage controlled oscillator signal.

在本發明之一個觀點,該回授路徑包括一序列連接之除頻器鏈。一第一本地振盪器信號由該回授路徑輸出503。該第一本地振盪器信號可以包括該電壓控制振盪器之輸出端,或者它可以包括由該序列連接之除頻器鏈中之一該除頻器電路的輸出端。 In one aspect of the invention, the feedback path includes a sequence of connected divider chains. A first local oscillator signal is output 503 from the feedback path. The first local oscillator signal may comprise an output of the voltage controlled oscillator or it may comprise an output of the frequency divider circuit of one of the frequency divider chains connected by the sequence.

在該回授路徑中,該第一本地振盪信號至少被一在序列連接之除頻器鏈的除頻器電路除頻504。一第二本地振盪器信號,具有不同於該第一本地振盪器信號之頻率,由該回授路徑中之序列連接的除頻器鏈輸出505。 In the feedback path, the first local oscillator signal is divided by frequency 504 by at least one of the frequency divider circuits of the sequentially connected divider chain. A second local oscillator signal having a frequency different from the first local oscillator signal, the divider chain output 505 connected by the sequence in the feedback path.

在本發明之一個觀點,該序列連接之除頻器鏈包括至少一第一除頻器電路和一第二除頻器電路。該除頻器鏈包含一第一本地振盪器輸出端,其在該第一除頻器電路之前被耦合,用於輸出一具有第一頻率之第一本地振盪器信號。該除頻器鏈還包含一第二本地振盪器輸出端,其在該第二除頻器電路之前被耦合,用於輸出一具有第二頻率且不同於該第一頻率之第二本地振盪器信號。通常,該第二頻率小於該第一頻率。該第一本地振盪器信號可被使用於一混合器中,用於升頻轉換及/或降頻轉換在收發 機中之信號,同時該第二本地振盪器信號可被使用於一不同於發送器功能之部分,如一用於一ADC之時脈信號。 In one aspect of the invention, the sequence-connected frequency divider chain includes at least a first frequency divider circuit and a second frequency divider circuit. The divider chain includes a first local oscillator output coupled prior to the first frequency divider circuit for outputting a first local oscillator signal having a first frequency. The divider chain further includes a second local oscillator output coupled prior to the second frequency divider circuit for outputting a second local oscillator having a second frequency and different from the first frequency signal. Typically, the second frequency is less than the first frequency. The first local oscillator signal can be used in a mixer for up-conversion and/or down-conversion in transceiving The signal in the machine, while the second local oscillator signal can be used in a different part of the transmitter function, such as a clock signal for an ADC.

本發明中所描述之該鎖相迴路電路和方法,可以在一整數型(integer-N)模式或分數型(fractional-N)模式中操作。藉由一整數型鎖相迴路所產生之該本地振盪訊號可能表現出相對較大量之相位雜訊。當該鎖相迴路操作時,該信號之頻率將改變並被控制在一由該迴路濾波器頻寬所決定之頻帶。在分數型鎖相迴路,該比較參考時脈信號之頻率可以更高。因此,該迴路濾波器可以有一較高之頻寬,從而抑制相位雜訊。分數型鎖相迴路拓撲,因此可以被用來產生相較於使用整數型鎖相迴路拓撲產生之本地振盪信號,其具有更少之相位雜訊的本地振盪信號。 The phase-locked loop circuit and method described in the present invention can operate in an integer-N mode or a fractional-N mode. The local oscillation signal generated by an integer phase-locked loop may exhibit a relatively large amount of phase noise. When the phase locked loop operates, the frequency of the signal will change and be controlled in a frequency band determined by the bandwidth of the loop filter. In a fractional phase-locked loop, the frequency of the comparison reference clock signal can be higher. Therefore, the loop filter can have a higher bandwidth to suppress phase noise. The fractional phase-locked loop topology can therefore be used to generate a local oscillator signal with less phase noise than a local oscillator signal generated using an integer phase-locked loop topology.

描述於此之方法和系統,僅僅說明本發明的特定觀點。應當理解,雖然沒有於此明確地描述或示出,熟習該項技術者將能夠設計各種配置,其具體化本發明的原理並包括在其範圍之內。此外,本文引用之所有示例和條件語言僅意圖用於教導目的,以幫助讀者理解本發明的原理。本發明和其相關的參考文獻係用於解釋,並不受限於這些具體引用的示例和條件。此外,於此所有陳述本發明之各原理和觀點,以及其具體實例,意在包含其結構和功能的之等同物。另外,本案意圖在該些等同物,其包含當前已知之等同物以及將來開發之等同物,亦即,具有執行相同功能的任何開發元件,而與其結構無關。 The methods and systems described herein are merely illustrative of specific aspects of the invention. It will be appreciated that those skilled in the art will be able to devise various configurations that are embodied within the scope of the invention. Moreover, all of the examples and conditional language cited herein are for the purpose of teaching purposes only, and are intended to aid the understanding of the principles of the invention. The present invention and its related references are for explanation and are not limited to the examples and conditions of these specific references. In addition, all of the principles and aspects of the present invention, as well as the specific examples thereof, are intended to include equivalents of the structure and function. In addition, the present invention is intended to be in terms of equivalents, and equivalents of the

200‧‧‧參考訊號產生器/晶體振盪器電路 200‧‧‧Reference signal generator/crystal oscillator circuit

201‧‧‧相位/頻率檢測器 201‧‧‧ phase/frequency detector

202‧‧‧電荷泵 202‧‧‧Charge pump

203‧‧‧迴路濾波器 203‧‧‧ Loop Filter

204‧‧‧電壓控制振盪器 204‧‧‧Voltage Controlled Oscillator

205、206、207‧‧‧除2除頻器電路 205, 206, 207‧‧‧ except 2 frequency divider circuit

208‧‧‧可變除頻器電路 208‧‧‧Variable frequency divider circuit

209‧‧‧數位/類比轉換器、類比/數位轉換器 209‧‧‧Digital/analog converters, analog/digital converters

210‧‧‧除頻器電路 210‧‧‧Densor circuit

218‧‧‧控制介面 218‧‧‧Control interface

Claims (15)

一鎖相迴路電路包括:一相位/頻率檢測器;一電壓控制振盪器(VCO);一序列連接之除頻器鏈,其位於將該電壓控制振盪器之輸出端與該相位/頻率檢測器耦合之回授路徑中;以及多個本地振盪器輸出端,其分佈在該除頻器鏈內的不同位置,以用於至少提供具有一第一頻率之一第一本地震盪信號和具有一第二頻率之一第二本地震盪訊號,該第二頻率不同於該第一頻率。 A phase-locked loop circuit includes: a phase/frequency detector; a voltage controlled oscillator (VCO); a sequence of connected frequency divider chains located at an output of the voltage controlled oscillator and the phase/frequency detector a coupled feedback path; and a plurality of local oscillator outputs distributed at different locations within the divider chain for providing at least one of the first seismic signals having a first frequency and having a first One of the two frequencies, the second seismic semaphore, the second frequency being different from the first frequency. 如申請專利範圍第1項所述之電路,其中該除頻器鏈至少包括一可變除頻器電路,用於致能該第一頻率和該第二頻率中至少一者之可選擇值。 The circuit of claim 1, wherein the frequency divider chain includes at least one variable frequency divider circuit for enabling a selectable value of at least one of the first frequency and the second frequency. 如申請專利範圍第2項所述之電路,其中至少一該可變除頻器電路和該等本地震盪器輸出端被配置用於產生數個具有該第一頻率的多重不同值,其每一者與具有該第二頻率之大致相等值配對。 The circuit of claim 2, wherein at least one of the variable frequency divider circuit and the output of the present oscillator are configured to generate a plurality of different values having the first frequency, each of Paired with approximately equal values having the second frequency. 如申請專利範圍第1項所述之電路,進一步包括一參考信號產生器,其被配置用以提供可選擇之參考頻率至該相位/頻率檢測器。 The circuit of claim 1, further comprising a reference signal generator configured to provide a selectable reference frequency to the phase/frequency detector. 如申請專利範圍第1項所述之電路,其被配置成以一整數型(integer-N)模式或一分數型(fractional-N)模式中的至少一者操作。 The circuit of claim 1, wherein the circuit is configured to operate in at least one of an integer-N mode or a fractional-N mode. 一鎖相迴路電路包括:一相位/頻率檢測器;一電壓控制振盪器(VCO);一序列連接之除頻器鏈,其位於將該電壓控制振盪器之輸出端與該相 位/頻率檢測器耦合之回授路徑中,該除頻器鏈包括一第一除頻器電路,一第一本地振盪器輸出端,其被耦合在該第一除頻器電路之前以用於提供具有一第一頻率之一第一本地振盪信號,一第二除頻器電路,以及一第二本地振盪器輸出端,其被耦合在該第二除頻器電路之前以用於提供具有一第二頻率之一第二本地振盪信號,該第二頻率不同於該第一頻率。 A phase-locked loop circuit includes: a phase/frequency detector; a voltage controlled oscillator (VCO); a sequence of connected frequency divider chains located at an output of the voltage controlled oscillator and the phase In a feedback path coupled to the bit/frequency detector, the divider chain includes a first frequency divider circuit, a first local oscillator output coupled to the first frequency divider circuit for use in Providing a first local oscillator signal having a first frequency, a second frequency divider circuit, and a second local oscillator output coupled to the second frequency divider circuit for providing a A second local oscillation signal of the second frequency, the second frequency being different from the first frequency. 如申請專利範圍第6項所述之電路,其中該除頻器鏈包括至少一可變除頻器電路,用於致能該第一頻率和該第二頻率中至少一者之可選擇值。 The circuit of claim 6 wherein the frequency divider chain comprises at least one variable frequency divider circuit for enabling a selectable value of at least one of the first frequency and the second frequency. 如申請專利範圍第7項所述之電路,其中該可變除頻器電路,該第一本地震盪器輸出端,和該第二本地震盪器輸出端中至少一者被配置用於產生數個具有該第一頻率的不同值,以及具有該第二頻率的大致相等值。 The circuit of claim 7, wherein the variable frequency divider circuit, the first current oscillator output, and the second current oscillator output are configured to generate a plurality of There are different values for the first frequency and approximately equal values for the second frequency. 如申請專利範圍第6項所述之電路,進一步包括一參考信號產生器,其被配置用以提供可選擇之參考頻率至該相位/頻率檢測器。 The circuit of claim 6 further comprising a reference signal generator configured to provide a selectable reference frequency to the phase/frequency detector. 如申請專利範圍第6項所述之電路,其被配置成以在一整數型模式或一分數型模式中的至少一者操作。 The circuit of claim 6, wherein the circuit is configured to operate in at least one of an integer mode or a fractional mode. 一種用於由一鎖相迴路(PLL)中同時產生多個參考頻率之方法,包括:將一參考信號插入至該鎖相迴路;在該鎖相迴路產生一電壓控制振盪信號;在該鎖相迴路之一回授路徑中產生一第一本地振盪器信號,該本地振盪器信號具有一第一頻率;對在該鎖相迴路之一回授路徑中的至少該第一本地振盪器信號進行頻率除頻,以產生一第二本地振盪器信號,其具有不同於該第一頻率之一第 二頻率;以及同時輸出該第一本地振盪器信號和該第二本地振盪器信號。 A method for simultaneously generating a plurality of reference frequencies from a phase locked loop (PLL), comprising: inserting a reference signal into the phase locked loop; generating a voltage controlled oscillating signal in the phase locked loop; Generating a first local oscillator signal in a feedback path of the loop, the local oscillator signal having a first frequency; and performing frequency on at least the first local oscillator signal in a feedback path of the phase locked loop Frequency division to generate a second local oscillator signal having a different one of the first frequencies Two frequencies; and simultaneously outputting the first local oscillator signal and the second local oscillator signal. 如申請專利範圍第11項所述之方法,其中頻率除頻是由至少一固定除頻器電路中和至少一可變除頻器電路所執行。 The method of claim 11, wherein the frequency division is performed by at least one fixed frequency divider circuit and at least one variable frequency divider circuit. 如申請專利範圍第11項所述之方法,其中該鎖相迴路被配置成以一整數型模式和一分數型模式中的至少一者操作。 The method of claim 11, wherein the phase locked loop is configured to operate in at least one of an integer mode and a fractional mode. 如申請專利範圍第11項所述之方法,進一步包括採用可選擇之參考頻率和可選擇之除頻值中的至少一者,用以選取該第一頻率和該第二頻率中的至少一者。 The method of claim 11, further comprising selecting at least one of the selectable reference frequency and the selectable divide value for selecting at least one of the first frequency and the second frequency . 如申請專利範圍第11項所述之方法,進一步包括產生數個具有該第一頻率之不同值,其與具有該第二頻率之大致相等值配對。 The method of claim 11, further comprising generating a plurality of different values having the first frequency paired with substantially equal values having the second frequency.
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