TW201312722A - Semiconductor device, electrostatic discharge protection device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device, an electrostatic discharge protection device and manufacturing method thereof are provided. The electrostatic discharge protection device includes a gate, a gate dielectric layer, an N-type source region, an N-type drain region, an N-type doped region and a P-type doped region. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The N-type source region and the N-type drain region are disposed in the substrate at two sides of the gate, respectively. The N-type doped region is disposed in the N-type drain region and connects to the top of the N-type drain region. The P-type doped region is disposed under the N-type drain region and connects to the bottom of the N-type drain region.

Description

Semiconductor element, electrostatic discharge protection element and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to an electrostatic discharge (ESD) protection device and a method of fabricating the same.

Electrostatic discharge is a phenomenon of electrostatic movement from a non-conductive surface, which causes damage to semiconductor components and other circuits in an integrated circuit. For example, when a common charged body such as a machine that packages an integrated circuit or an instrument that tests an integrated circuit contacts a wafer, the wafer is discharged, and the instantaneous power of the electrostatic discharge may cause damage to the integrated circuit in the wafer. Or invalid. In order to prevent the integrated circuit from being damaged by the electrostatic discharge phenomenon, the design of the electrostatic discharge protection element is usually incorporated in the integrated circuit.

A common electrostatic discharge protection component is to dispose a silicide block on the drain of the N-type transistor to prevent electrostatic current from passing through the surface of the substrate to damage the component to achieve electrostatic discharge protection. However, in forming the above-described telluride barrier layer, it is often necessary to additionally use a mask, thereby increasing process complexity and increasing production cost.

The present invention provides an electrostatic discharge protection element that prevents components from being damaged by electrostatic current.

The present invention further provides a method of fabricating an electrostatic discharge protection element that has fewer process steps and lower production costs.

The present invention further provides a semiconductor component that can prevent the component from being damaged by electrostatic current.

The present invention provides an electrostatic discharge protection device including a gate, a gate dielectric layer, an N-type source region, an N-type drain region, an N-type doped region, and a P-type doped region. The gate dielectric layer is disposed on the substrate. The gate is disposed on the gate dielectric layer. The N-type source region and the N-type drain region are respectively disposed in the substrate on the two sides of the gate. The N-type doped region is disposed in the N-type drain region and is connected to the top surface of the N-type drain region. The P-type doped region is disposed under the N-type drain region and is connected to the bottom surface of the N-type drain region.

According to the electrostatic discharge protection device of the embodiment of the invention, the P-type doped region is connected to a portion of the bottom surface of the N-type drain region, for example.

According to the electrostatic discharge protection device of the embodiment of the invention, the P-type doping region is connected to the entire bottom surface of the N-type drain region, for example.

According to the electrostatic discharge protection device of the embodiment of the invention, the N-type doping region is connected to a portion of the top surface of the N-type drain region, for example.

According to the electrostatic discharge protection device of the embodiment of the invention, the N-type doping region is connected to the entire top surface of the N-type drain region, for example.

According to the electrostatic discharge protection device of the embodiment of the invention, the doping concentration of the N-type drain region is greater than the doping concentration of the N-type doping region, for example.

According to the electrostatic discharge protection device of the embodiment of the invention, the substrate is, for example, a P-type substrate, and the doping concentration of the P-type doping region is greater than the doping concentration of the substrate.

The present invention further provides a method of fabricating an electrostatic discharge protection device by first providing a substrate having a memory region and a peripheral circuit region. Then, a first gate structure is formed in the memory region, and a second gate structure is formed in the peripheral circuit region. Then, performing a first erbium doping process, forming a P-type pocket doped region in the substrate under the first gate structure and forming an N-type light doping in the substrate on both sides of the first gate structure a lightly doped drain (LDD), and an N-type doped region and a P-type doped region are formed in a substrate on a side of the second gate structure, wherein the P-type pocket doped region is adjacent to the N-type doped region The P-type doped region is located below the N-type doped region, and the P-type doped region and the N-type doped region are separated from each other. Then, performing a second doping process to form a first N-type source region and a first N-type drain region respectively in the substrate on both sides of the first gate structure, and in the substrate on both sides of the second gate structure Forming a second N-type source region and a second N-type drain region, respectively, wherein the N-type doping region is located in the second N-type drain region and is connected to the top surface of the second N-type drain region, P-type doping The impurity region is located below the second N-type drain region and is connected to the bottom surface of the second N-type drain region.

According to the method of fabricating an electrostatic discharge protection device according to an embodiment of the invention, the P-type doped region is connected to a bottom surface of a portion of the second N-type drain region, for example.

According to the method of fabricating an electrostatic discharge protection device according to an embodiment of the invention, the P-type doping region is connected to the entire bottom surface of the second N-type drain region, for example.

According to the method of fabricating an electrostatic discharge protection device according to an embodiment of the invention, the N-type doped region is connected to a top surface of a portion of the second N-type drain region, for example.

According to the method of fabricating an electrostatic discharge protection device according to an embodiment of the invention, the N-type doping region is connected to the entire top surface of the second N-type drain region, for example.

According to the method of fabricating an electrostatic discharge protection device according to an embodiment of the invention, the doping concentration of the second N-type drain region is greater than the doping concentration of the N-type doped region, for example.

According to the manufacturing method of the electrostatic discharge protection device according to the embodiment of the invention, the substrate is, for example, a P-type substrate, and the doping concentration of the P-type doping region is greater than the doping concentration of the substrate.

The present invention further provides a semiconductor device including a substrate, a memory, and an electrostatic discharge protection element. The substrate has a memory region and a peripheral circuit region. The memory is placed in the memory area. The electrostatic discharge protection element is disposed in the peripheral circuit area. The electrostatic discharge protection component includes a gate, a gate dielectric layer, an N-type source region, an N-type drain region, an N-type doped region, and a P-type doped region. The gate dielectric layer is disposed on the substrate. The gate is disposed on the gate dielectric layer. The N-type source region and the N-type drain region are respectively disposed in the substrate on the two sides of the gate. The N-type doped region is disposed in the N-type drain region and is connected to the top surface of the N-type drain region. The P-type doped region is disposed under the N-type drain region and is connected to the bottom surface of the N-type drain region.

According to the semiconductor device of the embodiment of the invention, the P-type doping region is connected to a portion of the bottom surface of the N-type drain region, for example.

According to the semiconductor device of the embodiment of the invention, the P-type doping region is connected to the entire bottom surface of the N-type drain region, for example.

According to the semiconductor device of the embodiment of the invention, the N-type doping region is connected to a portion of the top surface of the N-type drain region, for example.

According to the semiconductor device of the embodiment of the invention, the N-type doping region is connected to the entire top surface of the N-type drain region, for example.

According to the semiconductor device of the embodiment of the invention, the doping concentration of the N-type drain region is greater than the doping concentration of the N-type doping region, for example.

According to the semiconductor device of the embodiment of the invention, the substrate is, for example, a P-type substrate, and the doping concentration of the P-type doping region is greater than the doping concentration of the substrate.

Based on the above, in the electrostatic discharge protection element of the present invention, since a P-type doped region is disposed under the N-type drain region, when an electrostatic current is generated and flows to the electrostatic discharge protection element, it flows to the N-type drain region. The electrostatic current flows down to the P-doped region, thereby changing the path of the electrostatic current, thereby preventing components on the surface of the substrate from being damaged by electrostatic current. In addition, the present invention integrates the formation steps of the P-type doped regions described above into the process of the memory region, thereby reducing process complexity and reducing production costs.

The above described features and advantages of the present invention will be more apparent from the following description.

FIG. 1 is a cross-sectional view of an electrostatic discharge protection device according to an embodiment of the invention. Referring to FIG. 1 , the ESD protection device 10 includes a gate 102 , a gate dielectric layer 104 , an N-type source region 106 , an N-type drain region 108 , an N-type doping region 110 , and a P-type doping region 112 . The gate 102 is disposed on the substrate 100. The gate 102 is, for example, a polysilicon gate, a gate or a metal gate. The gate dielectric layer 104 is disposed between the gate 102 and the substrate 100. The gate dielectric layer 104 is, for example, an oxide layer, a nitride layer, an oxynitride layer, a nitrided oxide layer, a high dielectric constant layer, or a combination thereof. The N-type source region 106 and the N-type drain region 108 are disposed in the substrate 100 on both sides of the gate 102, respectively. The dopants in the N-type source region 106 and the N-type drain region 108 are, for example, phosphorus or arsenic, and have a doping concentration of, for example, 3 × 10 ¹⁵ atoms/cm 2 to 6 × 10 ¹⁵ atoms/cm 2 .

Further, the N-type doping region 110 is disposed in the N-type drain region 108 and is connected to a portion of the top surface of the N-type drain region 108. In the present embodiment, the N-type doping region 110 is disposed away from the gate 102. The dopant in the N-type doping region 110 is, for example, phosphorus or arsenic, and has a doping concentration of, for example, 1 × 10 ¹⁵ atoms/cm 2 to 2 × 10 ¹⁵ atoms/cm 2 . The P-type doping region 112 is disposed under the N-type drain region 108 and is connected to a portion of the bottom surface of the N-type drain region 108. In the present embodiment, the P-type doping region 112 is disposed away from the gate 102, and the position of the P-type doping region 112 corresponds to the position of the N-type doping region 110. Of course, in other embodiments, the position of the P-type doping region 112 may not correspond to the position of the N-type doping region 110. The dopant in the P-type doping region 112 is, for example, boron or indium, and has a doping concentration of, for example, 5 × 10 ¹³ atoms/cm 2 to 7 × 10 ¹³ atoms/cm 2 .

It should be noted that when the substrate 100 is a P-type substrate doped with a P-type dopant, the doping concentration of the P-type doping region 112 must be greater than the doping concentration of the P-type substrate. The doping concentration of the P-type substrate is, for example, from 7 × 10 ¹¹ atoms/cm 2 to 9 × 10 ¹¹ atoms/cm 2 .

When an electrostatic current is generated and flows to the electrostatic discharge protection element 10, the electrostatic current flows to the N-type drain region 108 via a drain contact window (not shown). Thereafter, since the P-type doping region 112 is disposed under the N-type drain region 108, the electrostatic current flowing to the N-type drain region 108 flows down to the P-type doping region 112, thereby changing the path of the electrostatic current. Further, the components on the surface of the substrate 100 are prevented from being damaged by the influence of the electrostatic current.

2 is a cross-sectional view of an electrostatic discharge protection device in accordance with another embodiment of the present invention. Referring to FIG. 2, the electrostatic discharge protection component 20 differs from the electrostatic discharge protection component 10 in that, in the electrostatic discharge protection component 20, the N-type doping region 110 and the P-type doping region 112 are disposed adjacent to the gate 102, and P The position of the doped region 112 corresponds to the position of the N-type doped region 110. Of course, in other embodiments, the position of the P-type doping region 112 may not correspond to the position of the N-type doping region 110.

3 is a cross-sectional view of an electrostatic discharge protection device in accordance with still another embodiment of the present invention. Referring to FIG. 3, the electrostatic discharge protection component 30 differs from the electrostatic discharge protection component 10 in that, in the electrostatic discharge protection component 30, the N-type doping region 110 is disposed adjacent to the gate 102, and the P-type doping region 112 is configured as Keep away from the gate 102. Of course, in other embodiments, the N-type doping region 110 may be disposed away from the gate 102, and the P-type doping region 112 may be disposed adjacent to the gate 102.

In particular, in the case where the N-type doping region 110 is connected to a portion of the top surface of the N-type drain region 108 and the P-type doping region 112 is connected to a portion of the bottom surface of the N-type drain region 108, the N-type doping is performed. The positions of the impurity region 110 and the P-type doping region 112 are not limited to those shown in FIGS. 1 to 3, and the N-type doping region 110 and the P-type doping region 112 may be disposed at desired positions according to actual needs.

4 is a cross-sectional view of an electrostatic discharge protection device in accordance with still another embodiment of the present invention. Referring to FIG. 4, the electrostatic discharge protection component 40 differs from the electrostatic discharge protection component 10 in that, in the electrostatic discharge protection component 40, the N-type doping region 110 is connected to the entire top surface of the N-type drain region 108, and the P-type The doped region 112 is connected to the entire bottom surface of the N-type drain region 108.

Hereinafter, a method of manufacturing the electrostatic discharge protection element will be described by taking the electrostatic discharge protection element 10 of FIG. 1 as an example. Those skilled in the art can also apply the above manufacturing method to the manufacture of the electrostatic discharge protection element in other embodiments of the present invention.

5A-5C are schematic cross-sectional views showing a manufacturing process of an electrostatic discharge protection device according to an embodiment of the invention. First, referring to FIG. 5A, a substrate 100 having a memory region 100a and a peripheral circuit region 100b is provided. The memory area 100a is an area for forming a memory, and the peripheral circuit area 100b is an area for forming the electrostatic discharge protection element of the present invention. Then, a first gate structure 500 is formed in the memory region 100a, and a second gate structure 502 is formed in the peripheral circuit region 100b.

In the present embodiment, the first gate structure 500 includes a tunneling dielectric layer 500a, a floating gate 500b, an inter-gate dielectric layer 500c, and a control gate 500d. However, the present invention is not limited thereto, and the first gate structure 500 may be other well-known memory gate structures. In addition, the second gate structure 502 includes a gate dielectric layer 104 and a gate 102. The method of forming the first gate structure 500 and the second gate structure 502 is well known to those skilled in the art and will not be described herein.

Then, referring to FIG. 5B, a first erbium-doping process is performed to form a P-type pocket-type doped region 504 in the substrate 100 under the first gate structure 500 and a substrate 100 formed on both sides of the first gate structure 500. An N-type doped region 506, and an N-type doped region 110 and a P-type doped region 112 are formed in the substrate 100 on the side of the second gate structure 502. The P-type pocket doped region 504 is adjacent to the N-type lightly doped region 506. The first erbium doping process is, for example, an ion implantation process. By controlling the depth of ion implantation, the P-type doping region 112 is located below the N-type doping region 110, and the P-type doping region 112 and the N-type doping region 110 are separated from each other. The dopants in the P-type pocket doping region 504 and the P-type doping region 112 are, for example, boron or indium, and have a doping concentration of, for example, 5×10 ¹³ atoms/cm 2 to 7×10 ¹³ atoms/cm 2 . The dopants in the N-type lightly doped region 506 and the N-type doped region 110 are, for example, phosphorus or arsenic, and have a doping concentration of, for example, 1 × 10 ¹⁵ atoms/cm 2 to 2 × 10 ¹⁵ atoms/cm 2 .

Thereafter, referring to FIG. 5C, a second doping process is performed to form an N-type source/drain region 508 in the substrate 100 on both sides of the first gate structure 500, and a substrate on both sides of the second gate structure 502. An N-type source region 106 and an N-type drain region 108 are formed in 100 to form an electrostatic discharge protection element 10. The second erbium doping process is, for example, an ion implantation process. By controlling the depth of ion implantation, the N-type doping region 110 is located in the N-type drain region 108 and is connected to a portion of the top surface of the N-type drain region 108, and the P-type doping region 112 is located in the N-type drain region. Below 108 is connected to a portion of the bottom surface of the N-type drain region 108. The dopants in the N-type source/drain region 508, the N-type source region 106 and the N-type drain region 108 are, for example, phosphorus or arsenic, and the doping concentration thereof is, for example, 3×10 ¹⁵ atoms/cm 2 to 6 × 10 ¹⁵ atoms / square centimeter.

In the manufacturing process of the above electrostatic discharge protection element 10, the N-type doped region 110 and the P-type doped region 112 in the peripheral circuit region 100b and the P-type pocket-type doped region 504 and the N-type light in the memory region 100a are light. The doped region 506 is formed in the same doping process, that is, no additional steps are required to form the N-type doped region 110 and the P-type doped region 112 of the present invention for changing the path of the electrostatic current, thereby reducing The process complexity of the electrostatic discharge protection component is reduced, and the production cost is reduced.

Figure 6 is a graph showing the relationship between voltage and current in an electrostatic discharge protection device. As can be seen from FIG. 6, the electrostatic discharge protection device of the embodiment of the present invention (the N-type doped region is formed in the N-type drain region, and the P-type doped region is formed under the N-type drain region) and the prior art The electrostatic discharge protection element of the embodiment of the present invention can be compared with the electrostatic discharge protection element (the N-type doped region is not formed in the N-type drain region, and the P-type doped region is not formed under the N-type drain region). It has a low turn-on resistance, so that the electrostatic discharge protection element of the embodiment of the present invention can withstand a higher current when the same voltage is applied. Therefore, the electrostatic discharge protection element of the embodiment of the invention can have a better electrostatic discharge protection effect.

Further, after the electrostatic discharge protection element is formed, a contact electrically connected to the N-type source region and the N-type drain region is formed. The electrostatic discharge protection element 10 will be described below as an example.

Figure 7 is a schematic cross-sectional view showing the formation of a contact window after formation of an electrostatic discharge protection element. Referring to FIG. 7, a dielectric layer 704 covering the electrostatic discharge protection device 10 is formed, and contact windows 700, 702 are formed in the dielectric layer 704, wherein the contact window 700 is electrically connected to the N-type source region 106, and the contact window 702 is electrically connected to the N-type drain region 108. There is a distance L1 between the contact window 700 and the second gate structure 502, and a distance L2 between the contact window 702 and the second gate structure 502, wherein the distance L2 is greater than or equal to the distance L1. The distance L1 is, for example, between 0.5 μm and 1 μm. The distance L2 is, for example, between 1 μm and 3 μm. The distance L2 is preferably 2 μm so that the electrostatic discharge protection element 10 can have a better second breakdown failure current.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 20, 30, 40. . . Electrostatic discharge protection component

100. . . Base

100a. . . Memory area

100b. . . Peripheral circuit area

102. . . Gate

104. . . Gate dielectric layer

106. . . N-type source region

108. . . N-type bungee zone

110. . . N-doped region

112. . . P-doped region

500. . . First gate structure

500a. . . Tunneling dielectric layer

500b. . . Floating gate

500c. . . Dielectric layer

500d. . . Control gate

502. . . Second gate structure

700, 702. . . Contact window

704. . . Dielectric layer

1 is a cross-sectional view of an electrostatic discharge protection device in accordance with an embodiment of the invention.

2 is a cross-sectional view of an ESD protection device according to another embodiment of the invention.

3 is a cross-sectional view of an electrostatic discharge protection device according to another embodiment of the present invention.

4 is a cross-sectional view of an electrostatic discharge protection device according to another embodiment of the present invention.

5A-5C are schematic cross-sectional views showing a manufacturing process of an electrostatic discharge protection device according to an embodiment of the invention.

Figure 6 is a graph showing the relationship between voltage and current in an ESD protection device.

Figure 7 is a schematic cross-sectional view showing the formation of a contact window after formation of an electrostatic discharge protection element.

10. . . Electrostatic discharge protection component

100. . . Base

102. . . Gate

104. . . Gate dielectric layer

106. . . N-type source region

108. . . N-type bungee zone

110. . . N-doped region

112. . . P-doped region

Claims (21)

An electrostatic discharge protection component comprising: a gate dielectric layer disposed on a substrate; a gate disposed on the gate dielectric layer; an N-type source region and an N-type drain region, respectively disposed An anode of the two sides of the gate; an N-type doped region disposed in the N-type drain region and connected to a top surface of the N-type drain region; and a P-type doped region disposed in the The N-type drain region is below and connected to the bottom surface of the N-type drain region. The electrostatic discharge protection device of claim 1, wherein the P-type doped region is connected to a portion of the bottom surface of the N-type drain region. The electrostatic discharge protection device of claim 1, wherein the P-type doped region is connected to the entire bottom surface of the N-type drain region. The electrostatic discharge protection device of claim 1, wherein the N-type doped region is connected to a portion of a top surface of the N-type drain region. The electrostatic discharge protection device of claim 1, wherein the N-type doped region is connected to an entire top surface of the N-type drain region. The electrostatic discharge protection device of claim 1, wherein the N-type drain region has a doping concentration greater than a doping concentration of the N-type doped region. The electrostatic discharge protection device of claim 1, wherein the substrate is a P-type substrate, and a doping concentration of the P-type doping region is greater than a doping concentration of the substrate. A method for manufacturing an electrostatic discharge protection device, comprising: providing a substrate having a memory region and a peripheral circuit region; forming a first gate structure in the memory region; and forming a first layer in the peripheral circuit region a second gate structure; a P-type pocket-type doped region is formed in the substrate under the first gate structure; and an N-type lightly doped region is formed in the substrate on both sides of the first gate structure, and Forming an N-type doped region and a P-type doped region in the substrate on one side of the second gate structure, wherein the P-type pocket-type doped region is adjacent to the N-type lightly doped region, the P-type a doped region is disposed under the N-type doped region; and a first N-type source region and a first N-type drain region are respectively formed in the substrate on both sides of the first gate structure, and Forming a second N-type source region and a second N-type drain region in the substrate on the two sides of the second gate structure, wherein the N-type doping region is located in the second N-type drain region and a top surface of the second N-type drain region is connected, and a P-type doped region is located below the second N-type drain region and is opposite to the second N-type drain region The bottom side is connected. The method of manufacturing an electrostatic discharge protection device according to claim 8, wherein the P-type doped region is connected to a portion of a bottom surface of the second N-type drain region. The method of manufacturing an electrostatic discharge protection device according to claim 8, wherein the P-type doped region is connected to the entire bottom surface of the second N-type drain region. The method of manufacturing an electrostatic discharge protection device according to claim 8, wherein the N-type doped region is connected to a portion of a top surface of the second N-type drain region. The method of manufacturing an electrostatic discharge protection device according to claim 8, wherein the N-type doping region is connected to an entire top surface of the second N-type drain region. The method of manufacturing an electrostatic discharge protection device according to claim 8, wherein a doping concentration of the second N-type drain region is greater than a doping concentration of the N-type doping region. The method of manufacturing an electrostatic discharge protection device according to claim 1, wherein the substrate is a P-type substrate, and a doping concentration of the P-type doping region is greater than a doping concentration of the substrate. A semiconductor device comprising: a substrate having a memory region and a peripheral circuit region; a memory disposed in the memory region; and an electrostatic discharge protection component disposed in the peripheral circuit region, the electrostatic discharge protection component The method includes: a gate dielectric layer disposed on the substrate; a gate disposed on the gate dielectric layer; an N-type source region and an N-type drain region respectively disposed on the two sides of the gate An N-type doped region disposed in the N-type drain region and connected to a top surface of the N-type drain region; and a P-type doped region disposed in the N-type drain region Below, and connected to the bottom surface of the N-type drain region. The semiconductor device of claim 15, wherein the P-type doped region is connected to a portion of the bottom surface of the N-type drain region. The semiconductor device of claim 15, wherein the P-type doped region is connected to the entire bottom surface of the N-type drain region. The semiconductor device of claim 15, wherein the N-type doped region is connected to a portion of a top surface of the N-type drain region. The semiconductor device of claim 15, wherein the N-type doped region is connected to an entire top surface of the N-type drain region. The semiconductor device of claim 15, wherein a doping concentration of the N-type drain region is greater than a doping concentration of the N-type doping region. The semiconductor device of claim 15, wherein the substrate is a P-type substrate, and a doping concentration of the P-type doping region is greater than a doping concentration of the substrate.