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TW201241981A - Package substrate and fabrication method thereof - Google Patents

Package substrate and fabrication method thereof Download PDF

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Publication number
TW201241981A
TW201241981A TW100112523A TW100112523A TW201241981A TW 201241981 A TW201241981 A TW 201241981A TW 100112523 A TW100112523 A TW 100112523A TW 100112523 A TW100112523 A TW 100112523A TW 201241981 A TW201241981 A TW 201241981A
Authority
TW
Taiwan
Prior art keywords
electrical contact
straight
contact pads
contact pad
width
Prior art date
Application number
TW100112523A
Other languages
Chinese (zh)
Other versions
TWI501366B (en
Inventor
Shih-Ping Hsu
Tsung-Yuan Chen
Ho-Shing Lee
Original Assignee
Unimicron Technology Corp
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Priority to TW100112523A priority Critical patent/TWI501366B/en
Publication of TW201241981A publication Critical patent/TW201241981A/en
Application granted granted Critical
Publication of TWI501366B publication Critical patent/TWI501366B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Disclosed is a package substrate comprised of a circuit board and upright pillar copper bumps, wherein the circuit board has opposing first and second surface, the first surface having a plurality of first and second electrical connecting pads formed thereon, wherein the upright pillar copper bump is disposed on each of the first electrical connecting pads and higher than the second electrical connecting pads, thereby preventing stacked packages from bumping against each other unexpectedly, as well as the bridging phenomenon during the reflow process. The invention further discloses a fabrication method for the package substrate as described above.

Description

201241981 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係有關一種封裝基板及其製法，尤指一種具 直柱型銅凸塊之封裝基板及其製法。 [0002] ❹ 【先前技術】 隨著電子產品的微型化發展趨勢，印刷電路板（pCB )表面可供設置半導體封裝結構的面積越來越小，因此 遂發展出一種半導體封裝結構之立體堆疊技術，其係將 複數個半導體封裝結構相互堆疊一起，而成為一層疊封 裝件（package on package，簡稱POP)，以符合小型 表面接合面積與高密度元件設置之要求。 [0003] 請參閱第1圖’係習知之層疊封裝件之剖視圖，如圖 所示’習知之層疊封裝件係將兩個具有晶片1Π，121的封 裝結構11，12相互堆疊’並直接以焊球丨3連接，俾使該兩 個封裝結構11，12之間有所間隔而不至於互相碰觸。 [0004] 〇 惟，為了確保兩個封裝結構11，12之間不會互相碰觸 ，習知技術一般須使用較大直徑之焊球13以加深晶片封 裝區域深度D ’這使得焊球13的體積較大而佔用較大封裝 基板表面積’進而不利於封裝基板面積的縮小；另外， 在現代電子產品逐漸微型化之趨勢下，封裝基板上的焊 塾112，122之間的間距也愈來愈小，因此於迴鮮連接時， 體積較大的焊球13也容易溢流至四周而造成橋接現象， 進而導致不良品的產生。 [0005] 因此’如何避免習知技術中之層疊封裝件的焊球佔 100112523 用過大的封裝基板面積，且容易在迴銲時造成橋接，而 表單編就A0101 第3頁/共15頁 1002020874-0 201241981 使得整體良率下降等問題，實已成為目前亟欲解決的課 題。 【發明内容】 [0006] [0007] [0008] [0009] 鑑於上述習知技術之種種缺失，本發明之主要目的 係提供一種良率較高之封裝基板及其製法。 為達上述及其他目的，本發明揭露一種封裝基板， 係包括：線路板，係具有交互相疊之至少一介電層與線 路層，且具有相對之第一表面及第二表面；複數第一電 性接觸墊，係設於該第一表面上；複數第二電性接觸墊 ，係設於該第一表面上，其中，該等第一電性接觸墊係 圍繞該等第二電性接觸墊，且該第一電性接觸墊之寬度 係大於該第二電性接觸墊之寬度；以及直柱型銅凸塊， 係設於各該第一電性接觸墊上，且該直柱型銅凸塊與該 第一電性接觸墊之間係具有一導電層，其中，該直柱型 銅凸塊之寬度係小於該第一電性接觸墊之寬度，且該直 柱型銅凸塊係高於該第二電性接觸墊，以供該直柱型銅 凸塊藉由焊料連接至其他基板，同時，該第一表面、第 一電性接觸墊、第二電性接觸墊、與直柱型銅凸塊表面 係外露於環境中。 前述之封裝基板中，該第二表面復可具有複數第三 電性接觸墊。 依上述之封裝基板，該導電層22之材料係可選自由 電鏟錄/金、化學鍍錄/金、化鎳浸金（ENIG)、化錄把 浸金（ENEPIG)及化學鍍錫（Immersion Tin)所組成 之群組中之其中一者。 100112523 表單編號A0101 第4頁/共15頁 1002020874-0 201241981 [0010] —本發0轉提供—種封裝紐之製法，係包括：提供 線路板，係具有交互相疊之至少一介電層與線路層， 且具有相對之第—表面及第二表面，該第-表面上設有 複數第一電性接觸墊及複數第二電性接觸墊，又 蓉笛 ♦ /、I ，該 一電性接觸墊係圍繞該等第二電性接觸墊，且該第 一電性接觸塾之寬度係大於該第二電性接觸^ 二 面、該第—電性接觸塾及第二電性接觸墊上 ο t成第—阻層’且該第—阻層具有複數第-開孔，以令 各=第-電性接觸塾對應外露於各該第—開孔；於各: 第開孔外露之第一電性接觸塾上形成直柱型銅凸塊； 以及移除該第-阻層，俾令該直柱型銅凸塊高於該第二 電I·生接觸塾’該直柱型銅凸塊之寬度係小於該第一電性 接觸整之寬度’該直柱型銅凸塊綺以藉由料連接其 土板且該第—表面、第—電性接觸塾、第二電性接 觸塾、與純型銅凸塊表面係外露於環境中。 [0011] ο [0012] 依上所迷之封裝基板之製法，該第二表面復可具有 複數第三電性接觸塾。 別述之封裝基板之製法中，形成該直枉型銅凸塊之 v驟系可。括.於形成該第一阻層前，於該核心板之第 表 s等第一電性接觸墊及第二電性接觸蛰上形成 導電層；於該導電層上形成該第-阻層，且該第-阻層 中形成該等第1孔；電卿成該直柱型銅凸塊；以及 移除該第—阻層之步驟復包括移除該第-阻廣所覆蓋之 導電層。 [0013] 100112523 二知’由 1002020874-0 201241981 裝結構的金屬凸塊係明顯高於置晶用電性接觸墊，所以 能有效提高層疊封裝件（POP)對晶片的容許厚度，並避 免相互堆疊之封裝結構有非預期的碰觸，且可使用較小 直徑焊球，進而能改善後續封裝結構的可靠度。 【實施方式】 [0014] [0015] [0016] [0017] 以下藉由特定的具體實施例說明本發明之實施方式 ，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 請參閱第2A至2F圖，係本發明之封裝基板及其製法 的剖視圖。 如第2A圖所示，提供一線路板20，係具有交互相疊 之至少一介電層（未以元件符號標示）與例如内層線路 201的線路層，且具有相對之第一表面20a及第二表面 20b，該第一表面20a上設有複數第一電性接觸墊211及 複數第二電性接觸墊212，其中，該等第一電性接觸墊 211係圍繞該等第二電性接觸墊212，且該第一電性接觸 墊211之寬度係大於該第二電性接觸墊212之寬度，且該 第二表面20b復具有複數第三電性接觸墊213。 如第2B圖所示，於該核心板20之第一表面20a、該等 第一電性接觸墊211及第二電性接觸墊212上形成導電層 22 〇 如第2C圖所示，於該導電層22上形成該第一阻層2 3a ，且該第一阻層23a中形成有複數第一開孔230，以令各 該第一電性接觸墊211對應外露於各該第一開孔230，並 100112523 表單編號A0101 第6頁/共15頁 1002020874-0 [0018] 201241981 層23^。表面2〇b與第三電性接觸塾213上形成該第二阻 [0019] 垃餓航第2D圖所不’於各該第-開孔230外露之第-電性 接觸墊川均成錄_料24。 [0020] 〇 如第2E圖所示，移除該第二阻層⑽、該第—阻層 ;雪所覆蓋之導電層22 ’俾令該直柱型銅凸塊24高於 =一:性接觸她，該直枝型銅凸塊“之寬度係小於 人 性接觸墊211之寬度，且該第一表面20a、第一 電性接觸塾211、第二電性接觸塾212、與直柱型銅凸塊 Μ表面係外露於環境卜 幻凸塊 [0021] 人如第21?囷所示’將第-晶片26覆晶（flip chip) λ第—電性接觸墊2i2並以封裝材料27包覆，再另 提供接置有第二晶片31的封裝結構3，該封裝結構3以 其植球側的例如焊球32的焊料連接至本發明之直柱型銅 凸塊2 4頂面。 ❾ [0022] 本發明復提供一種封裝基板，係包括：線路板2〇 ’ 係具有父互相疊之至少一介電層與線路層，且具有相對 之第一表面20a及第二表面20b ;複數第一電性接觸墊 211，係設於該第一表面2〇a上；複數第二電性接觸墊 212，係設於該第一表面2〇a上，其中，該等第一電性接 觸墊211係圍繞該等第二電性接觸墊212，且該第一電性 接觸墊211之寬度係大於該第二電性接觸墊212之寬度，· 以及直柱型銅凸塊24，係設於各該第一電性接觸墊211上 ，且該直柱型銅凸塊24與該第一電性接觸塾2丨1之間係具 100112523 表單編號A0101 第7頁/共15頁 1002020874-0 201241981 有一導電層22，其中，該直柱型銅凸塊24之寬度係小於 該第一電性接觸墊211之寬度，且該直柱型銅凸塊24係高 於該第二電性接觸墊212，以供該直柱型銅凸塊24藉由焊 料連接至其他基板，同時，該第一表面20a、第一電性接 觸墊211、第二電性接觸墊212、與直柱型銅凸塊24表面 係外露於環境中。 [0023] [0024] [0025] [0026] 所述之封裝基板中，該第二表面20b復可具有複數第 三電性接觸墊213。 於上述之封裝基板中，該導電層22之材料係可選自 由電鑛鎳/金、化學鍍鎳/金、化錄浸金（ENIG)、化鎳 ί巴浸金（ENEPIG)及化學鍍錫（Immersion Tin)所組 成之群組中之其中一者。 綜上所述，相較於習知技術，由於本發明之封裝基 板用以連接其他封裝結構的金屬凸塊（例如直柱型銅凸 塊24)係明顯高於置晶用電性接觸墊（例如第二電性接 觸墊212)，所以能有效提高層疊封裝件（package on package，簡稱POP)對晶片的容許厚度，並避免相互堆 疊之封裝結構有非預期的碰觸，且可使用較小直徑焊球 ，而能防止迴銲時的橋接，進而能改善後續封裝結構的 可靠度。 上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均 可在不違背本發明之精神及範疇下，對上述實施例進行 修改。因此本發明之權利保護範圍，應如後述之申請專 100112523 表單編號A0101 第8頁/共15頁 1002020874-0 201241981 利範圍所列。 【圖式簡單說明】 [0027] 第1圖係習知之層疊封裝件之剖視圖；以及 [0028] 第2Λ至2F圖係本發明之封裝基板及其製法的剖視圖 【主要元件符號說明】 [0029] 11、12 封裝結構 [0030] 111 ' 121 晶片 [0031] 112 ' 122 焊墊 [0032] 13 > 32 焊球 [0033] D 晶片封裝區域深度 [0034] 20 線路板 [0035] 20a 第一表面 [0036] 20b 第二表面 [0037] 201 内層線路 [0038] 211 第一電性接觸墊 [0039] 212 第二電性接觸墊 [0040] 213 第三電性接觸墊 [0041] 22 導電層 [0042] 23a 第一阻層 100112523 表單編號A0101 第9頁/共15頁 1002020874-0 201241981 [0043] 230 第一開孔 [0044] 23b 第二阻層 [0045] 24 直柱型銅Λ塊 [0046] 26 第一晶片 [0047] 27 封裝材料 [0048] 3 封裝結構 [0049] 31 第二晶片 100112523 表單編號 A0101 第 10 頁/共 15 頁 1002020874-0201241981 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a package substrate and a method of fabricating the same, and more particularly to a package substrate having a straight pillar type copper bump and a method of fabricating the same. [0002] 先前 [Prior Art] With the development trend of miniaturization of electronic products, the area of printed circuit board (pCB) surface for mounting semiconductor package structure is getting smaller and smaller, so a three-dimensional stacking technology of semiconductor package structure has been developed. The plurality of semiconductor package structures are stacked on each other to form a package on package (POP) to meet the requirements of small surface bonding area and high density component placement. [0003] Referring to FIG. 1 ' is a cross-sectional view of a conventional laminated package, as shown in the 'well-known stacked package, two package structures 11, 12 having wafers 1 and 121 are stacked on each other' and directly soldered. The ball 丨 3 is connected so that the two package structures 11, 12 are spaced apart from each other without touching each other. [0004] However, in order to ensure that the two package structures 11, 12 do not touch each other, conventional techniques generally use a larger diameter solder ball 13 to deepen the depth of the chip package area D' which makes the solder ball 13 The larger the volume and the larger the surface area of the package substrate, which is not conducive to the reduction of the area of the package substrate; in addition, the gap between the pads 112, 122 on the package substrate is getting more and more in the trend of miniaturization of modern electronic products. It is small, so when the reflow connection is made, the large-sized solder ball 13 easily overflows to the periphery and causes bridging, which leads to the generation of defective products. [0005] Therefore, how to avoid the solder ball of the laminated package in the prior art accounts for 100,112,523, and the bridge substrate area is too large, and it is easy to cause bridging during reflow, and the form is compiled A0101 Page 3 of 151002020874- 0 201241981 The problem of declining overall yield has become a problem that is currently being resolved. SUMMARY OF THE INVENTION [0006] In view of the above-mentioned various deficiencies of the prior art, the main object of the present invention is to provide a package substrate having a high yield and a method of manufacturing the same. To achieve the above and other objects, the present invention discloses a package substrate, comprising: a circuit board having at least one dielectric layer and a circuit layer alternately stacked, and having opposite first and second surfaces; An electrical contact pad is disposed on the first surface; a plurality of second electrical contact pads are disposed on the first surface, wherein the first electrical contact pads surround the second electrical contacts a pad, and the width of the first electrical contact pad is greater than the width of the second electrical contact pad; and the straight-type copper bump is disposed on each of the first electrical contact pads, and the straight-type copper The conductive layer is formed between the bump and the first electrical contact pad, wherein the width of the straight-type copper bump is smaller than the width of the first electrical contact pad, and the straight-type copper bump is Higher than the second electrical contact pad for connecting the straight-type copper bumps to other substrates by soldering, while the first surface, the first electrical contact pads, the second electrical contact pads, and the straight The surface of the cylindrical copper bump is exposed to the environment. In the foregoing package substrate, the second surface may have a plurality of third electrical contact pads. According to the above package substrate, the material of the conductive layer 22 can be selected from the group consisting of electric shovel recording/gold, electroless plating/gold, nickel immersion gold (ENIG), immersion gold (ENEPIG) and electroless tin plating (Immersion). One of the groups consisting of Tin). 100112523 Form No. A0101 Page 4 of 15 1002020874-0 201241981 [0010] The present invention provides a method for manufacturing a package, comprising: providing a circuit board having at least one dielectric layer alternately stacked with each other a circuit layer having opposite first surface and second surface, wherein the first surface is provided with a plurality of first electrical contact pads and a plurality of second electrical contact pads, and a whistle ♦ /, I, the electrical The contact pads are disposed around the second electrical contact pads, and the width of the first electrical contact pads is greater than the second electrical contacts, the first electrical contacts, and the second electrical contact pads. And forming a first-perforation layer, and the first-resistive layer has a plurality of first-opening holes, so that each of the first-first electrical contacts is exposed to each of the first openings; and each of the first openings is exposed Forming a straight-type copper bump on the electrical contact ;; and removing the first-resistive layer, so that the straight-type copper bump is higher than the second electrical contact 塾' the straight-column copper bump The width is less than the width of the first electrical contact. The straight-post type copper bumps are connected to the soil plate by the material and the first Surface, the - Sook electrical contact, a second contact electrically Sook, based copper bumps to the surface of a pure type is exposed to the environment. [0012] According to the manufacturing method of the package substrate, the second surface may have a plurality of third electrical contact ports. In the method of fabricating a package substrate, the straight copper bumps may be formed. Forming a conductive layer on the first electrical contact pad and the second electrical contact pad of the first s of the core plate before forming the first resistive layer; forming the first resistive layer on the conductive layer, And forming the first holes in the first resist layer; forming the straight pillar type copper bumps; and removing the first resist layer comprises removing the conductive layer covered by the first resist. [0013] 100112523 Two knows that the metal bump system of the structure of 1002020874-0 201241981 is significantly higher than the electrical contact pad for the crystallizing, so that the allowable thickness of the stacked package (POP) to the wafer can be effectively improved, and the stacking is prevented from being stacked on each other. The package structure has unintended touches and smaller diameter solder balls can be used, which improves the reliability of subsequent package structures. [0017] [0017] [0017] [0017] [0017] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can easily understand other aspects of the present invention from the disclosure of the present specification. Advantages and effects. 2A to 2F are cross-sectional views showing a package substrate of the present invention and a method of manufacturing the same. As shown in FIG. 2A, a circuit board 20 is provided having at least one dielectric layer (not labeled by a component symbol) and a circuit layer such as an inner layer line 201, and having a first surface 20a and a first surface opposite thereto. The second surface 20b is provided with a plurality of first electrical contact pads 211 and a plurality of second electrical contact pads 212, wherein the first electrical contact pads 211 surround the second electrical contacts The pad 212 has a width greater than a width of the second electrical contact pad 212, and the second surface 20b has a plurality of third electrical contact pads 213. As shown in FIG. 2B, a conductive layer 22 is formed on the first surface 20a of the core board 20, the first electrical contact pads 211 and the second electrical contact pads 212, as shown in FIG. 2C. The first resistive layer 23a is formed on the conductive layer 22, and a plurality of first openings 230 are formed in the first resistive layer 23a, so that the first electrical contact pads 211 are correspondingly exposed to the first openings. 230, and 100112523 Form No. A0101 Page 6 / Total 15 Page 1002020874-0 [0018] 201241981 Layer 23^. The second resistance is formed on the surface 2〇b and the third electrical contact 塾213. [0019] The first electrical contact pad exposed in the first opening 230 is not recorded. _ material 24. [0020] As shown in FIG. 2E, removing the second resist layer (10), the first resist layer; and the conductive layer 22' covered by snow, so that the straight-type copper bump 24 is higher than = one: Contacting her, the straight-branched copper bumps have a width smaller than the width of the human contact pads 211, and the first surface 20a, the first electrical contact 塾211, the second electrical contact 塾212, and the straight-type copper bump The surface of the block is exposed to the environment of the bucking bump [0021] As shown in FIG. 21, the flip-chip λ-electro-contact pad 2i2 is covered with the encapsulation material 27, Further, a package structure 3 is provided in which the second wafer 31 is attached, and the package structure 3 is connected to the top surface of the straight-type copper bumps 24 of the present invention with solder on the ball-side side thereof, for example, solder balls 32. ❾ [0022 The present invention further provides a package substrate, comprising: a circuit board 2 〇 ′ having at least one dielectric layer and a circuit layer stacked on each other, and having a first surface 20 a and a second surface 20 b opposite to each other; The contact pad 211 is disposed on the first surface 2〇a; the plurality of second electrical contact pads 212 are disposed on the first surface 2〇a, wherein The first electrical contact pads 211 surround the second electrical contact pads 212, and the width of the first electrical contact pads 211 is greater than the width of the second electrical contact pads 212, and the straight columns The copper bumps 24 are disposed on the first electrical contact pads 211, and the straight copper bumps 24 and the first electrical contacts 塾2丨1 are connected to each other 100112523 Form No. A0101 No. 7 Page 15 of 1002020874-0 201241981 has a conductive layer 22, wherein the width of the straight-type copper bumps 24 is smaller than the width of the first electrical contact pads 211, and the straight-type copper bumps 24 are high. The second electrical contact pad 212 is configured to connect the stud-type copper bumps 24 to other substrates by soldering, and the first surface 20a, the first electrical contact pads 211, and the second electrical contact pads 212, and the surface of the straight-type copper bumps 24 is exposed to the environment. [0025] [0025] [002] [0021] In the package substrate, the second surface 20b may have a plurality of third electrical contacts Pad 213. In the above package substrate, the material of the conductive layer 22 is optional from nickel or gold, electroless nickel/gold, and gold immersion gold. ENIG), one of a group consisting of ENEPIG and Immersion Tin. In summary, compared to the prior art, the package substrate of the present invention is used. The metal bumps (for example, the straight-type copper bumps 24) connected to other package structures are significantly higher than the metal contact pads (for example, the second electrical contact pads 212), so that the package can be effectively improved. On package (referred to as POP) to the allowable thickness of the wafer, and to avoid unintended contact with the package structure stacked on each other, and can use smaller diameter solder balls, can prevent bridging during reflow, and thus improve the subsequent package structure Reliability. The above-described embodiments are intended to illustrate the principles of the invention and its advantages, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as listed in the following application form 100112523 Form No. A0101 Page 8 of 15 1002020874-0 201241981. BRIEF DESCRIPTION OF THE DRAWINGS [0027] FIG. 1 is a cross-sectional view of a conventional laminated package; and [0028] FIG. 2 to 2F are cross-sectional views of a package substrate of the present invention and a method of manufacturing the same [main element symbol description] [0029] 11, 12 package structure [0030] 111 '121 wafer [0031] 112 '122 pad [0032] 13 > 32 solder ball [0033] D chip package area depth [0034] 20 circuit board [0035] 20a first surface 20b second surface [0037] 201 inner layer line [0038] 211 first electrical contact pad [0039] 212 second electrical contact pad [0040] 213 third electrical contact pad [0041] 22 conductive layer [ 0042] 23a first resistive layer 100112523 Form No. A0101 Page 9 of 15 1002020874-0 201241981 [0043] 230 First opening [0044] 23b Second resisting layer [0045] 24 Straight cylindrical copper block [0046] 26 First wafer [0047] 27 Package material [0048] 3 Package structure [0049] 31 Second wafer 100112523 Form number A0101 Page 10 of 15 1002020874-0

Claims (1)

201241981 七、申請專利範圍： 1 . 一種封裝基板，係包括： 線路板，係具有交互相疊之至少一介電層與線路層， 且具有相對之第一表面及第二表面； 複數第一電性接觸墊，係設於該第一表面上； 複數第二電性接觸墊，係設於該第一表面上，其中， 該等第一電性接觸墊係圍繞該等第二電性接觸墊，且該第 一電性接觸墊之寬度係大於該第二電性接觸墊之寬度；以 及 ◎ 直柱型銅凸塊，係設於各該第一電性接觸墊上，且該 直柱型銅凸塊與該第一電性接觸墊之間係具有一導電層， 其中，該直柱型銅凸塊之寬度係小於該第一電性接觸墊之 寬度，且該直柱型銅凸塊係高於該第二電性接觸墊，以供 該直柱型銅凸塊藉由焊料連接至其他基板，同時，該第一 表面、第一電性接觸墊、第二電性接觸墊、與直柱型銅凸 塊表面係外露於環境中。 2 .如申請專利範圍第1項所述之封裝基板，其中，該第二表 U 面復具有複數第三電性接觸墊。 3.如申請專利範圍第1項所述之封裝基板，其中，該導電層 之材料係選自由電鍍錄/金、化學鍍錄/金、化鎳浸金、化 錄Ιε浸金及化學鑛錫所組成之群組中之其中一者。 4 . 一種封裝基板之製法，係包括： 提供一線路板，係具有交互相疊之至少一介電層與線 路層，且具有相對之第一表面及第二表面，該第一表面上 設有複數第一電性接觸墊及複數第二電性接觸墊，其中， 100112523 表單編號Α0101 第11頁/共15頁 1002020874-0 201241981 該等第一電性接觸墊係圍繞該等第二電性接觸墊，且該第 一電性接觸墊之寬度係大於該第二電性接觸墊之寬度； 於該第一表面、該第一電性接觸墊及第二電性接觸墊 上形成第一阻層，且該第一阻層具有複數第一開孔，以令 各該第一電性接觸墊對應外露於各該第一開孔； 於各該第一開孔外露之第一電性接觸墊上形成直柱型 銅凸塊；以及 移除該第一阻層，俾令該直柱型銅凸塊高於該第二電 性接觸墊，該直柱型銅凸塊之寬度係小於該第一電性接觸 墊之寬度，該直柱型銅凸塊係用以藉由焊料連接其他基板 ，且該第一表面、第一電性接觸墊、第二電性接觸墊、與 直柱型銅凸塊表面係外露於環境中。 5 .如申請專利範圍第4項所述之封裝基板之製法，其中，該 第二表面復具有複數第三電性接觸墊。 6 .如申請專利範圍第4項所述之封裝基板之製法，其中，形 成該直柱型銅凸塊之步驟係包括： 於形成該第一阻層前，於該核心板之第一表面、該等 第一電性接觸墊及第二電性接觸墊上形成導電層； 於該導電層上形成該第一阻層，且該第一阻層中形成 該等第一開孔； 電鍍形成該直柱型銅凸塊；以及 移除該第一阻層之步驟復包括移除該第一阻層所覆蓋 之導電層。 100112523 表單編號A0101 第12頁/共15頁 1002020874-0201241981 VII. Patent application scope: 1. A package substrate, comprising: a circuit board having at least one dielectric layer and a circuit layer alternately stacked, and having a first surface and a second surface opposite to each other; The first contact pads are disposed on the first surface, and the first electrical contact pads are disposed around the second electrical contact pads. And the width of the first electrical contact pad is greater than the width of the second electrical contact pad; and ◎ straight-type copper bumps are disposed on each of the first electrical contact pads, and the straight-type copper a conductive layer is formed between the bump and the first electrical contact pad, wherein a width of the straight-type copper bump is smaller than a width of the first electrical contact pad, and the straight-type copper bump is Higher than the second electrical contact pad for connecting the straight-type copper bumps to other substrates by soldering, while the first surface, the first electrical contact pads, the second electrical contact pads, and the straight The surface of the cylindrical copper bump is exposed to the environment. 2. The package substrate of claim 1, wherein the second surface U has a plurality of third electrical contact pads. 3. The package substrate according to claim 1, wherein the material of the conductive layer is selected from the group consisting of electroplating/gold, electroless plating/gold, nickel immersion gold, chemical Ιε immersion gold, and chemical mineral tin. One of the group consisting of. A method of manufacturing a package substrate, comprising: providing a circuit board having at least one dielectric layer and a circuit layer alternately stacked, and having opposite first and second surfaces, wherein the first surface is provided a plurality of first electrical contact pads and a plurality of second electrical contact pads, wherein: 100112523 Form No. 101 0101 Page 11 / Total 15 Pages 1002020874-0 201241981 The first electrical contact pads surround the second electrical contacts a pad, and the width of the first electrical contact pad is greater than the width of the second electrical contact pad; forming a first resist layer on the first surface, the first electrical contact pad and the second electrical contact pad, The first resistive layer has a plurality of first openings, so that the first electrical contact pads are correspondingly exposed to the first openings; and the first electrical contact pads exposed on the first openings are formed straight. a pillar-shaped copper bump; and removing the first resist layer to make the straight-type copper bump higher than the second electrical contact pad, the width of the straight-type copper bump is smaller than the first electrical property The width of the contact pad, the straight-type copper bump is used for soldering Bonding another substrate and the first surface, a first electrical contact pad, a second electrical contact pad, and copper bumps Straight lines exposed surface to the environment. 5. The method of fabricating a package substrate according to claim 4, wherein the second surface has a plurality of third electrical contact pads. The method of manufacturing the package substrate according to claim 4, wherein the step of forming the straight-type copper bump comprises: before forming the first resist layer, on the first surface of the core plate, Forming a conductive layer on the first electrical contact pad and the second electrical contact pad; forming the first resist layer on the conductive layer, and forming the first openings in the first resist layer; a pillar-shaped copper bump; and the step of removing the first resist layer includes removing the conductive layer covered by the first resist layer. 100112523 Form No. A0101 Page 12 of 15 1002020874-0
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CN108231729A (en) * 2017-12-29 2018-06-29 通富微电子股份有限公司 A kind of package substrate, chip packing-body and chip stack package method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105225975A (en) * 2014-05-27 2016-01-06 矽品精密工业股份有限公司 Package structure and method for fabricating the same
CN108231729A (en) * 2017-12-29 2018-06-29 通富微电子股份有限公司 A kind of package substrate, chip packing-body and chip stack package method

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