TW201225216A - Multi-gate transistor devices and manufacturing method thereof - Google Patents

Abstract

A method for manufacturing multi-gate transistor devices includes providing a semiconductor substrate having a first patterned hard mask for defining at least a first fin formed thereon, forming the first fin having a first crystal plane orientation on the semiconductor substrate, forming a second patterned hard mask for defining at least a second fin on the semiconductor substrate, forming the second fin having a second crystal plane orientation that is different from the first crystal plane orientation on the semiconductor substrate, forming a gate dielectric layer and a gate layer covering a portion of the first fin and a portion of the second fin on the semiconductor substrate, and forming a first source/drain in the first fin and a second source/drain in the second fin, respectively.

Description

201225216 VI. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a multi-gate transistor element, particularly a gate with different crystal plane orientations. A method of fabricating a polar crystal element. [Prior Art] The important goal of continuous research and development in the semiconductor industry is to increase the efficiency of semiconductor components and reduce the power consumption of semiconductor components. How to continuously increase the performance of semiconductor components remains a problem that semiconductor manufacturers are trying to solve. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a pMOS transistor having a n-channel metal-oxide-semiconductor (nMOS) transistor element having a stereo channel and a stereo channel. A multi-gate transistor element for crystal plane orientation that enhances carrier mobility and a method of fabricating the same. According to the patent application scope provided by the present invention, a method of fabricating a multi-gate transistor element is provided. The method first provides a semiconductor substrate having a first patterned hard mask defining at least one first fin structure. The first fin structure is then formed on the semiconductor substrate, and the first fin structure has a first crystal plane orientation. After forming the second fin structure of the 201225216, a second patterned hard mask for defining at least one second fin structure is formed on the semiconductor substrate, and then a second fin structure is formed on the semiconductor substrate. The second fin structure has a second crystal plane orientation 'and the second crystal plane orientation is different from the first crystal plane orientation. Forming the second fin structure to form a gate dielectric layer and a gate layer on the first die structure and the second die structure. The gate dielectric layer and the gate layer cover portion The m structure and a portion of the Hth structure. Finally, a -first source/drain is formed in the first-Korean structure and a second source/drain is formed in the second die structure. According to the scope of the patent application provided by the present invention, a multi-question complementary metal oxide semiconductor (4) is provided, and the multi-gate CMOS device includes a semiconductor substrate, and is disposed on the semiconductor. a first-to-slice structure having a -plane-plane orientation on the substrate, disposed on the semiconductor substrate and having a second crystal plane oriented second fin structure, and disposed on the semiconductor substrate and covering the portion a rotor structure and a gate layer and a gate dielectric layer of the second fin structure, wherein the first crystal plane orientation is different from the second crystal plane orientation. According to the present invention, a terrestrial electric (four) component and a method of fabricating the same, are respectively formed on a semiconductor substrate to form a first rotor having a first crystal plane orientation: a second Zhao structure having a second crystal plane orientation And the second crystal plane orientation of the first crystal plane orientation 14 may be (10)) and (1) 0) oriented. (110) Orientation and (10)) 201225216 direction can respectively improve the carrier mobility of pMOS multi-gate transistor elements and 11 centistokes and 8 gates of transistor elements, so the multi-gate transistor element provided by the present invention The manufacturing method is to provide a CMOS component with south efficiency. [Embodiment] 第 FIGS. 1 to 3 and 5 to 8 , FIGS. 1 to 3 and 5 to 8 are multi-gate transistor elements provided by the present invention. A schematic diagram of one of the first preferred embodiments of the fabrication method. As shown in FIG. 1, the preferred embodiment first provides a semiconductor substrate 2, and the semiconductor substrate 2 can include a germanium insulation (41丨(:011_011_丨11阳1咖1>, 8〇1) The substrate, as known to those skilled in the art, includes a substrate 202, a bottom oxide (BOX) layer 204, and a semiconductor formed on the bottom oxide layer 204 from bottom to top. The layer, such as a layer 206, and the layer 206 has a crystal plane orientation of (100). However, in order to provide better heat dissipation and grounding effects, and to help reduce cost and suppress noise, the preferred embodiment The semiconductor substrate 200 may also include a bulk silicon substrate. As shown in FIG. 1 'the semiconductor substrate 200 is formed with a patterned hard mask 210a, and the patterned mask 21a is used to define a The Fin section of the multi-gate transistor component. Please continue to refer to Figure 1. After the patterned hard mask 21〇a is formed, a first etching process is performed, which is etched through the patterned hard mask 21〇a. The germanium layer 206' of the semiconductor substrate 200 forms a fin structure (fin) 2 12a. And as shown in Fig. 1 of 201225216, the fin structure 212a has a pair of opposing side walls 214a. It is noted that in the preferred embodiment, the first etching process is a dry etching process. The dry (four) process system includes sulphur hexafluoride muscle and/or three gasified nitrogen (NF3). The dry etching process etches the germanium layer anisotropically, so that the sidewall 214a of the die structure 212a is perpendicular to the semiconductor substrate 2〇〇; the cross-section of the fin structure 2i2a has one rectangle. More importantly, after the dry etching process, the sidewall 2Ma of the fin structure 212a has a first crystal plane orientation, and in the preferred embodiment, the first crystal plane orientation is (100) 〇 see the second Figure and Figure 3. Next, a patterned hard mask 210b is formed on the semiconductor substrate 200 for defining a Fin# knife of a multi-gate transistor element. As shown in FIGS. 2 and 3, the patterned hard mask 21〇a and the patterned hard mask 21 〇b are coplanar (co_planar). A second etching process is then performed to form another wafer structure 2 i 2 b through the patterned hard mask 21〇b|insect semiconductor substrate. It will be appreciated by those skilled in the art that in order to protect the wheel temple of the slab structure 2Ua from the second (four) process, the preferred embodiment forms a protective layer on the rotator structure 212a, for example to define a patterned hard The photoresist layer of the mask 210b is not limited thereto. It should be noted that in the preferred embodiment, the second surname engraving process includes a secret engraving (four) coffee (four) manufacturing. For example, the preferred embodiment of the wet (10) process (10) is a solution, and the ratio of ammonium hydroxide to water (_) is 丨: 7 wherein X is less than 250. In addition, the wet etching process of the preferred embodiment may further comprise hydrogen 201225216 tetramethylammonium hydroxide (TMAH) solution, wherein the concentration of cerium is less than 2.5%. In the preferred embodiment, the wet etching process is performed at a temperature of 20-6 (TC. The wet etching process is isotropically etched the layer 206, so that the sidewall 214b of the fin structure 212b is not vertical. In detail, the cross-section of the fin structure 212b may be formed in a trapezoidal shape on the semiconductor substrate 200 as shown in FIG. 2; or as shown in FIG. On the semiconductor substrate 200. More importantly, after the wet etching process, regardless of whether the fin structure 212b has a trapezoidal or inverted trapezoidal shape, the sidewall 214b of the fin structure 212b has a second crystal plane orientation and a second crystal plane. The orientation is different from the first crystal plane orientation of the sidewall 214a of the fin structure 212a. In the preferred embodiment, the second crystal plane orientation is (110). In addition, in the preferred embodiment, the second etch process Preferably, a two-stepped etch process is first performed by first etching the ruthenium layer 206 anisotropically using a dry etch process comprising SF6 and/or NF3 to form the fin structure 212b, the sidewall of the fin structure 212b. Is perpendicular to the semiconductor substrate 200. Next utilized A wet etching process comprising an ammonium hydroxide solution or a TMAH solution isotropically etched at a side wall ' perpendicular to the fin structure 212b of the semiconductor substrate 200 at 20-60 ° C to obtain a film as shown in FIG. 3 or FIG. 4, The side wall 214b is inclined to the surface of the semiconductor substrate 200. As described above, the dumpling in the wet etching process has a second crystal face regardless of whether the fin structure 212b has a trapezoidal or inverted trapezoidal shape. Orientation, and the second crystal plane orientation 201225216 'in this comparison = the first plane orientation of the sidewall 214a of the rotor structure 212a is better, the second crystal plane orientation is (1) 〇). Please refer to FIG. 4, which is a schematic diagram of a preferred embodiment of the multi-gate transistor of the present invention. In a second preferred embodiment of the present invention, the first-money engraving process may be the two-step etching process of the above-mentioned single-wet money engraving process or the dry quenching thirst etching as described above. . The first etching process is performed by patterning the hard mask layer 206' so that the surface of the semiconductor substrate 200 is first formed into a trapezoidal or inverted trapezoidal shape (as shown in Fig. 3). And as described above, after the secret engraving process, the sidewalls 2Mb of the structure (10) having a trapezoidal or inverted trapezoidal fin structure 212b have a plane orientation, and the crystal plane orientation is in the preferred embodiment. For (11 〇). In the second preferred embodiment, the second process is a dry process.

The process is used to form a fin structure 2i2a as shown in Fig. 2 on the semiconductor substrate 200 by patterning the hard mask 21Ga (4) layer. The sidewall 214a of the rotor structure 2]& is perpendicular to the semiconductor substrate 2〇〇; in other words, the fin structure η, since the dry-engraving process is anisotropically etched. The wearing system has a rectangle. More importantly, after the dry fine boring process, the sidewall 214a of the singular structure 2Ua has a crystal plane and the crystal is (100). You 201225216 Next, please refer to Figure 5 to Figure 8. It should be noted that, since the first preferred embodiment and the second preferred embodiment have the same steps after the present invention has the same steps as the second preferred embodiment, the steps are 5 to 8 are described later without being separately described. As shown in FIG. 5, after the fabrication of the element fin structure 212a and the fin structure 212b, a dielectric layer (not shown) and a gate Z layer are sequentially formed on the semiconductor substrate 2GG (Fig. And a patterned hard mask 216, and then patterning the (4) layer and the gate forming layer, and forming a pattern on the semiconductor substrate 2〇0 covering the partial rotor structure 212a and the partial chip structure 212b Electrical layer 218 · " gate layer 220. As shown in FIG. 5, the gate dielectric layer 218 and the gate layer 220 extend in a direction perpendicular to the extending direction of the fin structure 212a and the fin structure 21, and the gate dielectric layer 218 and the gate layer 22 The tether covers a portion of the sidewall 2] 4a of the fin structure 212a and a portion of the sidewall 214b of the fin structure 212b. The inter-electrode dielectric layer 218 may comprise a dielectric material such as a oxidized stone (SiO), a tantalum nitride (SiN), or a bismuth oxynitride (Si〇N). In the preferred embodiment, the gate dielectric layer 218 may further comprise a high-k material, such as oxygen (Hf〇), HfSi(R) or aluminum, Metal oxides such as ruthenium and osmium, or metal silicates, etc., but are not limited thereto. In addition, when the gate dielectric layer 218 of the preferred embodiment is made of high_K material, the present description can be integrated with a metal gate process to provide a control electrode sufficient to match the high-K gate dielectric layer. . Accordingly, the gate layer 22 can be provided with a different gate material for the gate-first process or the gate_last process of the alloy gate. For example, when the preferred embodiment is integrated with the front gate process 10 201225216, the gate layer 220 may comprise a metal such as a group (Ta), titanium (butadiene), ruthenium (Ru), molybdenum (Mo), Or an alloy of the above metals, a metal nitride such as a nitride nitride (TaN), a nitrided (TiN), a molybdenum nitride (MoN), or the like, a metal carbide such as a carbonized button (butyl ac), or the like. And the selection of the metals is based on the principle of the conductive form of the multi-gate transistor element to be obtained, that is, the metal satisfying the required work function of the N-type or p-type transistor is the selection principle, and the gate layer 22 The crucible may be a single layer structure or a multi-layer structure. When the preferred embodiment is integrated with the back gate process, the gate layer 220 is used as a dummy gate, which may include a semiconductor material such as polycrystalline stone. In addition, in the preferred embodiment, since the tops of the fin structure 2123 and the fin structure 212b are as shown in FIG. 5, the patterned hard mask 2 and the patterned hard mask are respectively employed, so Unable to form the channel area (10) coffee ^ reg1〇n). In other words, the channel region of the transistor in the preferred embodiment is formed in the gate layer 220 and the gate dielectric layer 218 covering the sidewalls of the rotor structure 2143 and the sidewall 214b covering the rotor structure 212b. At the office. Therefore, the multi-gate transistor component provided by the preferred embodiment is a double-pole transistor. More importantly, because the fin structure is such that the wall 214a is covered by the gate layer 22 〇 and the gate dielectric layer 218 and has a first crystal plane orientation, that is, (10) crystal plane orientation, it is advantageous for the sinking. Carrier mobility in the transistor channel region. Similarly, since the structure 2Ub is covered by the (4) fine and inter-electrode dielectric layer 218, the second crystal plane orientation, i.e., the crystal plane orientation, is advantageous for the carrier mobility of the pMOS transistor channel region. 201225216 In addition, the present invention is not limited to removing the patterned hard masks 210a, 210b after forming the fin structures 212a, 212b, and obtaining a tri-gate after subsequent fabrication of components such as source/drain electrodes. Transistor element. Although the sidewalls of the fin structure 212b have different crystal plane orientations after the patterned hard mask 210b is removed, the sidewalls 214b of the fin structure 212b have a second crystal plane orientation, ie, a (110) crystal plane orientation. Therefore, the carrier mobility of the pMOS transistor channel region is still favorable. Please refer to Figure 6. After the fabrication of the gate dielectric layer 218 and the gate layer 220 is completed, an n-type lightly doped germanium is formed in the fin structure 212a and the fin structure 212b by using different conductivity types of oblique ion implantation. Light-doped drain (LDD) 222a and a p-type light-changing pole 222b (shown in Figure 8). It is worth noting that the sidewall 214a of the fin structure 212a has a (100) crystal orientation that favors the nMOS transistor element; and the sidewall 214b of the tab structure 212b has a (no) φ crystal orientation that favors the pMOS transistor component. Therefore, regardless of the order in which the fin structures 212a and 212b are formed, the fin structure 212a having a (1 〇〇) crystal orientation is a formation place of the n-type LDD 222a at the time of LDD fabrication; and has a (110) crystal. The fin structure 212b is the formation site of the P-type LDD 222b. After the n-type lightly doped 222a and the P-type lightly doped 222b are formed, the sidewalls 224 are formed on the opposite sidewalls of the gate layer 220 and the gate dielectric layer 218, and the sidewall 224 may be a single layer. Structure or composite layer structure. 12 201225216 Please refer to Figure 7. After forming the sidewalls, the present invention can perform a selective epitaxial growth (SEG) process to expose the sidewalls 214a of the fin structures 210a outside the patterned hard masks 210a, 210b, 216 and The sidewall 214b of the fin structure 210b forms an epitaxial layer 226a and an epitaxial layer 226b, respectively. As previously mentioned, since the sidewall 214a of the fin structure 212a has a (100) crystal orientation that favors the nMOS transistor element; the sidewall 214b of the fin structure 212b has a (110) lure orientation that favors the pMOS transistor element. 'Therefore, when the crystal layer 226a and the worm layer 226b are formed, the worm layer 226a contains bismuth carbon (SiC); and the epitaxial layer 226b contains germanium (SiGe) for providing the subsequently formed nMOS transistor element. The stress required with the pMOS transistor component. In addition, a recess may be selectively formed on the sidewall 214a of the fin structure 210a and the sidewall 214b of the fin structure 210b before the SEG process, so that the subsequently grown epitaxial layer 226a and the epitaxial layer 226b are respectively formed. The stress provided acts more effectively on the channel regions of the nMOS transistor elements and the pMOS transistor φ elements. Please refer to Figure 8. Please note that Figure 8 is a cross-sectional view taken along line A-A' in Figure 7. Subsequently, an n-type source/drain 228a is formed in the fin structure 212a and a p-type source/drain 228b is formed in the fin structure 212b by means of ion implantation of different conductivity types. As previously mentioned, since the sidewall 214a of the fin structure 212a has a (100) crystal orientation that favors the nMOS transistor element; the sidewall 214b of the fin structure 212b has a (110) crystal orientation that favors the 201225216 pMOS transistor component. Therefore, when the source/drain is fabricated, the fin structure 212a having a (100) crystal orientation is a formation place of the n-type source/drain 228a; and the fin structure 212b having a (110) crystal orientation is formed. Then, it is a formation place of the p-type source/drain 228b. It is also worth noting that the <ion implantation process described in the preferred embodiment is not limited to the SEG process, or even in-situ incorporation of the n-type source/drain 228a in the SEG process. The dopants required for the p-type source/drain 228b are substituted for the ion implantation described above and the desired tempering process. As shown in FIG. 8, after the fabrication of the n-type source/drain 228a and the p-type source/drain 228b is completed, an nMOS transistor 230a and a pMOS transistor 230b are completed on the semiconductor substrate 200. The manufacture of CMOS components. The method for fabricating a polysilicon gate transistor device according to the present invention 'the channel region of the pMOS transistor 230b is formed on the (110) crystal plane orientation obtained by the wet etching process by the surname layer 206, thus facilitating To improve its carrier mobility. The nMOS transistor 230a is disposed on the (100) crystal plane orientation obtained only by the dry etching etch process, thereby contributing to the improvement of carrier mobility. Further, as shown in Fig. 7, the method for fabricating the polycrystalline silicon gate of the present invention is more suitable for providing a CMOS device including an nMOS transistor and a pMOS transistor. Please refer to FIG. 9A and FIG. 9B. FIG. 9A is a circuit diagram of a typical six-transistor static random access 14 201225216 memory '6T-SRAM memory unit; The 9B diagram is a 6T-SRAM layout (iayout) diagram. The general 6T-SRAM memory cell 100 is composed of a pM〇s transistor 112/114 as a pull-up transistor (pUll_Up transist〇r) and an nMOS transistor 122/124 as a pull-down transistor. And two nMOS transistors 126/128 as access transistors (access transistors). The pMOS transistor 112 is connected in series with the nMOS transistor 122, and the pM〇S transistor 114 is connected in series with the nMOS transistor 124. The above transistors 112, 114, 122, and 124 form a latch circuit for storing data. As shown in Figs. 9A and 9B, in the fabrication of nMOS transistors and pM〇S transistors to be connected in series, the method of fabricating the multi-gate transistor of the present invention can be utilized. Please refer to FIG. 7 to FIG. 9B simultaneously. The gate electrode layer 220 can be used as the gate of the series pMOS transistor 丨12 and the nM〇s transistor 122 according to the method for fabricating the multi-gate transistor device according to the present invention. The nM〇s transistor 23〇a serves as the pull-down transistor 122, and the pMOS transistor 230b serves as the pull-up transistor 112. Similarly, the gate layer 220 can serve as the gate of the series pMOS transistor 114 and the nMOS transistor 124, and the nMOS transistor 230a serves as the pull-down transistor 124; the pMOS transistor 230b acts as the pull-up transistor! 14. As described above, since the channel region of the pMOS transistor 230b is formed in the (11 〇) crystal plane orientation obtained by etching the lithographic layer 206 by the wet etching process; and the ηΜ〇§ transistor 23〇a It is disposed on the (丨00) crystal plane orientation obtained by etching the germanium layer 206 only by the dry etching process. Therefore, the method for fabricating the multi-gate transistor device according to the present invention can simultaneously improve the two types of conductivity type. The carrier of the crystal element migrates 15 201225216 without the purpose of degrading the characteristics of the opposite conductivity type transistor element. In addition, after the fabrication of the nMOS transistor 230a and the pMOS transistor 230b is completed, a metal silicide process can be performed to form a metallization on the surface of the epitaxial layer 226a and the crystal layer 226b (not shown). ) for reducing the sheet resistance of the n-type source/drain 228a and the p-type source/drain 228b. Next, an inter-layer dielectric (ILD) layer (not shown) may be formed on the semiconductor substrate 200. As described above, when the preferred embodiment is integrated with the gate process after the metal gate, the gate layer 220, which is a dummy gate, is removed after being formed into the inner dielectric layer. According to the different electrical requirements of the nMOS transistor 230a and the pMOS transistor 230b, a metal that satisfies the required work function, a metal with a low resistance value or a better hole filling capability, and an adjustable metal work function are filled. The metal is post-annealed (卩(^11^313111^3b?)^8). In addition, the preferred embodiment can also be integrated with the high-K last process, that is, the gate is removed. After the pole layer 220, the gate dielectric layer 218 is also removed, and a gate dielectric layer having a high dielectric constant material is newly formed therein, and then a metal gate process is performed. After the fabrication, the original ILD layer can be removed, and a contact etch stop layer (CESL) or a contact etch stop layer (CESL) is formed on the surface of the semiconductor substrate 200 between the nMOS transistor 230a and the pMOS transistor 230b having metal gates. Stress layer. In other words, the present invention can integrate selective stress such as CESL Selective strain scheme (SSS), 16 201225216 improves the performance of the nMOS transistor 230a and the pMOS transistor 230b with metal gates, and is formed on the surface of the semiconductor substrate 200 after the fabrication of the selective stress system is completed. An ILD layer (not shown) is formed therein to form a contact hole exposing the source/drain 228a/228b. It is worth noting that the metal telluride is more susceptible to the high thermal budget of the metal deposition and metal post-annealing. Process influence, therefore, in the present invention, the metal telluride process can be postponed until after removing the ILD layer, before forming the CESL or stress layer, or even after the φ f reforms the ILD layer and forming the contact hole, to avoid The effect of the above-mentioned warm-temperature process on the metal lithium compound. Because the above-mentioned process of metal-week process, ILD layer formation process, metal-question process and selective stress system are well known to those skilled in the art, No longer repeat them. , '', two above, according to the hair _ provided by the multi-gate transistor element and its ^ side = using the first _ process and the second saki The formation of the structure and the orientation of the second crystal plane with the second crystal plane orientation is (100) 盥 (1) 0) the orientation of the fixed crystal plane is respectively - (4) the base of the simple electric solar particle . In other words, ηΜ0; body: (iv) mobility can be formed by the invention according to the invention two = electricity (four) (four). Therefore, the 2#; crystal 17 201225216 body manufacturing method provided by the present invention provides a highly efficient CMOS component. The above is only the preferred embodiment of the present invention, and all changes and modifications made to the patent scope of the present invention should be covered by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 to FIG. 3 and FIG. 5 to FIG. 8 are schematic diagrams showing a first preferred embodiment of a method for fabricating a multi-gate transistor device according to the present invention, wherein the eighth embodiment Figure 7 is a cross-sectional view taken along line AA, tangential; Figure 4 is a schematic view of a second preferred embodiment of the method for fabricating a multi-gate transistor element provided by the present invention; A circuit diagram of a typical six-crystal SRAM memory cell; and a 9B-SRAM layout of the heart. [Major component symbol description] 100 Six-transistor SRAM cell 112, 114 Pull-up transistor 122 > 124 Pull-down transistor 126, 128 Access transistor 200 Semiconductor substrate 202 矽 Substrate 204 Bottom oxide layer 206 矽Layer 210a patterned hard mask 210b patterned hard mask 212a fin structure 212b fin structure 18 201225216 214a sidewall 214b sidewall 216 patterned hard mask 218 gate dielectric layer 220 gate layer 222a n-type light doping Pole 222b ρ-type lightly doped 235 side wall 226a worm layer 226b worm layer 228a n-type source / immersion 228b P-type source / immersion 230a NMOS transistor 230b PMOS transistor 19

Claims (1)

201225216 VII. Patent application scope: 1. A method for manufacturing a multi-transistor component, comprising: a fossil substrate; the semiconductor substrate is formed with a first patterned hard mask for defining at least one first wafer Structure (4); = the first Korean sheet structure is formed on the conductor substrate, and the structure has a -first plane orientation (4) - _ _ _ 峨); the rotor forms at least a second rotor structure on the shaker conductor substrate; Forming the second rotor structure on the semiconductor substrate has a second plane orientation, and: a fin-fin surface orientation; the first-day surface orientation is different from the first crystal - Transfer structure and layer and - gate layer, Tuen Mun W. Forming an inter-electrode dielectric μ ^ Μ gate; 1 electrical layer and the gate layer covering f Qiu 8 > sheet structure and part of the H-th structure; and "(4) a fin respectively in the first-rotary structure In the two-rotor structure, a source of two sources/=first-source/no-pole is formed in the second method. For example, the method of Wei (in the application) is directed to (100). The crystal plane is set to 20 201225216. The method of claim 3, wherein the dry etching process comprises at least sulfur hexafluoride (SF6) or nitrogen trifluoride (NF3). King 5. The method of claim 1 And wherein the second crystal h direction is (1) 0). The method of claim 5, further comprising at least an engraving process for forming the second fin structure. The method of claim 6, wherein the wet__ comprises at least an ammonium hydroxide solution (NH4〇H) or a tetramethylammonium hydroxide 'TMAH solution. The method of item 5, wherein the cross section of the first structure has a trapezoidal or inverted trapezoid. , , , Q 9. The method of claim 2, wherein the second structure is formed after the first fin structure, wherein, the first rotor 1 is as described in claim 1, The structure is formed after the second fin structure. The method of claim 1, wherein the first patterned 21 201225216 hard mask is coplanar with the second patterned hard mask. The method of claim 2, further comprising forming a first lightly doped drain (LDD) and the first fin structure and the second fin structure respectively; A second lightly doped drain step. 13. The method of claim 12, further comprising the step of forming a sidewall on the sidewall of the gate layer to form the first light blend After the second pole is doped with the second lightly doped drain. 14. The method of claim i, further comprising forming a first on the first (four) structure and the second returning structure respectively Step of a stupid layer and a first worm layer. The conductor (C 〇 mple nie nie nie nie nie nie nie nie nie nie nie a second fin structure disposed on the semiconductor substrate, the second crystal plane is oriented, and the second crystal and the second fin surface orientation are different from the first structure having a crystal plane directional gate layer A gate dielectric layer is disposed on the semiconductor substrate, and the layer 22 201225216 and the gate dielectric layer cover a portion of the first fin structure and the first fin structure. [4] A multi-gate complementary metal oxide element as described in claim 15 of the patent range wherein the flute a ^, medium. The head of the Haidi-crystal plane is (_’ the orientation of the second crystal plane is A multi-gate complementary MOS device according to claim 16 wherein the cross section of the first Korean structure has a rectangular shape, and the cross section of the second structure has a trapezoidal or inverted trapezoidal % %Specially surrounding the multi-gate complementary MOS-strips described in Item 15 wherein the first material structure further comprises a plurality of poles, and the second Korean structure further comprises a plurality of second nudges Miscellaneous. The multi-gate complementary MOS semi-conductive flute described in Item 15 of the patent _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ It also includes a plurality of second source/drain electrodes. The plurality of gate complementary metal oxide semiconductors are disposed on the gate layer and the gate dielectric layer 20. The body element of the fifteenth body of the patent application includes a sidewall of a sidewall. The multi-gate complementary MOS device according to claim 15, wherein the first fin structure further comprises a plurality of first epitaxial layers, and the second fin structure further comprises A plurality of second epitaxial layers. For example, the application of the (4) section of the Μ 互补 互补 互补 互补 互补 ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ For example, the < $ Μ% $ body element described in claim 15 of the patent scope, the complementary gold-oxygen semiconductor is in the mth..." μ layer--the extension direction is the vertical fin, the structure and the second fin Sheet structure - extending direction. Eight patterns twenty four