201214968 六、發明說明： 【發明所屬之技術領域】 本心月係有關於-種移位暫存器，尤指一種可增加驅動能力以 及降低動態功率消耗之移位暫存器。 【先前技術】 先前技術將移位暫存器製作在玻璃基板上，所採用的製程係為 非晶石夕或多祕製程技術，由於其材質賴子遷移率低，在一定的 操作電壓下，需要設計較大的_電晶體，才能有效驅動面板的掃 描線。然而越大的_電晶體所產生的寄生電容效應也越大，造成 驅動電路上的_功率雜也讀上升。因此將移位暫存器作在基 板上’雜可以節省閘極驅動晶片之成本，但卻增加動態功率之消 耗。 先前技術係姻移㈣存n的上㈣職升移位暫存器的輸出 級電晶體的閘極的電位。當輸出級電晶體接收高頻時脈訊號時，閘 極的電位會因為在移位暫存||的輸出級電晶體的閘極與源極之間的 麵接電容_係更往上拉升。但在歧技射，輸出級電晶體的閉 極的電位在被耦接電容拉升之前，受限於上拉電路的緣故，只能充 電至VGH-Vth(VGH係為時脈訊號的高電壓準位，^係為輸出級電晶 體的閥值電壓)無法充電至更高電位。因此，先前技術魏增加部: 輸出級電晶體的驅動能力。 201214968 【發明内容】 本發明的-實關提供-種可增加驅域力之第n級移位暫存 器。該第η級移位暫存器包含-下拉電路、—上拉電路、一驅動電 路、一第-電容及-關鍵下拉電路。該下拉電路係用以利用—第— 節點的電位及至少-低頻時脈滅，將該第—節點的電位下拉至該 第η級移位暫存器的輸出節點的電位以及該第η級移位暫存器的輪 出節點的電钉拉至-參考減位；該场電路係雛於該下拉電 ^用以使用—第η_2級移位暫存器的輸出訊號，第—次上拉該第 -節點的電位’和-第^級移位暫存器的輸出訊號或—第一高頻 時脈訊號，第二次上拉該第-節點的電位；該驅動電路係雛於該 j拉電路’肋根據-第二高鱗脈訊號，改魏第η級移位暫存 裔的輸出節點的電位；該第—電容_以根據該第二高頻時脈味 號，透過該驅動電路提升該第-節_電位；及該_下拉電路係 =妾於該駆動電路，用以使用-第η+2級移位暫存器的輸出訊號， 遠第-節點的電位和該第η級移位暫存器的輸出節點的電位 至該參考低電位。 、、本發明的另-實施例提供-種増加移位暫存器驅動能力之方 法。該方法包含使用-第η·2級移位暫存器的輸出訊號將一第η 級的-第-節點充電至-第-電位，和—第二節點充電至一第二^ 位；使用-第W級移位暫存器的輸出訊號或—第—高頻時脈= 號’將該第二節點提升至—第三電位，其中該第三電位大於該第一 201214968 電位；使用該第三電位和該第一電位’將該第一節點充電至一第四 電位；及使用一第二高頻時脈訊號的高電位，將該第一節點提升至 一第五電位以及將該第η級移位暫存器的輸出節點充電至該高電 位。 本發明所提供的一種可增加驅動能力之第η級移位暫存器及增 加移位暫存器驅動能力之方法’係利用一上拉電路二次拉升用以驅 動一驅動電路的第一節點的電位，然後再利用一高頻時脈訊號及一 第一電容第三次拉升該第一節點的電位。因此，謂第—節點的電位 有二階段的抬升，以增加該驅動電路的驅動電流。而當該驅動電路 有更大的驅動電流後，可將該驅動電路的通道寬度縮小，如此該驅 動電路的寄生電容也跟著縮小，因而降低該驅動電路的動態功率消 耗。 【實施方式】 △凊參照第1圖，第1圖係為本發明的一實施例說明可增加驅動 b力之第η級移位暫存器⑽的示意圖。第η級移位暫存器包 3下拉電路1〇2、上拉電路1〇4、驅動電路1〇6、第一電容⑽及關 鍵下拉電路110。下拉電路脱係利用第-節點Q⑻的電位及第一 低頻時脈魏un、第二低頻時脈訊號LC2，將第一節點⑽的電 拉至第η、.及移位暫存_ 1〇㈣輸出節點g⑻的電位以及將第。 及移位暫存器1〇〇的輸出節點G⑻的電位下拉至參考低電位。 上拉電路1〇4係搞接於下拉電路⑽，利用第η_2、級移位暫存器的 201214968 輸出訊號G(n-2) ’第一次上拉第一節點Q(n)的電位，和第n_i級移 位暫存器的輸出訊號G(n-l)，第二次上拉第一節點Q(n)的電位。驅 動電路106係耦接於上拉電路1〇4與下拉電路1〇2，用以根據第二 高頻時脈訊號HC2，改變第η級移位暫存器的輸出節點G(n)的電 位。第一電容⑽係用以根據第二高頻時脈訊號HC2，第三次上拉 第一節點Q(n)的電位。關鍵下拉電路110係耦接於驅動電路1〇6、 上拉電路1〇4與下拉電路102，用以使用第n+2級移位暫存器的輸 出訊號G(n+2)，將第一節點Q⑻的電位和第n級移位暫存器的輸出 節點G(n)的電位下拉至參考低電位Vss。 上拉電路104包含第一電晶體1042、第二電晶體馳、第三電 晶體1046、第四電晶體1048及第二電容1〇5〇。第一電晶體we 具有第-端，用以接收第n-2級移位暫存器的輸出訊號^_2)，第 二端耗接於第-端’及第三端输於第二節點s(n)。第二電晶體腦 具有第一端，収接收第n_2級移位暫存器的輸出訊號G(n_2)，第 二端輕接於第-端，及第三端柄接於第—節點Q(n)。第三電晶體 1046具有第一端，用以接收第n]級移位暫存器的輸出訊號G(n_i)， 第山-端_於第二節點S⑻，及第三端。第四電晶體购具 二2ΓΓΓs⑻，第二魅接於第1，及第三端耗接於 及第-軌I電谷1〇50具有第一端，轉接於第二節點S(n)， 接於第三電晶體藝的第三端。第—電晶體_、第 :上晶體義及第，體_係為-_ 201214968 下拉電路102包含第-下拉㈣電路贈、第三下拉控制電路 1024、第一下拉電路1〇26及第二下拉電路1〇28。第一下拉控制電 路1022係根據第-節點q⑻的電位和第一低頻時脈訊號lci，產 生第-下拉控制訊號P(n)。第二下拉控制電路職係根據第一節點 Q⑻的電位和第二低頻時脈訊號奶，產生第二下拉控制訊號 K(n)第下拉電路1026係柄接於第一下拉控制電路ίο?〕、第一 郎點Q(n)及第η級移位冑存器的輸出節點G(n)，用以根據第一下拉 控制訊號P⑻’將第-節點Q⑻的電位下拉至第續移位暫存器的 輸出節點G⑻的電位，以及將第n級移位暫存器的輸出節點G⑻ 的電位下減參考低電位VSS。第二下拉電路丨⑽係減於第二 下拉控制電路職、第-節·點Q⑻及第n級移位暫存⑽輸出節點 G⑻，用崎據第二下拉控制訊⑻，將第—節點Q⑻的電位下 拉至第η級移位暫存器的輸出節點G⑻的電位，以及將第n級移位 暫存器的輸ίϋ節點G⑻的電位下拉至參考低電位vss。另外，第一 低頻時脈訊號LC1和第二低頻時脈訊號LC2係互為反向訊號。 «月參照第2圖，第2圖係說明第一高頻時脈訊號HC1、第二高 頻時脈峨HC2、第三高頻時脈訊號HC3和第四高頻時脈訊號⑽ 之間的關係的示意圖。驅動電路1〇6係用以根據第二高頻時脈訊號 產生第n級移位暫存器的輸出訊號，亦即第〇級移位暫存器 的輸出㈣G(n)的電位；第η]級移位暫存器的驅動電路係用以根 據第-尚頻時脈訊號HC1 ’產生第η_ι級移位暫存器的輸出訊號 201214968 G㈣；第n-2級移位暫存器的驅動電路係用以根據第四高頻時脈訊 號HC4，產生第n-2級移位暫存器的輪出訊號邮_2);第n_3級移 位暫存器雜動電路_以根據第三高辦脈訊號⑽ ，產生第n-3 級移位暫存ϋ的輸出罐G㈣。第叫辦脈訊號脳和第二高 頻時脈喊HC2互為反向城n猶奇數祕位暫存器的驅動 電路產生輸出錢’以及第-高頻時脈訊號HCi和第三高頻時脈訊 號HC3亦互為反向職，且用以讓偶數級移位暫存㈣驅動電路產 生輸出机號。但第四南頻時脈訊號HC4和第二高頻時脈訊號HC2 亦此用以讓偶數級移位暫存㈣驅動電路產生輸出訊號，以及第— 尚頻喊HC1和第三高_械訊號HC3亦_以讓奇數級移 位暫存器的驅動電路產生輸出訊號。 請參照第3A圖和第3B圖，第3A圖係說明第一次上拉第一節 點Q(n)的電路動作的示意圖，第3B圖係說明第n_2級移位暫存器 的輸出訊號G(n-2)、第n-l級移位暫存器的輸出訊號G(n_i)、第n 級移位暫存器的輸出節點G(n)的電位、第n+2級移位暫存器的輪出 訊號G(n+2)、第二高頻時脈訊號HC2、第一節點Q⑻和第二節點 S(n)的電位的示意圖。如第3A圖所示，當第n-2級移位暫存器的輪 出訊號G(n-2)由低電位轉態至高電位時，第一電晶體1〇42、第四電 晶體1048和第二電晶體1〇44導通，此時輸出訊號G(n-2)對第一節 點Q(n)第一次充電至第一電位VI(亦即第一次上拉第一節點Q(n)的 電位），且輸出訊號G(n-2)亦對第二節點S⑻充電至第二電位V2。 如第3B圖的第一時段T1所示，可看出第一節點Q(n)的電位被第一 201214968 次上拉。 5月參照*4A圖和帛4B® ’第4A圖係說明第二次上拉第― 點Q⑻的電路動作的示意圖’第4B圖係說明第3B圖的第二時： T2之不意圖。如第4A圖所示，當第n七級移位暫存器的輸出訊 G(n-l)由低電位轉態至高電位時，第三電晶體雜導通(因為第 級移位暫存n的輸出峨G(n_2)仍為高電位，触第—電晶體 腿、第四電晶體卿和第二電晶體腦維持導通），此時輸出訊 说f(n 1)透過第二電晶體腿以及與第三電晶體觸純的第二 電谷1050提兩第二節點s⑻的電位至第三電位％，其中第三電位 V3大於第二電位v卜此時第二節點s⑻的第三電位％透過第四 電晶體1048對第—節點Q⑻第二次充電至第四電位科亦即第二乂 上拉第-節點Q(n)的電位）。如第4B圖的T2區間所示，可看人 一節點Q(n)的電位被第二次上拉。 珩 # 請參照第5A圖和第5B圖，第5A圖係說明第三次上拉第一節 = Q(I^電路動作的示意圖’第5B圖係說明第3B圖的第三時段 τι® g ®所不’當第二高頻時脈訊號蹈由低電位 ::、戶 =位時’驅動電路106因第-節點Q⑻被拉高的電位而導 1/ΛΟ 币〜阿頻時脈訊號HC2透過第一電踅 Q⑻的電位）。如第5B圖所示，可看出第—節點⑽的電位被第三 201214968 次上拉，以及第η級移位暫存H的輸出節如⑻的電位由低電位轉 為高電位。料，當第三高_脈訊號HC2由高電位轉態至低電位 時’第η級移位暫存器的輸出節點G⑻的電位亦會由高電位轉態至 低電位。 請參照第6Α圖和第6Β圖’第6Α圖係說明第η+2級移位暫存 器的輸出訊號G(n+2)由低電位轉態至高電位時，關鍵下拉電路ιι〇 的電路動作的示意圖’第6B圖係說明第3B圖的第四時段τ4之示 意圖。當輸出訊號G㈣由低電位轉態至高電位時，關鍵下拉電路 U〇所包含的第六電晶體_及第七電晶體_被開啟，因此輸 出節點G(n)的電位經由第六電晶體11()2放電至參考低電位卿、 第-節點Q⑻的電位經由第七電晶體丨觀放電至參考减位卿 及將第二節點S⑻的電位經由第四電晶體_及第七電晶體_ 放電至參考低電位VSS。 另外，由第2圖可知，第·| 罘η 1級移位暫存器的輸出訊號G( 和第一高頻時脈訊號的時序相同。因此，本發明的另-實施例 係將第㈣號咖 HC1取代，其餘的操作原理皆和 ^ 第n級移位暫存器100相同，在此 不再贅述。 另外’請參照第7圖，第7圖总*丄a 乐圖係為本發明的另一實施例說明可 增加驅動能力之第η級移位暫存器 κ子益的tf意U。第η級移位暫存 201214968 器700和第η級移位暫存器10㈣差異在於僅包含一下拉控制電路 7022與-下拉電路屬。第n級移位暫存器的其餘的操作原理 皆和第η級移位暫存器100相同，在此不再贅述。 請參照第請，第8圖係為本發明的另—實施例說明增加移位 暫存器驅動能力之方法之_圖。第8圖之方法係利用第】圖的第 η級移位暫存器1〇〇說明詳細步驟如下： 步驟800 :開始； 步驟802 :使用第二2級雜暫存器的輸出訊號啊），將第續 的第-節點Q⑻的電位充電至第一電位V1，和第二節點 S(n)的電位充電至第二電位 步卿：使用^級移位暫存=2出訊號G(n.糊一高頻 時脈峨Ηα，將第二_ s(n)的電位提升至第三電位 V3 ’其中第三電位V3大於第—電位V1 ; 步驟隊使用第三電位V3和第一電位νι，將第一節點q⑻的電 位充電至第四電位V4 ; 步驟職：根據^_脈峨HC2的高電位，拉升第n級移位 暫存益的輸出節點G⑻的電位，且第二高頻時脈訊號 H的高電㈣將第-節點Q⑻的電位_至第五電 步驟⑽：刪二高頻時脈訊號配2的低電位，將輸㈣點G⑻ 的電位放電至第二高頻時脈訊號HC2的低電位； 13 201214968 步驟812 :使用第n+2級移位暫存器的輪出訊號G(n+2)開啟第六電 晶體1102及第七電晶體1104，以將輸出節點G⑻的電 位、第-節點Q⑻的電位及第二節點s⑻的電位放電至 參考低電位VSS ; 步驟814 :結束。 在步驟8〇2中，係利用第n_2級移位暫存器的輸出訊號G(n·2) 開啟第η級移位暫存器的第-電晶體難及第二電晶體難，以 將第-節點Q⑻的電位充電至第一電位νι |σ第二節點s⑻的電位# 充電至第二電位V2。在步驟804中，係利用該第n]級移位暫存器 的輸出訊號G(n-l)或第一高頻時脈訊號HC1，藉由一 將第二節點S⑻的電位提升至第三電位V3，其中第三電位％大於 第一電位V卜在步驟806中，係利用第三電位％和第一電位％ 開啟第四電晶體卿，以將第—節點Q⑻的電位拉升至第四電位 V4。在步驟職中’係姻第二高頻時脈訊號脆的高電位藉由 第電谷1〇8將第一節點Q⑻的電位提升至第五電位V5。在步驟籲 812中係、利用開啟的第六電晶體聰將輸出節點G(n)的電位放電 至參考低電位VSS、開啟的第七電晶體麗將第—節點⑽的電 位放電至參考低電位vss以及經由第四電晶體翻及第七電晶體 Π04將第二節點S⑻的電位放電至參考低電位㈣。 知上所述’本發明所提供的可增加驅動能力之第η級移位暫存 器及增加移位暫存器驅動能力之方法，係利用上拉電路二次拉升用 14 201214968 以驅動驅動電路的第一節點的電位，然後再利用高頻時脈訊號及第 一電容第三次拉升第一節點的電位。因此’用以驅動驅動電路的第 一節點的電位有三階段的抬升，以增加驅動電路的驅動電流。而當 驅動電路的驅動能力上升後，驅動電路有更大的驅動電流，因此可 以將驅動電路的通道寬度縮小，如此寄生電容也跟著縮小，因而降 低動態功率消耗。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 •所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖係為本發明的一實施例說明可增加驅動能力之第η級移位暫 存器的示意圖。 第2圖係說明第—高辦脈訊號、第二高頻時脈^^號、第三高頻時 脈訊號和第四高頻時脈訊號之間的關係的示意圖。 #第3Α圖係說明第一次上拉第一節點的電路動作的示意圖。 第3Β圖係說明第η·2級移位暫存器的輸出訊號、第w級移位暫存 器的輸出訊號、第η級移位暫存器的輸出節點的電位、第啦 級移位暫存H的輸出織、第二高頻時脈峨、第—節點 二節點的電位的示意圖。 第4A圖係說明第二次上拉第一節點的電路動作的示意圖。 第4B圖係說明第3B圖的第二時段之示意圖。 .第5A圖係說明第三次上拉第一節點的電路動作的示意圖。 201214968 第 第 第 5B圖係說明第3B圖的第三時段之示旁圖。 6A圖係說明帛n+2級移位暫存器的輸出訊號由低電位轉態至高 電位時，關鍵下拉電路的電路動作的示意圖。 6B圖係說明第3B圖的第四時段之示意圖。 第7圖係為本發明的另—實施例說明可增加驅動能力之第續移位 暫存的不意圖。 第8圖係=發明的另—實施例說明增加移位暫存純動能力之方 【主要元件符號說明】 100、700 第η級移位暫存器 102 > 7024 下拉電路 104 上拉電路 106 驅動電路 108 第一電容 110 關鍵下拉電路 7022 下拉控制電路 1022 第一下拉控制電路 1024 第二下拉控制電路 1026 第一下拉電路 1028 第二下拉電路 1042 第一電晶體 1044 第二電晶體201214968 VI. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a type of shift register, and more particularly to a shift register capable of increasing drive capability and reducing dynamic power consumption. [Prior Art] The prior art has fabricated a shift register on a glass substrate, and the process used is an amorphous or multi-secret process technology. Due to the low mobility of the material, it is required at a certain operating voltage. Design a larger _ transistor to effectively drive the scan line of the panel. However, the larger the parasitic capacitance effect produced by the _ transistor, the higher the _ power miscellaneous read on the drive circuit. Therefore, shifting the scratchpad on the substrate can save the cost of the gate drive chip, but increase the consumption of dynamic power. The prior art system shifts (4) the potential of the gate of the output stage transistor of the upper (four) liter shift register. When the output stage transistor receives the high frequency clock signal, the potential of the gate is pulled up by the junction capacitance between the gate and the source of the output stage transistor of the shift register || . However, in the differential shot, the potential of the closed-pole of the output stage transistor is limited to the pull-up circuit before being pulled up by the coupling capacitor, and can only be charged to VGH-Vth (VGH is the high voltage of the clock signal). The level, ^ is the threshold voltage of the output stage transistor) can not be charged to a higher potential. Therefore, the prior art Wei added: the drive capability of the output stage transistor. 201214968 SUMMARY OF THE INVENTION The present invention provides an n-th stage shift register that can increase the driving force. The nth stage shift register includes a pull-down circuit, a pull-up circuit, a driving circuit, a cascode and a key pull-down circuit. The pull-down circuit is configured to pull down the potential of the first node to the potential of the output node of the nth stage shift register and the nth stage shift by using the potential of the -th node and at least the low frequency clock. The pin of the bit register of the bit register is pulled to the reference minus bit; the field circuit is used for the output signal of the n_2 stage shift register, and the first pull up The potential of the first node and the output signal of the first stage shift register or the first high frequency clock signal, the second time pulling up the potential of the first node; the driving circuit is in the j pull The circuit 'ribs according to the second high scale pulse signal, the potential of the output node of the Wei η shift shift temporary storage; the first capacitor _ is boosted by the drive circuit according to the second high frequency clock scent The first-segment_potential; and the_down-down circuit are used in the swaying circuit for using the output signal of the -n+2th stage shift register, the potential of the far-node and the η-th shift The potential of the output node of the bit register is low to this reference. Further, another embodiment of the present invention provides a method of driving a shift register drive capability. The method includes charging an -n-th node of the n-th stage to a -first potential using an output signal of the -n-2 stage shift register, and - charging the second node to a second bit; using - The output signal of the W-stage shift register or the -first-high frequency clock = No.' raises the second node to a third potential, wherein the third potential is greater than the first 201214968 potential; using the third The potential and the first potential 'charge the first node to a fourth potential; and use a high potential of the second high frequency clock signal to boost the first node to a fifth potential and the nth stage The output node of the shift register is charged to this high potential. The invention provides an n-th stage shift register capable of increasing driving capability and a method for increasing the driving capability of the shift register, which is a first pull-up circuit for driving a driving circuit by using a pull-up circuit. The potential of the node is then pulled up by the high frequency clock signal and a first capacitor for the third time. Therefore, the potential of the first node has a two-stage rise to increase the drive current of the drive circuit. When the driving circuit has a larger driving current, the channel width of the driving circuit can be reduced, so that the parasitic capacitance of the driving circuit is also reduced, thereby reducing the dynamic power consumption of the driving circuit. [Embodiment] Δ凊 Referring to Fig. 1, Fig. 1 is a schematic view showing an n-th stage shift register (10) capable of increasing the driving force b according to an embodiment of the present invention. The n-th stage shift register package 3 pull-down circuit 1〇2, pull-up circuit 1〇4, drive circuit 1〇6, first capacitor (10) and key pull-down circuit 110. The pull-down circuit is disconnected by using the potential of the first node Q(8) and the first low frequency clock Weiun and the second low frequency clock signal LC2, and pulling the electric current of the first node (10) to the nth, and shifting temporary storage_1〇(4) Output the potential of node g(8) as well as the first. And the potential of the output node G(8) of the shift register 1〇〇 is pulled down to the reference low potential. The pull-up circuit 1〇4 is connected to the pull-down circuit (10), and the potential of the first node Q(n) is pulled up for the first time by using the 201214968 output signal G(n-2) of the n_2 and the stage shift register. And the output signal G(nl) of the n_ith stage shift register, and the potential of the first node Q(n) is pulled up a second time. The driving circuit 106 is coupled to the pull-up circuit 1〇4 and the pull-down circuit 1〇2 for changing the potential of the output node G(n) of the n-th stage shift register according to the second high-frequency clock signal HC2. . The first capacitor (10) is used to pull up the potential of the first node Q(n) for a third time according to the second high frequency clock signal HC2. The key pull-down circuit 110 is coupled to the driving circuit 1〇6, the pull-up circuit 1〇4 and the pull-down circuit 102 for using the output signal G(n+2) of the n+2th stage shift register. The potential of one node Q(8) and the potential of the output node G(n) of the nth stage shift register are pulled down to the reference low potential Vss. The pull-up circuit 104 includes a first transistor 1042, a second transistor, a third transistor 1046, a fourth transistor 1048, and a second capacitor 1〇5〇. The first transistor we have a first end for receiving the output signal ^_2) of the n-2th stage shift register, the second end is consumed at the first end and the third end is outputted to the second node s (n). The second transistor brain has a first end receiving the output signal G(n_2) of the n-2th stage shift register, the second end is lightly connected to the first end, and the third end is connected to the first node Q ( n). The third transistor 1046 has a first end for receiving the output signal G(n_i) of the nth stage shift register, the second end S_8, and the third end. The fourth transistor purchases two 2 ΓΓΓ s (8), the second enchantment is connected to the first, and the third end is consuming and the first trajectory I 谷 〇 1 〇 50 has a first end, and is transferred to the second node S(n), Connected to the third end of the third transistor art. The first-transistor_, the first: the upper crystal and the first, the body_ is -_201214968 The pull-down circuit 102 includes a first-down (four) circuit gift, a third pull-down control circuit 1024, a first pull-down circuit 1〇26 and a second Pull down circuit 1〇28. The first pull-down control circuit 1022 generates a first-down pull control signal P(n) according to the potential of the first node q(8) and the first low frequency clock signal lci. The second pull-down control circuit grade generates a second pull-down control signal K(n) according to the potential of the first node Q(8) and the second low-frequency clock signal milk, and the pull-down circuit 1026 is connected to the first pull-down control circuit ίο? The first node Q(n) and the output node G(n) of the nth stage shift register are used to pull down the potential of the node Q(8) to the subsequent shift according to the first pulldown control signal P(8)' The potential of the output node G(8) of the register and the potential of the output node G(8) of the nth stage shift register are decremented by the reference low potential VSS. The second pull-down circuit 丨(10) is reduced from the second pull-down control circuit, the first-point-point Q(8), and the nth-level shift temporary storage (10) output node G(8), and the first node Q(8) is used by the second pull-down control signal (8). The potential is pulled down to the potential of the output node G(8) of the nth stage shift register, and the potential of the input node G(8) of the nth stage shift register is pulled down to the reference low potential vss. In addition, the first low frequency clock signal LC1 and the second low frequency clock signal LC2 are mutually inverted signals. «Monthly reference to Fig. 2, Fig. 2 illustrates the first high frequency clock signal HC1, the second high frequency clock 峨HC2, the third high frequency clock signal HC3 and the fourth high frequency clock signal (10) Schematic diagram of the relationship. The driving circuit 1〇6 is configured to generate an output signal of the nth stage shift register according to the second high frequency clock signal, that is, an output of the fourth stage shift register (4) G(n) potential; The drive circuit of the stage shift register is used to generate the output signal of the n_th stage shift register according to the first-frequency shift clock signal HC1' 201214968 G (4); the drive of the n-2th shift register The circuit is configured to generate an output signal of the n-2th stage shift register according to the fourth high frequency clock signal HC4; the n_3 stage shift register noise circuit _ according to the third The high pulse signal (10) generates the output tank G (4) of the n-3th shift temporary storage. The first call pulse signal 脳 and the second high frequency clock call HC2 mutual reverse city n yue number secret register drive circuit to generate output money 'and the first high frequency clock signal HCi and the third high frequency The pulse signal HC3 is also a reverse job, and is used to cause the even-numbered shift temporary storage (4) drive circuit to generate the output machine number. However, the fourth south frequency clock signal HC4 and the second high frequency clock signal HC2 are also used to cause the even-numbered shift temporary storage (four) driving circuit to generate an output signal, and the first-frequency frequency call HC1 and the third high-machine signal HC3 also generates an output signal for the drive circuit of the odd-numbered shift register. Please refer to FIG. 3A and FIG. 3B. FIG. 3A is a schematic diagram showing the circuit operation of the first pull-up first node Q(n), and FIG. 3B is a diagram showing the output signal G of the n-2th shift register. (n-2), the output signal G(n_i) of the nl-stage shift register, the potential of the output node G(n) of the n-th stage shift register, and the n+2th shift register Schematic diagram of the potentials of the turn-off signal G(n+2), the second high-frequency clock signal HC2, the first node Q(8), and the second node S(n). As shown in FIG. 3A, when the turn-off signal G(n-2) of the n-2th shift register is turned from a low potential to a high potential, the first transistor 1 〇 42 and the fourth transistor 1048 And the second transistor 1 〇 44 is turned on, at this time, the output signal G(n-2) charges the first node Q(n) to the first potential VI for the first time (that is, the first pull-up of the first node Q ( The potential of n) is), and the output signal G(n-2) also charges the second node S(8) to the second potential V2. As shown in the first period T1 of Fig. 3B, it can be seen that the potential of the first node Q(n) is pulled up by the first 201214968 times. A schematic diagram of the circuit operation of the second pull-up point Q (8) will be described with reference to *4A and 帛4B® '4A in May'. FIG. 4B illustrates the second time of FIG. 3B: T2 is not intended. As shown in FIG. 4A, when the output signal G(nl) of the nth-stage shift register is turned from a low potential to a high potential, the third transistor is turned on (because the output of the first stage shift register n)峨G(n_2) is still at a high potential, and the touch-transistor leg, the fourth transistor, and the second transistor are maintained in conduction. At this time, the output signal f(n 1) is transmitted through the second transistor leg and The third transistor touches the pure second electric valley 1050 to raise the potential of the two second nodes s (8) to the third potential %, wherein the third potential V3 is greater than the second potential v b at this time, the third potential % of the second node s (8) passes through The fourth transistor 1048 charges the second node of the node Q (8) to the fourth potential section, that is, the potential of the second 乂 pull-node Q(n). As shown in the T2 section of Fig. 4B, it can be seen that the potential of the human node Q(n) is pulled up a second time.珩# Please refer to Figure 5A and Figure 5B. Figure 5A shows the third pull-up of the first section = Q (the schematic diagram of the I^ circuit action). Figure 5B shows the third period of the 3B diagram τι® g ® does not 'when the second high-frequency clock signal is driven by a low potential::, household = bit' drive circuit 106 due to the potential of the first node Q (8) is pulled high 1 / ΛΟ ~ A frequency clock signal HC2 Pass the potential of the first electric 踅Q(8)). As shown in Fig. 5B, it can be seen that the potential of the first node (10) is pulled up by the third 201214968, and the output of the nth stage shift register H is turned from the low potential to the high potential as the output of (8). Therefore, when the third high_pulse signal HC2 transitions from a high potential to a low potential, the potential of the output node G(8) of the nth stage shift register also shifts from a high potential to a low potential. Please refer to Fig. 6 and Fig. 6 'Fig. 6 to illustrate the circuit of the key pull-down circuit ιι〇 when the output signal G(n+2) of the n+2 shift register is changed from low potential to high potential. Schematic diagram of the action 'FIG. 6B is a schematic diagram illustrating the fourth period τ4 of FIG. 3B. When the output signal G(4) is switched from the low potential to the high potential, the sixth transistor__ and the seventh transistor__ included in the critical pull-down circuit U〇 are turned on, so the potential of the output node G(n) is passed through the sixth transistor 11 ()2 discharge to the reference low potential, the potential of the first node Q (8) is discharged to the reference degraded via the seventh transistor and the potential of the second node S (8) is discharged via the fourth transistor _ and the seventh transistor _ To the reference low potential VSS. In addition, as can be seen from Fig. 2, the output signal G of the first stage shift register is the same as the timing of the first high frequency clock signal. Therefore, another embodiment of the present invention will be the fourth (fourth) The coffee maker HC1 is replaced, and the rest of the operation principle is the same as that of the n-th shift register 100, and will not be described here. In addition, please refer to Fig. 7, and the total figure is shown in Fig. 7. Another embodiment illustrates a tf meaning U of the n-th stage shift register that can increase the drive capability. The n-th stage shift register 201214968 700 and the n-th stage shift register 10 (four) differ only in The pull-down control circuit 7022 and the pull-down circuit are included. The remaining operating principles of the n-th shift register are the same as those of the n-th shift register 100, and will not be described here. 8 is a diagram illustrating a method of increasing the drive capability of a shift register according to another embodiment of the present invention. The method of FIG. 8 is a detailed description of the n-th shift register 1 of the first drawing. The steps are as follows: Step 800: Start; Step 802: Use the output signal of the second 2-stage miscellaneous register, and continue the first section The potential of Q(8) is charged to the first potential V1, and the potential of the second node S(n) is charged to the second potential step: using the stage shifting temporary storage = 2 output signal G (n. paste a high frequency clock 峨Ηα, raising the potential of the second _s(n) to the third potential V3′ where the third potential V3 is greater than the first potential V1; the step team using the third potential V3 and the first potential νι to increase the potential of the first node q(8) Charging to the fourth potential V4; Step: According to the high potential of ^_ pulse HC2, pull up the potential of the output node G(8) of the nth stage shifting temporary storage, and the high frequency of the second high frequency clock signal H (4) Putting the potential of the first node Q(8)_ to the fifth electrical step (10): deleting the low frequency of the high frequency clock signal with 2, discharging the potential of the input (four) point G(8) to the low potential of the second high frequency clock signal HC2; 201214968 Step 812: Turn on the sixth transistor 1102 and the seventh transistor 1104 by using the turn-off signal G(n+2) of the n+2th stage shift register to set the potential of the output node G(8), the node Q (8) The potential and the potential of the second node s (8) are discharged to the reference low potential VSS; Step 814: End. In step 8〇2, the n_2th stage shift is temporarily stored. The output signal G(n·2) turns on the first transistor of the nth stage shift register and the second transistor is difficult to charge the potential of the first node Q(8) to the first potential νι |σ second node The potential # of s(8) is charged to the second potential V2. In step 804, the output signal G(nl) of the nth stage shift register or the first high frequency clock signal HC1 is utilized, The potential of the two nodes S(8) is raised to the third potential V3, wherein the third potential % is greater than the first potential V. In step 806, the fourth transistor is turned on by using the third potential % and the first potential % to The potential of the node Q (8) is pulled up to the fourth potential V4. In the step of the operation, the high potential of the second high frequency clock signal is increased by the first valley Q 8 to raise the potential of the first node Q (8) to the fifth potential V5. In step 812, the potential of the output node G(n) is discharged to the reference low potential VSS by using the turned-on sixth transistor, and the potential of the first node (10) is discharged to the reference low potential by the turned-on seventh transistor. Vss and discharges the potential of the second node S(8) to the reference low potential (4) via the fourth transistor flip and the seventh transistor Π04. The method for increasing the driving capability of the n-th stage shift register and the method for increasing the driving capability of the shift register is provided by the pull-up circuit for the second pull-up 14 201214968 to drive the drive. The potential of the first node of the circuit is then pulled up by the high frequency clock signal and the first capacitor for the third time. Therefore, the potential of the first node for driving the driving circuit has a three-stage rise to increase the drive current of the drive circuit. When the driving capability of the driving circuit is increased, the driving circuit has a larger driving current, so that the channel width of the driving circuit can be reduced, and thus the parasitic capacitance is also reduced, thereby reducing the dynamic power consumption. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing an n-th stage shift register capable of increasing driving capability according to an embodiment of the present invention. Fig. 2 is a view showing the relationship between the first-high pulse signal, the second high-frequency clock ^^, the third high-frequency pulse signal, and the fourth high-frequency clock signal. #第3Α图 illustrates a schematic diagram of the circuit action of the first node being pulled up for the first time. The third diagram shows the output signal of the n-th stage shift register, the output signal of the w-th stage shift register, the potential of the output node of the n-th stage shift register, and the first-order shift. Schematic diagram of the potential of the output woven, the second high frequency clock, and the second node of the first node. Figure 4A is a schematic diagram showing the circuit operation of the first node for the second pull-up. Figure 4B is a schematic diagram illustrating the second time period of Figure 3B. Figure 5A is a schematic diagram showing the circuit operation of the first node for the third pull-up. 201214968 Fig. 5B is a side view showing the third time period of Fig. 3B. The 6A diagram illustrates the circuit operation of the critical pull-down circuit when the output signal of the 帛n+2 stage shift register transitions from a low potential to a high potential. 6B is a schematic diagram illustrating the fourth time period of FIG. 3B. Fig. 7 is a view showing another embodiment of the present invention for explaining the possibility of increasing the displacement of the drive capacity. Figure 8 is a further embodiment of the invention. The method for increasing the capacity of the shift temporary memory is explained. [Main element symbol description] 100, 700 n-th stage shift register 102 > 7024 pull-down circuit 104 pull-up circuit 106 Drive circuit 108 first capacitor 110 key pull-down circuit 7022 pull-down control circuit 1022 first pull-down control circuit 1024 second pull-down control circuit 1026 first pull-down circuit 1028 second pull-down circuit 1042 first transistor 1044 second transistor
201214968 1046 1048 1050 1102 1104 Q(n) S(n) 吻） ® VSS G(n-2)、G(n-l)、G(n+2) HC1 HC2 HC3 HC4 ΤΙ • T2 T3 T4 P⑻ K(n) LC1 LC2 800- 814 第三電晶體 第四電晶體 第二電容 第六電晶體 第七電晶體 第一節點 第二節點 輸出節點 參考低電位 輸出訊號 第一高頻時脈訊號 第二局頻時脈訊號 第二局頻時脈訊號 第四南頻時脈訊號 第一時段 第二時段 第三時段 第四時段 第一下拉控制訊號 第二下拉控制訊號 第一低頻時脈訊號 第二低頻時脈訊號 步驟 17201214968 1046 1048 1050 1102 1104 Q(n) S(n) Kiss) ® VSS G(n-2), G(nl), G(n+2) HC1 HC2 HC3 HC4 ΤΙ • T2 T3 T4 P(8) K(n) LC1 LC2 800- 814 Third transistor Fourth transistor Second capacitor Sixth transistor Seventh transistor First node Second node Output node reference Low potential output signal First high frequency clock signal Second local frequency clock Signal second local frequency pulse signal fourth south frequency clock signal first time second time third time third time fourth time first pull down control signal second pull down control signal first low frequency clock signal second low frequency clock signal Step 17