TW201140850A - Thin-film field-effect transistor and method for manufacturing the same - Google Patents

Abstract

A thin-film field-effect transistor with good TFT characteristics and high reliability, and a method for manufacturing the same are provided. In the thin-film field-effect transistor, at least a gate electrode, an insulating film, an active layer, an etching stop layer, a source electrode, and a drain electrode are formed on a substrate. The etching stop layer is formed on the active layer, and the source electrode and the drain electrode are formed on the etching stop layer. The etching stop layer comprises an amorphous oxide of In, Ga and Zn, wherein the concentration of Zn is less than 20%. The active layer comprises an amorphous oxide semiconductor of In, Ga and Zn, wherein the concentration of Zn is higher than that of the etching stop layer.

Description

201140850 JOZUipif VI. Description of the Invention: [Technical Field] The present invention relates to a thin film field effect transistor using an amorphous oxide semiconductor and a method for fabricating the same, and the method has a side P and a block A thin film field effect transistor having good layer and TTFT characteristics and high reliability, and a method of manufacturing the same. [Prior Art] At present, field effect transistors are widely used as semiconductor memory bulk circuits, high frequency signal amplification elements, and the like. Further, in the field effect transistor, a thin film field effect transistor (hereinafter also referred to as TFT) is used as a planar thin pattern of a liquid crystal display device (lcd), an electroluminescence display device (EL), and a field emission display (fED). A switching element such as a display device (Flat Panel Display: FPD). A TFT used in FPD is formed with an amorphous iridium film or a polycrystalline germanium film as an active layer on a glass substrate. The above-described TFT using an amorphous germanium film or a polycrystalline germanium film in the active layer requires a higher temperature thermal process. Therefore, although the glass substrate can be used for tft, it is difficult to use a resin substrate having low heat resistance. Further, for FPD, further reduction in thickness, weight reduction, and breakage resistance are required. It has been studied to use a lightweight and flexible resin substrate instead of a glass substrate. Therefore, development of a TFT using an amorphous oxide which can form a film at a low temperature has been actively carried out. A TFT using an amorphous oxide has a substrate, a gate electrode, a gate insulating film, a living oxide composed of an amorphous oxide semiconductor, a semiconductor layer, a source electrode, and a drain electrode (drainelectr〇). De), and forms a source and a drain on the active layer. In a TFT using an amorphous oxide, the source and the electrode are formed by the side conductive film, and in the case where the active layer does not form an etChing Stopperlayer which protects it, the source is formed. At the same time, the active layer may be etched at some time, and the characteristics of the TFT may be unstable. In the extreme case, the active layer is completely engraved, and sometimes the TFT characteristics are not displayed. In the above case, a TFT for the active layer layer 2 is provided (for example, refer to Japanese Patent Special: 20 (Japanese Unexamined Patent Publication No. Hei No. Hei No. Hei. No. Hei. No. Hei. No. Hei. No. 2009-141342). a second insulating film having a closed electrode, an ith insulating film as a film, an oxide semiconductor layer as a channel layer, an active layer, and a protective layer: the conductive layer includes a second conductive layer; In the case of a temperature-dependent detachment analysis, a channel-protected thin film transistor is disclosed in the Japanese Patent Publication No. 2009-21612, which is incorporated herein by reference. A gate is formed on the substrate, and a first gate insulating film is formed to cover the gate, and a second edge film is formed on the first gate insulating film. Further, the second gate insulating film is formed on the second insulating film. An oxide semiconductor film (corresponding to an active layer) is formed to cover the gate On the oxide semiconductor film, a channel protective film is formed in the _heavy (four) region, and the channel is prevented when the source semiconductor and the ruthenium channel protective film form a source and a drain. The semi-conducting part of the channel. The protective film of the channel is composed of oxidized stone (si0x), nitrite (siNJ yttrium (SiOxNy) (x>y), yttrium oxynitride (SiNx〇y), etc.: Japanese Patent Publication No. 2__141342 describes a thin grinding machine 2]= (TFT) having at least a gate electrode, an open film, an active layer of an amorphous oxide semiconductor, a source electrode and a gate electrode. The average root mean square of the interface of the transistor's active layer is less than 2 nm, the carrier depth of the active layer is greater than or equal to M0丨5/cm3, and the film thickness of the active layer is greater than or equal to 0.5 mn and less than 2 〇. In addition, the laminated layer has a low carrier concentration layer of amorphous === with a carrier concentration of less than or equal to ig1W. The protective film of the low carrier desert layer is free from the environment (moisture, oxygen) The role of the gate type ^本2 special open 2_-166716 under the insulation U, has the role of an etch barrier 2nd, ', and Bu' are purchased exclusively in Japan. The film of the publication No. 2_21612 is also provided with a channel protection film for preventing the semiconductor layer of the channel portion from being etched. In Japanese Laid-Open Patent Publication No. Hei. No. 2-166716, Japanese Laid-Open Patent Publication No. Hei No. 2 GG9-21612, a layer as a barrier layer is provided. As described above, an etching stopper layer is formed on the active layer, and the source and It is also recorded on the wire-like layer. In this case, when the shape is secret, the etching barrier must be processed. However, as disclosed in Japanese Laid-Open Patent Publication No. 2008-166716, Japanese Patent Application Publication No. Hei. No. Hei. In the case of the side, it is necessary to process the Lin test, and the processing of the fairy barrier layer is difficult to carry out. ^ In addition, when the film is formed on the active layer, and the film is called a side-stop layer, the active layer is damaged. Due to this damage, the active layer is reduced in resistance, and the (4) negative value of the TFT or TF ^ does not show the TFT operation. It is to be noted that (4) is that the illusion 2 film which is an etch barrier layer is formed by a sputtering method in a high-concentration oxygen atmosphere. According to the film formation conditions, the reduction in resistance of the active layer can be prevented. : The county that makes the Z low-resistance 'reverse channel of the active layer of the bottom layer', the price of the layer is composed of _, / value ^ large oxygen in the Japanese Patent Laid-Open No. 2009_141342 Phase _ low-concentration layer, as a layer that also produces Naga. However, according to the (four) condition when the source and the drain are formed, the low load 201140850 [the content of the invention or the reliability of the tft is lowered. The purpose of providing 22 is to solve the problem based on the above prior art, and the method of the i manufacturing method is good, and the method is also high, and the field effect of the thin field effect transistor is high. The first aspect of the present invention provides a thin film layer. Eclipse: the barrier layer is formed on the yoke plate at least with a gate electrode, an insulating film, an active source and a immersion electrode, and an upper L, f=擒 layer formed on the active layer is formed on the side barrier layer The above-mentioned source is characterized by: the above-mentioned side resistance: the amorphous oxygen of In, Ga and Zn having a concentration of less than 2% of Zn and the above active layer is composed of In containing An amorphous oxygen product semiconductor composed of Ga and Zn, and the Zn concentration is higher than the Zn concentration of the silver-etched barrier layer. In the present invention, the active Zn concentration refers to an amorphous oxide other than the oxygen source. The atomic concentration of Zn contained in the semiconductor film. As a method of calculating the Zn concentration, Zn concentration = [non = 曰 = amount of Zn atoms contained in the oxide semiconductor / (a amount of In atoms contained in the amorphous oxide 2 conductor film + amorphous oxide semiconductor) The amount of Ga atoms in the film 3 + the amount of Zn atoms contained in the amorphous oxide semiconductor film. The In concentration and the Ga concentration in the active layer are also the same as the Zn concentration, and the 'In concentration and the Ga concentration are also related to Zn. The concentration is determined by the calculation of the earth. 201140850 JOZUipif It should be noted that 'the concentration of Zn, the degree of Ino and Ga in the barrier layer of the present invention, the concentration of Zn in the active layer, and the concentration of In and

The same applies to the definition of the Zn concentration, the In concentration, and the Ga = degree in the active layer, and the "amorphous oxide semiconductor" is replaced by the "amorphous oxide film." Preferably, the etching barrier layer has an In concentration of 40% or more and a Ga concentration of 37 Å/〇. Further, the source and the drain are preferably made of molybdenum or a molybdenum alloy, and particularly preferably Further, the above-mentioned thin film field effect transistor may be any one of a top contact type bottom-gate structure or a top contact type upper gate (t〇p_gate) structure. Further, the above active layer and the above etching Preferably, the barrier layer has the same shape. The second aspect of the present invention provides a method for fabricating a thin film field effect transistor. The thin film field effect transistor has at least a via, an insulating film, an active layer, and an etch barrier formed on the substrate. a layer, a source, and a drain, and the money encapsulating layer is formed on the active layer, and the source and the drain are formed on the side resist layer, and the manufacturing method is characterized in that it has a use-containing fill And an aqueous solution of acetic acid and stone mixed acid as a surname, 'to form the source and the above-mentioned drain, the etching barrier layer is composed of an amorphous oxide containing ln, Ga&amp;Zn having a Zn concentration of less than 20%. The active layer is composed of an amorphous oxide semiconductor containing Ga and Zn, and the Zn concentration is still at the zn concentration of the above-mentioned barrier layer. 201140850 1 jJif* In this case, the silver-etched barrier layer is preferably The gas mixture is greater than or equal to 37%. The exhibitivity is greater than or equal to the above. Further, the mixed acid aqueous solution preferably contains 7% by mass of (tetra) acid, 5% by mass to 1% by mass of acetic acid, and % by mass of nitric acid. Before the process of the following steps: the process of forming the gate on the substrate; the process of forming the substrate on the substrate; the process of forming the active layer on the germanium insulating film; and the active layer Preferably, the top surface is formed by forming the source and the gateless forming layer, and forming the source and the drain on the substrate in the process of forming the source and the gate. Part of the above eclipse After the encapsulation layer ❶ wind replenishing, the process of forming the source and the above-mentioned drain electrode forms a layer on the upper plate to cover the barrier layer, the source and the drain. And, as another method, preferably, before the forming of the source process, the following process is performed: a process formed on the substrate; and a paste-forming layer formed on the active layer In the process of forming the source and the above-mentioned electrodeless, the above-mentioned secret upper pole is formed on the substrate, so as to cover the portion of the above-mentioned etched layer 'and in the process of forming the source of the above-mentioned bungee The process of forming the insulating film on the substrate to cover the underlayer, the source and the drain, and the process of forming the gate on the insulating film. 201140850 J02Ulpif, and preferably, the active layer has the same shape as the above-mentioned etch. In addition, each of the above-mentioned scissels is carried out at a temperature of β. The preferred enthalpy of each process is less than or equal to 200t base, and the above-mentioned according to (4), the concentration of &amp; The amorphous oxides of n, a and Zn constitute a side barrier layer, which is similar to the electroforming of an active layer composed of an In, Ga and Zn-crystalline oxide semiconductor, and the active layer is not damaged or occurred. Low resistance. Since it becomes a negative value and shows good-movement=, by making _ the above-mentioned composition, the source can be made with respect to the (10) aqueous solution containing yttrium, y, and yue for forming the source and the secret. The speed of the poles and the bungee and the surnames of the engraved layer are sufficiently large. Therefore, the active layer is protected by the side resist layer when the source and the drain are formed, and the active layer is not injured. Thereby, a thin film field effect transistor having excellent TFT characteristics and high reliability can be obtained. Further, the barrier layer of the present invention is similar in composition to the active layer, and can be etched using the same liquid as the active layer. Therefore, the side barrier layer can be easily processed as compared with when the film is used in the fine barrier layer. Moreover, even if the surname is provided with a barrier layer, the active layer is not damaged and the resistance is not reduced, so that it is not necessary to perform sputtering in a high concentration of oxygen environment, which can provide a small threshold shift and good reliability. Tft. The above described features and advantages of the present invention will become more apparent and obvious. 201140850 ouz-uipif [Embodiment] Hereinafter, a thin film field effect transistor of the present invention will be described based on a suitable embodiment shown in the drawings. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; (The following is only referred to as TFT1 (n, 12, gate 14, gate insulating film 16, active layer 18 functioning as a channel layer, engraved barrier layer (hereinafter referred to as Es layer) ^, immersed 2 〇 b, and The protective layer 22. The π· is active = the pole 2 applies an electric a to the gate 14 to control the function of the current between the Z, 2Ga and the drain 2% of the active layer 18; A TFT called a top contact type lower gate structure, and a gate surface 14a is formed on the surface 12a of the substrate 12, and a gate insulating film 16 is formed on the surface 12a of the board 12 to cover the germanium. The surface 16a of the 纟16 is formed with a layer 3 on the surface 18a of the active layer 18. The layer 18 is formed on the surface 16a of the insulating film 16 to form a source electrode 20a. = a surface 18a of the layer 18 and a portion 8 of the surface 3〇a of the Es layer 3〇 are rightly wound on the surface 16a of the gate insulating film 16, opposite to the source 20a:: = the source 20a forms a pair The pole is moved to cover the surface of the surface of the ES layer 30 and the surface of the surface of the ES layer 30. The surface 18a and the surface of the surface layer 3a of the ES layer 30 are formed. A protective layer 22 is formed. To cover the source 30 green LED 201140850 iWUipif 20b. The substrate 12 is not particularly limited. In the substrate i2, for example, YSZ (oxygen recording and glass inorganic materials can be used. In addition, the substrate 12 can also be used. Polyesters such as pet, polybutylene terephthalate (PBT), polyethylene naphthalate (pEN), polystyrene, polycarbonate, polyethersulfone, polyaryl An organic material such as a synthetic resin such as ester, allyl diglycol carbonate, polyimine, polycycloolefin, norbornene resin, or polydifluoroethylene/ethene. When an organic material is used for the substrate 12, it is preferably It is excellent in heat resistance, dimensional stability, solvent resistance, electrical insulating properties, workability, low air permeability, and low moisture absorption. Further, when glass is used for the substrate 12, in order to reduce eluted ions from the glass, It is preferable to use an alkali-free glass. In the case where soda-lime glass is used for the substrate 12, it is preferable to use a barrier coat which is subjected to a dioxide dream or the like. Feed glass. The substrate 12 can also use a flexible substrate. The thickness of the substrate is preferably from 50 //m to 500 //m. This is because when the thickness of the flexible substrate is less than 50/mi, it is difficult to maintain sufficient flatness of the substrate itself. When the thickness exceeds 500/m, the flexibility of the substrate itself is insufficient, and it is difficult to freely bend the substrate itself. The flexible substrate is preferably an organic plastic film having a high transmittance. For example, the organic plastic film is used. Use: Polyethylene terephthalate (PET), polybutylene phthalate (PBT), polyethylene naphthalate (PEN) and other polyesters, polystyrene, polycarbonate Ester, polyether hard, 13 201140850 36201pif polyarylate, polyimine, polycycloolefin, norbornene resin, or poly (gas trifluoroethylene) plastic film. When a plastic film or the like is used for the substrate 12, if the electrical insulating property is insufficient, an insulating layer is formed and used. In the substrate 12, a moisture-proof layer (gas barrier layer) may be provided on the surface or the reverse surface to prevent the passage of water vapor and oxygen. As the material of the moisture-proof layer (gas barrier layer), an inorganic substance such as tantalum nitride or cerium oxide is suitably used. The moisture-proof layer (gas barrier layer) can be formed, for example, by a high-frequency sputtering method or the like. Q. It should be noted that when a thermoplastic substrate is used, a hard coat layer, a lower coat layer, or the like may be provided as needed. For the gate electrode 14, for example, a metal such as A, Mo, Cr, Ta, Ti, Au, or Ag or an alloy thereof, an alloy such as Al-Nd or APC, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), or oxidation is used. A metal oxide conductive material such as indium zinc (IZ〇), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof is formed. As the gate 14, considering the reliability of the TFT characteristics, the remainder is (4) MQ, MQ alloy or C". The thickness of the gate 14 is, for example, 1 〇 nm to 1 〇〇〇 nm. The formation method of the gate 14 is not The gate electrode μ is, for example, a wet method such as a printing method or a coating method, a vacuum vapor deposition method, a subtractive bonding method, or an ion plating method (I〇n Plating methGd), or a chemical vapor deposition (Chemical Vapor Deposition, It is formed by a chemical method such as CVD) or plasma CVD. Considering the suitability of the material constituting the gate 14, an appropriate formation method is selected from the above methods. For example, a gate is formed using Mo 201140850 362Ulpif or M〇 alloy. At 14 o'clock, DC sputtering is used. When an organic conductive compound is used in the gate 14, a wet film formation method is used. Si 〇 2, SiN x , SiON, Al 2 〇 3, Ys 〇 3 are used in the gate insulating film 16. An insulator such as 〇5, or Hf〇2, or a mixed crystal compound including at least two or more of the above compounds. Further, a polymer insulator such as polyimide may be used for the gate insulating film 16. The thickness is preferably 10 nm~ 10/m. In order to reduce leakage current and improve voltage resistance, the gate insulating film 16 must have a certain thickness. However, if the film thickness of the gate insulating film 16 becomes thick, the driving voltage of the TFT1 turns is increased. When it is an inorganic insulator, the thickness of the gate insulating film 16 is more preferably 50 nm to 1 〇〇〇 nm; and when it is a polymer insulator, the thickness of the gate insulating film 16 is more preferably 0 5 〜5 芦 m. In the case where a high dielectric constant insulator such as Hf 〇 2 is used for the gate insulating film 16, the transistor can be driven at a low voltage even if the film thickness is increased. Therefore, it is particularly preferable that the gate insulating film 16 is provided. A high dielectric constant insulator is used. For the source 2 (^ and the drain 2〇b, for example, a metal such as A, Mo, Cr, Ta, Ti, Au, or Ag or an alloy thereof, A1_Nd, Apc, or the like is used. It is formed of a metal oxide conductive material such as tin oxide, zinc oxide, indium oxide, indium tin oxide (Indium Oxide) or indium zinc oxide (IZO). As the source electrode 20a and the electrodeless electrode 2b, reliability of the TFT characteristics and From the viewpoint of the etching rate ratio of the ES layer 30, it is preferable to use M〇 or Mo alloy, What is more preferable is M. It should be noted that the thickness of the source 2〇a and the drain 20b is, for example, 1〇nm~1000 leg. 15 201140850 JO/Uipif Source 20a and drain 20b are formed as follows: The film is formed by forming a photoresist pattern on the crucible by photolithography, and then etching the film to form the film. The method of forming the film constituting the source 20a and the drain 2〇b is described. The film is not particularly limited, and is formed by, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD. For example, when the source 2a and the drain 2〇b are formed using Mo or a Mo alloy, for example, a Mo film or a Mo alloy film is formed by a DC sputtering method. Then, a photoresist pattern is formed on the Mo film or the alloy film by photolithography, and the Mo film or the Mo alloy film is etched by an etching solution to form a source electrode 20a and a drain electrode 20b. As the contact liquid, a mixed acid aqueous solution containing scalylic acid, acetic acid and citric acid is used. The mixed acid aqueous solution contains, for example, 7〇% by mass to 75% by mass of citric acid, 5% by mass to 1% by mass of acetic acid, and 1% by mass to 5% by mass of nitric acid, and the remainder is water. The active layer 18 is composed of an amorphous oxide semiconductor containing In, Ga, and Zn. The Zn concentration of the active layer 18 is higher than the Zn concentration of the ES layer 30. In the active layer 18, when the total atomic weight other than oxygen is i 〇〇〇 / 0, it is preferable that the Zn concentration (Zn / (Zn + In + Ga)) is 20% to 50%. The ES layer 30 protects the active layer 18' so that the active layer 18 is not etched when the source 20a and the drain 20b are formed. The ES layer 30 is composed of an amorphous oxide containing In, Ga, and Zn. In the ES layer 30, when the total atomic weight other than oxygen is 1 〇〇〇 / 0 201140850 JDZUipif, the Zn concentration (Zn / (Zn + In + Ga)) is less than 2%. In the Es layer 30, it is further preferred that the In concentration (In / (Zn + In + Ga)) is greater than or equal to 40% and the Ga concentration (Ga / (Zn + In + Ga)) is 37% or more. As described above, the concentration of Zn atom contained in the amorphous oxide semiconductor film or the amorphous oxide film other than the Zn in the active layer 18 and the ruthenium layer 3 这里.曰 As a method of calculating the Zn concentration in the active layer 18 and the ES layer 30, T is used in the Zn concentration = [amount of Zn atoms contained in the amorphous oxide semiconductor film (amorphous oxide film) / (amorphous oxide) The amount of In atoms contained in the semiconductor film (amorphous oxide film) + the amount of Ga atoms contained in the amorphous oxide semiconductor film (amorphous oxide film) + the amorphous oxide semiconductor film (amorphous oxide film) The amount of Zn atoms contained)). The In concentration and the Ga concentration in the active layer 18 and the ES layer 30 are also the same as the definition of the Zn concentration, and the In concentration and the Ga concentration are also calculated in the same manner as the Zn concentration. In addition, the amount of Zn atoms, the amount of ln atoms, and the amount of Ga atoms in the amorphous oxide semiconductor film (amorphous oxide film) are values obtained by XRF (fluorescence X-ray analysis). The Zn concentration, the In concentration, and the Ga concentration in the ES layer 30 may be the concentration in the entire ruthenium layer 30, or may be the surface 3 〇 a portion of the ES layer 30 in contact with the source 20a and the drain 20b, or the concentration above. . It is to be noted that the Zn concentration of the ES layer 30 is preferably 5% or more and less than 20%. This is because when the Zn concentration is less than 5%, the amorphous nature of the oxide semiconductor film is deteriorated, and crystallization tends to occur. 17 201140850 302Ulpif The In concentration of the ES layer 30 is preferably 40% to 58%, and the Ga concentration of the ES layer 30 is preferably 37% to 55%. When the above mixed acid aqueous solution is used as an etching liquid to form the source 20a and the nonpolar electrode 20b made of Mo or a Mo alloy, the ES layer 30 is also in contact with the surname. At this time, if the ES layer 30 is not resistant to the etching liquid, the ES layer 30 is also etched. Therefore, in the present invention, the etching rate of the ES layer 3 〇 with respect to the aqueous mixed acid solution is lowered, so that the ES layer 3 〇 is not etched. That is, the etch rate ratio (selection ratio) of the ruthenium layer 30' to Mo constituting the source electrode 2a and the drain electrode 2b is sufficiently high. In the present invention, if the Zn concentration of the ES layer 30 is less than 20%, as shown in Fig. 2, the etching rate with molybdenum is more than 1 Å with respect to the aqueous mixed acid solution containing phosphoric acid, acetic acid and nitric acid. Therefore, when the source electrode 2a and the drain electrode 20b are formed, the etching of the active layer 18 is suppressed. If the Ga concentration of the ES layer 30 is 37% or more, as shown in FIG. 3, it is relative to containing Wei, acetic acid and The mixed acid aqueous solution has a button ratio of more than 10 to the key. Therefore, when the source electrode 20a and the drain electrode 2b are formed, the etching of the layer 30 is suppressed. Even if the ip concentration of the ES layer 30 is 4% or more, as shown in Fig. 3, the ratio of the contact ratio with the key in the mixed acid solution containing impurities, acetic acid and helium exceeds 1 〇. Therefore, when the source 2a and the gate 2b are formed, the etching of the layer 30 is suppressed. In the present invention, the composition of the ES layer 30 is adjusted so that the Zn concentration m is 20,000 Å so as to be sufficiently high, for example, more than 10, with respect to the mixed acid aqueous solution to the source 20a and the etch rate. With this, in the formation of 18 8 201140850

When Jo/υιριί source 20a and drain 20b, the etching of the ES layer 30 can be suppressed, and the function as an etching stopper can be sufficiently exhibited. It is to be noted that, with respect to the composition of the ES layer 30, by making the concentration of ζι 1 less than 20%, and making the concentration of ηη4% or more and the concentration of Ga of 37% or more, the aqueous solution with respect to the mixed acid can be further sufficiently improved. The source engraving rate ratio of the source 20a and the poleless 20b. Thereby, the etching of the ES layer 30 can be more surely suppressed. The protective layer 22 is formed to protect the active layer 18, the ES layer 30, the source 20a, and the drain 20b from deterioration by the atmosphere, and is insulated from the electronic device fabricated on the transistor. The protective layer 22 of the present embodiment is formed, for example, by heat-hardening a photosensitive acrylic resin under a nitrogen atmosphere. In addition to the above-mentioned photosensitive acrylic resin, the protective layer 22 may be, for example, MgO, SiO, SiO 2 , Al 2 〇 3, GeO, NiO, CaO, BaO, Fe 2 〇 3, γ 2 〇 3, 〇 3 or Ti 〇 2 Metal oxides; metal nitrides such as SiNxOy; metal fluorides such as MgI?2, UF, Α1??3 or CaF2, polyethylene, polypropylene, decyl acrylate, polyimine, polyurea , a copolymer of polytetrafluoroethylene, polygas trifluoroethylene, polydifluoroethylene fluoride, chlorofluoroethylene and monofluoroethylene, copolymerization of a monomer mixture comprising tetrafluoroethylene and at least one comonomer The obtained copolymer, a fluorinated copolymer having a cyclic structure in a copolymerization main chain, a water-absorbent substance having a water absorption of 1% or more, a moisture-proof substance having a water absorption of 0.1% or less, or the like. The method of forming the ruthenium layer 22 is not particularly limited. The protective layer 22 can be, for example, a vacuum distillation method, a sputtering clock method, a reactive sputtering method, an MBE (201140850 JOXVipif sub-line extension)*, a cluster ion beam method, an ion surface method (still frequency-excited ion plating method), Plasma CVD method, laser / ^ σ / heat = method, gas source CVD method, coating method, printing method, or transfer ^ Next, the manufacturing method of the present embodiment will be described with reference to Figs. 4a to 4c. First, as the substrate 12, for example, a glass substrate is prepared. Next, a molybdenum film (not shown) having a thickness of 4 Å is formed on the surface i2a of the substrate 12 by DC sputtering. Next, a photoresist film (not shown) is formed on the molybdenum film to form a photoresist pattern. In the light, for example, a mixed acid solution containing 70% by mass to 75% by mass of phosphoric acid, 5% by mass to 1% by mass of acetic acid, i% by mass to 5% by mass of acid, and the balance of water is used. To etch molybdenum film. Strip the photoresist film. Thereby, as shown in Fig. 4a, a gate electrode 14 made of molybdenum is formed on the surface ΐ2'&amp; of the substrate 12. Next, a Sl 〇 2 film (not shown) as a gate insulating film 16 is formed on the entire surface of the surface 12a of the substrate 12 by RF sputtering, for example, to a thickness of 200 rnn to cover the gate electrode 14. Next, the UGZ ruthenium film as the active layer 18 is formed on the surface of the Si 〇 2 film by a DC sputtering method, for example, at a thickness of 3 〇 nm (not shown in the following 'Using the DC sputtering method, the pressure is 〇 Under the condition of .37 Pa, a second IGZO film (not shown) as the Es layer 30 is formed on the surface of the first IGZO film at a thickness of, for example, 2 Å. Thus, Si 2 film is continuously formed on the substrate 12 in this order. The first IGZO film and the second IGZO film. 201140850 iO^UIpif Next, a photoresist film (not shown) is formed on the second IGZO film. Then, a photoresist pattern is formed by photolithography. Thereafter, for example, 5% oxalic acid is used. The second IGZO film and the i-th IGZ film are engraved with water, and then the photoresist film is peeled off, thereby forming the active layer 18. Next, a photoresist film (not shown) is formed on the second IGZO film. The photoresist pattern is formed by a photolithography method. Thereafter, for example, 5% of the sputum water is used, and after the second IGZO film is implanted, the photoresist film is peeled off. Thereby, the ES layer 30 is formed. 2 film / iIGZ 〇 film / 2IGZ 〇 film formed on the photoresist film (not shown) 'Photolithography to form a photoresist Then, for example, buffered hydrofluoric acid is used to etch the Si〇2 film. Thereafter, the photoresist film is peeled off. Thus, as shown in Fig. 4b, a pattern of the ES layer 3, the active layer 18, and the gate insulating film 16 is formed. It is to be noted that the first IGZO film constituting the active layer 18 contains

In, Ga, and Zn' and the Zn concentration is 20% or more, which is higher than the Zn concentration of the ES layer 30. The second IGZO film constituting the ES layer 30 contains In, Ga, and Zn, and the Zn concentration is less than 20%. Preferably, the In concentration is 4% by mass or more, and the concentration is 37% or more. Further, when the first IGZO film and the second IGZO film are formed by the DC saving method, the dry materials having the composition adjusted in advance are used to achieve the respective compositions of the second film and the second film. 〇 Next, using the DC sputtering method, under the condition of a pressure of 〇·37 pa, on the surface of the gate insulating film 16! 6a is formed as a source with a thickness of 1〇〇 nm 21 201140850 ίοζυιριί

The layer 30 and the active layer 18, for example, _ (not shown) covering the ES pole 2〇a and the secret 20b. A resist film (not shown) is formed on the molybdenum film by 1', and a photoresist pattern is formed by photolithography using the gate electrode. After that, for example, use contains. 75 mass% of citric acid, 5% by mass to 10% by mass of acetic acid, ～5 f4% of nitric acid' and the remaining part of mixed acid water composed of water: liquid ^ bribe. Need. Lang's is that _ is better at the time of contact with the mixed acid water _ liquid temperature small material is carried out under 35 ,, and, better, at, the temperature is hungry ~ 25. (: after the side is performed, the photoresist is peeled off. Thereby, as shown in FIG. 4c, the source 20a formed to cover the surface 30a of the ruthenium layer 30, the core and a part of the surface 18a of the active layer 18, and The drain 20b. Next, for example, a photosensitive acrylic resin is applied to cover the sand layer 30, the source 20a, and the drain 20b. Then, a propylene resin film is formed by photolithography. The curing conditions of the acrylic resin in the case of ruthenium are, for example, a temperature of 180 〇 c, 3 〇 minutes. Next, in a nitrogen atmosphere, at a temperature of rc (the temperature of rc, post-annealing is performed for hours; as described above, it can be formed In the TFT 10 of the present embodiment, even if the Es layer is provided on the surface 18a of the active layer 18 to protect the active layer 18 from being etched, since the composition of the layer 30 and the active layer 18 are similar, the active layer is 18 is not damaged, and low resistance does not occur. Therefore, the _ of TFT1G does not become a negative value, but shows a good TFT operation. 22 8 201140850 302Ulpif In addition, the source 2 with respect to the etching liquid is made蚀刻a and bungee 2% and es layer 30 etch rate The rate ratio is as high as 1 〇 or more, which improves the etching resistance of the ruthenium layer. Thus, when etching the source 20a and the drain 20b, the etching of the underlying ES layer 30 is reduced, and the activity of the underlayer is not caused. The layer 18 causes any damage. Therefore, it is possible to uniformly form the TFT 1 which exhibits good TFT characteristics and high reliability in the plane. Further, in the manufacturing process of the TFT 10, the ES layer 3 can be utilized with the active layer. 18 etching is performed on the same etching liquid, and the ES layer 3 can be easily processed compared to when an Si 2 film is used as an etching stopper. Further, even if the ES layer 30 is provided, the active layer 18 is not damaged. Since the low resistance does not occur, it is not necessary to form the ES layer by sputtering in a high-concentration oxygen atmosphere, and it is possible to provide a τρΓ having a small threshold shift and good reliability. Further, in the manufacturing process of the TFT 10, the photoresist film is provided. The formation of the photoresist pattern, the formation of various films, and the formation of the protective layer 22 are all performed at a temperature of 200 ° C or less. Thus, since each process is performed at a temperature of 2 小于 or less, In the substrate 12 For example, PET, PEN, or the like having low heat resistance is used. Since these PET and PEN have flexibility, a flexible transistor can be obtained. Next, a second embodiment will be described. A schematic cross-sectional view of the thin film field effect transistor according to the second embodiment of the present invention. In the present embodiment, the same configuration as the TFT 10 of the first embodiment shown in FIG. 1 has the same configuration. The detailed description of the symbols is omitted. 23 201140850 The TFT 10a shown in FIG. 5 is different from the TFT 10 shown in FIG. 1 in that the ES layer 32 has the same shape as the active layer 18, and other configurations and figures are shown. The configuration of the TFT 10 shown in Fig. 1 is the same. It is to be noted that the Es layer 32 is the same as the ES layer 3A of the first embodiment except for the shape, and therefore detailed description thereof will be omitted. Next, a method of manufacturing the TFT 10a of the present embodiment will be described. Fig. 6a to Fig. 6c are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to a second embodiment of the present invention in a process sequence. In the method of manufacturing the TFT 10a, the same processes as those of the TFT1A of the first embodiment shown in Figs. 4a to 4c will be omitted. In the manufacturing method of the TFT 10a of the present embodiment, the manufacturing process of the TFT 1G of the first embodiment is the same as the manufacturing process of the TFT 1G of the first embodiment, except that the manufacturing process of the Es layer &amp; Therefore, the detailed description of the drawings and the drawings other than the forming process of the ES layer 32 will be omitted. In the same operation as in the first embodiment, the TFT 10a of the present embodiment has the gate electrode 14 formed on the surface 12a. In the manufacturing method, first, as shown in Fig. 6a, a photoresist film (not shown) is formed on the ruthenium film of 糸Ti^2lGZ after the absence of the substrate 12, 201140850, 36201pif. A photoresist pattern is formed, and then the second bottle of the ruthenium film 32 and the active layer 18 are engraved. The photoresist film is peeled off. Thereby, a photoresist film (not shown) is formed on the galvanized tZ2IGZQ film, and it forms a photoresist pattern. Then, _ _ membrane. After that, two photoresist films. Thereby, as shown in Fig. 6b, the pattern of the layer of the yeah layer 32 and the active layer 18 is formed on the surface 1 of the interlayer insulating film 16. At this time, the layer formed on the surface 18a of the living 18 has the same shape as the active layer ι8. In addition, the description of the gate insulating film 16, the ES layer 32, and the active layer 18 can be performed in the same manner as in the first embodiment. Further, the second IGZO film constituting the ES layer 32 is the same as the second IGZ0 ray composition constituting the ES layer 3G of the first embodiment. In the same manner as in the first embodiment, when the i-th IGZ0 film and the second IGZG film are formed by the DC sputtering method, the material which has been previously composed of the scent is formed. Next, the same operation as in the first embodiment is performed, and a molybdenum film (not shown) as a source 20a and a drain 20b is formed on the surface 16&amp; of the gate insulating film 16 to cover the ES layer 32 and the active layer 18. . Then, a photoresist pattern is formed by photolithography. Thereafter, the molybdenum film was etched using the same mixed acid aqueous solution as the components of the first embodiment. Thereby, the source 20a and the drain 20b which are formed so as to cover a part of the surface 32a of the ES layer 32 are obtained as shown in Fig. 6c. Next, the same operation as in the first embodiment is performed to form a protective layer 22 covering the 25 201140850 JWUlplf ES layer 32, the source 20a, and the drain 20b. As described above, the TFT 10a shown in Fig. 5 can be formed. It should be noted that although the £3 layer 32 and the active layer W are uniformly formed at one time, it is not limited thereto. The photoresist pattern may be formed by photolithography, and then etched to form the Es layer 32 and the active layer 18, respectively. In the present embodiment, even if the Es layer 32 and the active layer 18 are formed in the same shape, the composition of the ES layer 32 and the active layer 18 are similar, and the ruthenium layer 32 also functions as an active layer to function as a TFT. By making the ES layer 32 the same as the shape of the active layer 18, the ES layer 32 and the active layer 18 can be formed using a photoresist pattern formed by the same mask. By this, the number of masks required to form a light-receiving case can be reduced, the cost can be reduced, and the manufacturing process can be simplified. Thereby, it is also possible to improve the production. In addition to this, in the present embodiment, the same effects as in the above formula 0 and the manufacturing method thereof can be obtained. Therefore, the threshold of the Tmoa of this implementation does not become a negative value, but shows a good top. Further, the TFT 10a which exhibits good TFT phase characteristics and high reliability can be formed uniformly in the plane. Further, the sand layer can be easily formed as compared with the prior art, and the processing can be easily performed. : Outer In the manufacturing process of the TFT 10a, the formation of the photoresist film, the formation of the missing pattern, the formation of various films, and the formation of the protective layer 22 are also long = less significant than the material 2 thief. Thus, since each process is performed at a temperature less than _ coffee (3), it is possible to produce a substrate 12 having low heat resistance. Thereby, a transistor having a manageability can be obtained. Next, a third embodiment will be described. Fig. 7 is a schematic cross-sectional view showing a thin film field effect transistor according to a third embodiment of the present invention. In the present embodiment, the same components as those of the TFT 10 of the first embodiment shown in Fig. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. The TFT 10b shown in Fig. 7 is usually a TFT called a top contact type upper gate structure. Compared with the TFT1〇 shown in FIG. 1, the TFn〇b is different in that the arrangement position of the gate electrode 14 and the position of the Es layer 3 and the active layer 18 and the source 20a and the drain 20b are reversed. The other configuration is the same as that of the TFT 10 shown in Fig. 1 . The TFT 10b shown in Fig. 7 has an active layer 18 formed on the surface 12a of the substrate 12. A layer of germanium 3 is formed on the surface 18a of the active layer is. A source electrode 2a is formed on the surface 12a of the substrate 12 to cover a surface 18a of the active layer 18 and a portion of the surface 30a of the ES layer 30. Further, on the surface i2a of the substrate 12, a drain electrode 2b' forming a pair with the source electrode 2a is formed opposite to the source electrode 20a to cover the surface 1 of the active layer 18 and the surface of the es layer 30. Part of a. An insulating film 24 is formed on the substrate 12 to cover the ES layer 30 and the active layer 18, and the source 2a and the drain 20b. A gate electrode 14 is formed on the surface 24a of the insulating film 24. A protective layer 22 is formed on the surface 24a of the insulating film 24 to cover the gate 14. It should be noted that the 'insulator 24' is for insulating the ES layer 30 and the active layer 18 and the source 2a and the drain 2〇b from the gate 14. Since the insulating film 27 201140850 is the same as the gate insulating layer 16 of the &amp; TFT 10 shown in Fig. 1, the detailed description thereof will be omitted. Next, a method of manufacturing the TFT 10b of the present embodiment will be described. Fig. 8a to Fig. 8d are schematic cross-sectional views showing a method of manufacturing the thin film field effect transistor according to the third embodiment of the present invention in a process sequence. In the method of manufacturing the TFT 10b, the same processes as those of the TFT1A of the i-th embodiment shown in Figs. 4a to 4c will be omitted. In the method of manufacturing the TFT 10b of the present embodiment, first, for example, a glass substrate is prepared as the substrate 12. Next, a first IGZ ruthenium film (not shown) as an active layer μ is formed on the surface i2a of the substrate 12 by a DC sputtering method at a thickness of, for example, 30 nm. Next, a second IGZO film (not shown) as a layer of 30 Å 11111 is formed on the surface of the first IGZO film by a DC sputtering method under the conditions of a pressure of 〇 37 Pa. Thus, the i-th IGZ〇 film and the second edge 20 film are continuously formed. Next, a photoresist film (not shown) was formed on the second IGZO film. Then, a photoresist pattern is formed by photolithography, and then the second IGZO film and the second IGZ film are etched using, for example, 5% of oxalic acid water. Thereafter, the photoresist film was peeled off. A photoresist film (not shown) was formed again on the second IGZO film, and then a photoresist pattern was formed by photolithography. Then, for example, oxalic acid 8 201140850 ^ozuipif water is used to etch only the 2nd IGZO film. After that, the photoresist is peeled off. Thereby, as shown in Fig. 8a, the active layer 18 is formed on the surface 12a of the substrate 12, and the ES layer 30 is formed on the surface 18a thereof. Next, 'DC sputtering method' is used to form, for example, a molybdenum film as a source 2 plus a gate 2 (^> on a surface 12a of the sheet 12 at a thickness of 100 nm under the condition of 37.37 Pa. The figure is shown to cover the £8 layer of the erbium layer 18. Next, a photoresist film (not shown) is formed on the key film, and a photoresist pattern is formed by photolithography. The aqueous solution of the mixed acid having the same composition is used to roll the film. After the last name, the photoresist film is peeled off. Thereby, as shown in FIG. 8b, the surface 3〇&amp; and the surface i8a of the active layer 18 are covered to cover the surface of the ES layer. The source 2 〇 &amp; and the drain 2 are formed by a part of the method. Next, as shown in FIG. 8c, 'the thickness of 2 〇〇 11111 is formed as the insulating film *24 by the rf money ore method. 2 film (not shown), cover active layer 18, source 20a and drain 2〇b. A photoresist film (not shown) is formed on the Si〇2 film, and then a photoresist is formed by photolithography. Then, for example, a buffered hydrofluoric acid is used to form a film 24, and then, on the surface 2 of the insulating film 24, by DC sputtering. For example, a film (not shown) as a thickness of 40 nm is formed. Next, a photoresist film (not shown) is formed on the molybdenum film, and then a photoresist pattern is formed by photolithography. 'Use the same mixed acid aqueous solution side pin as the composition of the i-th embodiment. Thereafter, the lion's ray is used. Thus, as shown in Fig. 8d, a pin made of a pin is formed on the surface 24a of the JUZUipif insulating film 24 of 29 201140850. 14 β dilute: Come: the surface of the t-edge film 24 is applied, for example, by coating photosensitive C 1 = amperate pole 14 , and then by photolithography to form the acrylic acid tree film ® case. The curing condition of the acid resin at the time of formation is, for example, a temperature of 180 ° C for 30 minutes. Next, a post-annealing is performed for 1 hour under a nitrogen atmosphere at a temperature of 180 ° C. As described above, FIG. 7 can be formed. In the present embodiment, the same effects as those of the TFT 10 of the first embodiment and the method of manufacturing the same can be obtained. Therefore, the threshold value of the TFT 10b of the present embodiment does not become a negative value but is displayed. Out of good Kenting action, 'can be in-plane The TFT 10b which exhibits excellent TFT characteristics and high reliability is formed uniformly. Further, the ES layer 32 can be easily formed as compared with the related art, and the processing can be easily performed. In the TFT1〇b(4) of the present embodiment, In the process, the formation of the photoresist film, the formation of the photoresist pattern, the formation of various films, and the formation of the protective layer 22 are all performed at a temperature of 2 or less (ΚΓς:τ. Thus, since it is performed at a temperature of 200 C or less, etc. Since each process is used, it is possible to use a substrate 12 having a low heat-generating property such as ρΕΤ or ugly, whereby a flexible tft can be obtained. Next, a fourth embodiment will be described. Fig. 9 is a schematic cross-sectional view showing a thin film field effect transistor according to a fourth embodiment of the present invention. In the present embodiment, the same constituents as the TFT IGb of the third embodiment shown in Fig. 7 are provided with a phase (10) symbol, and the description of the 30 8 201140850 like Ulpif is omitted. The TFT 10C shown in Fig. 9 is different from the TFT 10b shown in Fig. 7 in that the ES layer 32 has the same shape as the active layer 18, and the other configuration is the same as that of the TFT 10b shown in Fig. 7. It should be noted that, as described above, the ES layer 32 has the same composition as the ES layer 30 of the first embodiment. Therefore, the detailed description is omitted. Next, a method of manufacturing the TFT 10c of the present embodiment will be described. . 10a to 10d are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to a fourth embodiment of the present invention in a process sequence. In the manufacturing method of the TFT 10c, the same process as the manufacturing method of the claw 1% of the third embodiment shown in Fig. 8d will be omitted. In the method of manufacturing the TFT 1 〇 c of the present embodiment, the es layer U and the forming process are different from the manufacturing method of the TFT 1Gb of the third embodiment in the same manner as the manufacturing method of the TFT 1Gb of the third embodiment. The process of FIG. 1B except for the formation process of the ES layer η is omitted. In the manufacturing method of the first 〇d and the first TFT1 〇e, first, the tangent point Γί is performed in the same manner 'continuously on the surface 12a of the substrate 12=1 as the ith film a = r of the active layer 18. The surface of the film is formed as -(4). "Next, a photoresist film is formed on the second IGZ0 film (not shown), 20114085α. Then, a photoresist pattern _ oxalic acid water is used to form the 21st coffee film and 5%. The u 夂 夂 1 1 IGZO film. Thereafter, the doped iridium film, thereby forming the ES layer 32 and the active layer 18 as shown in FIG.

picture of. At this time, the ruthenium layer W formed on the surface of the active layer 18 is formed in the same shape as the active layer 18. The i-th ES layer 32 (four) 2 IGZ tantalum film has the same composition as the second IGZ tantalum film constituting the ES layer 30 of the first embodiment. f. In the third embodiment, when the first service film and the second IGZQ film are formed by the Dc-salt method, a dry material having a composition adjusted in advance is used. Next, in the same operation as in the third embodiment, a molybdenum film (not shown) as a source electrode 2a and a drain electrode 2% is formed on the surface 12a of the substrate 以 to cover the ES layer 32 and the active layer 18 . Then, after the photoresist pattern is formed by photolithography, the same aqueous acid-soluble silk film as the component of the i-th embodiment is used as in the third embodiment. Thereby, as shown by l 〇 b, the source 20a and the drain 2 〇b which are formed to cover a part of the surface 仏 of the ES layer 32 are obtained. Next, the same operation as in the third embodiment is performed, and as shown in Fig. 10c, an insulating film 24 covering the ES 2, the source 2a, and the step 2b is formed. Next, the same operation as in the third embodiment is performed. As shown in FIG. 1A, the gate electrode 14 made of molybdenum is formed on the surface 2 of the insulating film 24, and then formed on the surface 24a of the insulating film 24. The layer 22 is protected to cover the gate 14. Thereafter, a post-annealing was performed for 1 hour under a nitrogen atmosphere at a temperature of 18 Torr to form a TFT 10c. 32 201140850 36201pif It should be noted that although the Es layer 32 18 is uniformly formed at one time, it is also rare to use I to form a photoresist and an active layer by photolithography, and then etched to form the ES layer 32 and the active layer ^8 pattern, respectively. In the present embodiment, even if the ES layer 32 is formed in the same shape as the material a, the ES layer 32 and the active layer 18 have a composition similar to that of the active layer 18, and operate as a TFT. Layer 32 Further, the formation layer 18 is formed by using the photoresist pattern formed by the same mask by using the shape of the ES layer 32 and the active layer 18. Thereby, the number of covers required to form the sister pattern can be reduced, and the amount can be reduced. (4) IX can be simplified to improve the production efficiency. In addition to this, in the present embodiment, the TFTs of the i-th embodiment and the system thereof can be obtained in the third embodiment. Therefore, the threshold value of TF· does not become a negative value, but it can be easily formed into a ruthenium layer process as compared with the prior art. Further, in the manufacturing process of the TFT 10C, the formation of the photoresist film, the formation of various light films, and the formation of the protective layer 22 are also performed at a degree of &gt; -搂, ^ ^ 200t temperature for each process, ^ foot sample, because it is less than or equal to secret (four) two L, so you can use PET, ugly, etc. 12 Thereby, a TFT having flexibility can be obtained. This month is basically as described above. The thin film field effect electric power 33 201140850 JO/Ulplf crystal of the present invention and the method for producing the same have been described in detail above, but the present invention is not limited to the above embodiment, and various modifications can of course be made without departing from the gist of the invention. Or change. [Example 1] Hereinafter, examples of the thin film field effect transistor of the present invention will be specifically described. In the present Example, the TFTs shown in the following Example 1, Example 2, and Comparative Example 1 to Comparative Example 3 were produced, and the TFTs of Example 1, Example 2, and Comparative Example 1 to Comparative Example 3 were produced. Evaluation. In the TFTs of the first embodiment, the second embodiment, and the comparative examples 1 to 3, the TFT 10 having the configuration shown in FIG. 1 was used. Each of the TFTs of Example 1, Example 2, and Comparative Example 1 to Comparative Example 3 was basically produced by the above-described manufacturing method shown in Figs. 4a to 4c. In each of the TFTs of Example 1, Example 2, Comparative Example 1, and Comparative Example 2, the gate electrode 14 was formed by forming a molybdenum film having a thickness of 40 nm by DC sputtering, and then photolithographically coating the molybdenum film. A resist pattern is formed thereon, and a mixed acid aqueous solution containing 73% by mass of phosphoric acid, 7% by mass of acetic acid, 3% by mass of nitric acid, and the remainder of water is used (the liquid temperature is 35. The etching is performed to form.) Next, a Si 2 film having a thickness of 200 nm as a gate insulating film 16 was formed by RF sputtering. Next, an active layer was formed on the surface of the Si 2 film by a DC sputtering method at a thickness of 30 nm. a first IGZO film having the following composition of 18: The second layer of the following composition as the ES layer 3〇 is formed on the surface of the j-th IGZ yttrium film by a DC sputtering method at a thickness of 30 nm; 20114850 36201pif IGZO Then, a photoresist pattern is formed on the second IGZ ruthenium film by photolithography, and then the second IGZ ruthenium film and the first IGZO film are formed by using 5% oxalic acid water, and the active layer 18 is formed using Zn concentration ( Zn/In+Ga+Zn) is 26 9%,

The first IGZO film having a Ga concentration (Ga/In+Ga+Zn) of 34.6% and an In concentration (In/In+Ga+Zn) of 38.5%. It should be noted that the concentration analysis of the i-th IGZ〇 film was carried out by XRF analysis as described above. The ES layer 30 is formed by forming a photoresist pattern on the second IGZO film by photolithography after the active layer 18 is formed. Then, using only 5% of oxalic acid water to etch only the second IGZO film, the ES layer 3 can be formed. The gate insulating film 16 is formed by forming a pattern on the other film 2 / ith IGZO film / 3⁄4 2 IGZO film by photolithography, and etching the si 〇 2 film by using buffer gas acid to form a gate insulating film. 16. The source electrode 20a and the drain electrode 20b were formed by forming a ruthenium film at a thickness of 1 〇〇 nm under a condition of a pressure of 0.37 Pa by a DC sputtering method. A photoresist pattern is formed on the molybdenum film by photolithography. Then, the molybdenum film is etched by using an aqueous mixed acid solution containing a mass% of acid, 7% by mass of acetic acid, 3% by mass, and the balance of water (liquid temperature: 25 〇c) as an etching solution. form. The protective layer 22 is coated with a photosensitive acrylic resin (pC4〇5G (manufactured by JSR Co., Ltd.)) to form an acrylic resin film by photolithography after covering the active layer 18, the source 2a and the electrode 20b'. pattern. The curing conditions of the acrylic resin at the time of pattern formation were post-annealing at a temperature of 180 ° C under a nitrogen atmosphere at a temperature of 18 ° C for 3 〇 minutes, and 35 201140850 JOZUlplf to form the TFT 10 . In Example 1, the ES layer used a Zn concentration (Zn/In+Ga+Zn) of 14.6%, a Ga concentration (Ga/In+Ga+Zn) of 41.6%, and an In concentration of 〇/111+0&amp;+211). It is 43.8% of the 21020 film. Incidentally, the concentration analysis of the second IGZO film was carried out by xrf analysis as described above. In the first embodiment, the ES layer and the constituent source are formed by using the above etching liquid (73 mass% phosphoric acid, 7 mass% acetic acid, and 3% by mass aqueous mixed acid solution of nitric acid (liquid temperature: 25 ° C)). The etch rate of the molybdenum of the bungee is 1:13.8 (IGZO:Mo). Example 1 corresponds to the symbol A shown in Fig. 2. In the second embodiment, the ES layer has a Zn concentration (Zn/In+Ga+Zn) of 19.2% and a Ga concentration (Ga/In+Ga+Zn) of 38.8. The %, In concentration (In/In+Ga+Zn) was 42.0% of the second IGZO film. In the second embodiment, the ES layer and the constituent source and the immersion electrode are formed by using the above etching liquid (73 mass% phosphoric acid, 7 masses of acetic acid, and 3% by mass of a mixed acid solution of nitric acid (liquid temperature: 25 C)). The molybdenum meal rate ratio (IGZO:Mo) is 1:10.6. Embodiment 2 corresponds to the symbol B shown in Fig. 2 . In Comparative Example 1, a Si〇2 film having a thickness of 20 nm was used as the Es layer. In Comparative Example 1, the same as Example 1 except that the configuration and the formation method of the ES layer were different. In Comparative Example 1, an Es layer was formed as follows. In Comparative Example 1, after the first IGZ0 film was formed, a pattern of the active layer 18 was formed. Thereafter, an Si 2 film having a thickness of 20 nm was formed on the surface 16 &amp; 5 201140850 JOZUipif of the gate insulating film 16 by RF sputtering to cover the active layer 18. Next, a photoresist pattern was formed on the Si 2 film, and the SiO 2 film was etched using buffered hydrofluoric acid to form an ES layer. In Comparative Example 2, the ES layer used Zn concentration (Zn/In+Ga+Zn) of 34.7%, Ga concentration (Ga/In+Ga+Zn) of 30_3%, and In concentration (In/In+Ga+Zn). It is 35.0% of the 2nd IGZO film. In Comparative Example 2, the ES layer and the constituent source were formed by the etching liquid (73 mass% phosphoric acid, 7 mass% acetic acid, and 3% by mass aqueous mixed acid solution of nitric acid (liquid temperature: 25 ° C)). The etch rate ratio (IGZO:Mo) of the molybdenum of the bungee is 1:3.1. Comparative Example 2 corresponds to the symbol C shown in Fig. 2 . In Comparative Example 3, the ES layer used a Zn concentration (Zn/In+Ga+Zn) of 25.1%, a Ga concentration (Ga/In+Ga+Zn) of 36.5%, and an In concentration (In/In+Ga+Zn). It is 35% of the 2nd IGZO film. In Comparative Example 3, the ES layer and the constituent source were formed by the etching liquid (73 mass% phosphoric acid, 7 mass% acetic acid, and 3% by mass aqueous mixed acid solution of nitric acid (liquid temperature: 25 ° C)). The etch rate ratio (IGZO:Mo) of the molybdenum of the bungee is 1:9.0. Comparative Example 3 corresponds to the symbol D shown in Fig. 2 . The mobility of each of the electrochemical crystals of Example 2 and Comparative Example 1 to Comparative Example 3 was measured. As a result, the mobility of the crystals of Example 1 and Example 2 was 10 〇 cm 2 /Vs or more, and the uniformity of TFT characteristics was good. On the other hand, in Comparative Example 1, the active layer of the underlayer was also etched due to the etching at the time of forming the ES layer, and the contact with the source and the immersion pole was insufficient, and the current of the JOZUipif current was deteriorated even if it was reliability. The test 'has also obtained poor results compared to Example i and Example 2. Further, in Comparative Example 2, the ES layer did not function. The etching of the source and the drain disappeared, and the active layer disappeared, and the TFT could not be formed, and the TFT operation was not performed. In Comparative Example 3, the 'ES layer function was insufficient', although the TFT operation was performed, but the in-plane uniformity of the TFT characteristics was poor. [Example 2] In the present Example, the TFTs shown in the following Examples 3 and 4 were produced, and the TFTs of Examples 3 and 4 were evaluated. It is to be noted that the TFTs of the third embodiment and the comparative example 4 use the TFT 10a formed as shown in Fig. 5 . In the present embodiment, the ES layer and the active layer have the same shape as the first embodiment, and the same as the first embodiment, the detailed description thereof will be omitted. In Example 3, the ES layer and the active layer formed the same shape. This embodiment 3 is the same as the first embodiment of the first embodiment except that the ES layer and the active layer form the same shape. In Comparative Example 4, the 'ES layer and the active layer formed the same shape. This Comparative Example 4 is the same as Comparative Example 1 of the first embodiment except that the ES layer and the active layer have the same shape. The mobility of each of the TFTs of Example 3 and Comparative Example 4 was measured. As a result, the mobility of the TFT of Example 3 was 10 〇cm 2 /Vs or more, and the uniformity of TFT characteristics was good. Comparative Example 4 did not show TFT operation. It should be noted that since the embodiment 3 can use the same mask shape 38 5 201140850 JOZUipif into the ES layer and the active layer, the number of masks can be reduced, and the cost can be reduced. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make a few changes and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a thin film field effect transistor according to a first embodiment of the present invention. Fig. 2 is a view showing the use of 73% by mass of scaly acid and 7 mass% in the #刻液. Acetic acid, 3 mass% nitric acid, and a temperature of 25. A plot of the ratio of the IGZO film relative to the molybdenum in the case of a mixed acid water solution. 3 is a view showing that 73% by mass of phosphoric acid, 7% by mass of acetic acid, 3% by mass of nitric acid, and a temperature of 25 are used in the etching solution. A plot of the ratio of the lGz ruthenium film relative to molybdenum at the In concentration and the Ga concentration in the case of a mixed acid water solution. 4a to 4c are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to an i-th embodiment of the present invention in a process sequence. Fig. 5 is a schematic cross-sectional view showing a thin film field effect transistor according to a second embodiment of the present invention. Fig. 6a to Fig. 6c are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to a second embodiment of the present invention in a process sequence. Fig. 7 is a schematic cross-sectional view showing a film field effect 39 201140850 transistor according to a third embodiment of the present invention. 8a to 8d are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to a third embodiment of the present invention in a process sequence. Fig. 9 is a schematic cross-sectional view showing a thin film field effect transistor according to a fourth embodiment of the present invention. 10a to 10d are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to a fourth embodiment of the present invention in a process sequence. [Description of main component symbols] 10, 10a, 10b, 10c: Thin film field effect transistor (TFT) 12: Substrate 12a, 16a, 18a, 24a, 30a, 32a: Surface 14: Gate 16: Gate insulating film 18: Active Layer 20a: source 20b: drain 22: protective layer 24: insulating film 30, 32: etching barrier layer (ES layer)

Claims (1)

201140850f VII. Patent application scope: 1. A thin film field effect transistor, which has at least a problem layer, an insulating film, an active layer, a paste layer, a source and a secret on the substrate, and an upper axis of the active layer : the side layer, the source and the secret are formed on the resistive layer, and the thin film field effect is characterized in that: the etching barrier layer comprises a Zn concentration of less than 20%. The In and Zn are formed of an amorphous oxide; the active layer is composed of an amorphous oxide semiconductor containing In, Ga, and Zn and the Zn concentration is higher than the Zn concentration of the etching stopper. 2. The thin film field effect device of claim i, wherein the etching barrier layer has an In concentration of 4% or more and a Ga concentration of 37% or more. 3. The thin film field effect transistor of claim i, wherein the source and the gate are composed of a tantalum or a key alloy. 4. The thin film field effect transistor of claim 1, wherein the active layer and the etch stop layer have the same shape. 5. The thin film field effect transistor as described in the application of the patent &lt;RTI ID=0.0&gt;&gt;&gt;&gt; 6. The thin film field effect transistor of any one of clauses 1-4, wherein the thin film field effect transistor is a top contact type upper gate structure. 7. A method for fabricating a thin film field effect transistor, wherein the thin film field effect electric power 201140850 JOZUlpif crystal has at least a gate electrode, an insulating film, an active layer, a rice crack barrier layer, a source electrode, and a drain electrode formed on the substrate, and Forming the source and the electrode on the etch stop layer on the active layer, the manufacturing method is characterized by: using phosphoric acid, acetic acid, and nitric acid a mixed acid aqueous solution as a rice engraving liquid to form the source electrode and the immersion process; the etch resist layer is composed of an amorphous oxide containing In, Ga, and Zn having a Zn concentration of less than 20%; The active layer is composed of an amorphous oxide semiconductor containing In, Ga, and Zn, and the Zn concentration is higher than the Zn concentration of the etch barrier layer. 8. The method of producing a thin film field effect transistor according to claim 7, wherein the etching barrier layer has an In concentration of 4% by weight or more and a Ga concentration of 37% or more. 9. The method for producing a thin film field effect transistor according to claim 7, wherein the mixed acid aqueous solution comprises 70% by mass to 75 mass% of rhodium/phosphoric acid, and 5% by mass to 10% by mass of acetic acid, 1 Mass % to 5 mass% of terminal acid. 10. The method of producing a thin film field effect transistor according to claim 7, wherein the active layer and the etch stop layer form the same shape. The method for producing a thin-working field effect transistor according to any one of the preceding claims, wherein, before the process of forming the source and the drain, the method has the following a process of forming the gate on the substrate; forming a pattern on the substrate to form the insulating film to cover the gate; forming the active layer on the insulating film a process of forming the etch stop layer on the active layer; forming the source and the drain on the substrate in a process of forming the source and the drain Covering a portion of the surnamed barrier layer. 12. The method of manufacturing a thin film field effect transistor according to claim 11, wherein after forming the source and the electrodeless process, a protective layer is formed on the substrate to cover the substrate. The process of etching the barrier layer, the source and the drain. The method for producing a thin film field effect transistor according to any one of claims 7 to 10, wherein, before the process of forming the source and the drain, the process is as follows a process of forming the active layer on the substrate; and a process of forming the #etch resist layer on the active layer; in a process of forming the source and the drain, Forming the source and the drain on the substrate to cover a portion of the etch barrier layer; after forming the source and the gateless process, having a process of forming the An insulating film covering a process of etching the etch stop layer, the source and the drain; and a process of forming the gate on the insulating film. 43