201133390 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種影像管線（image pipeline)，特別是一種可 選徑（routable )的影像管線裝置。 【先前技術】 在現今的日常生活巾’各獅代佩_技術_位化技術 已非常普及’數位影像（digital image)便是—個很好的例子。數 •位影像係以陣列的型態紀錄影像中各個像素的值，且影像中每一 個像素的數值係以有限的位元（bit)來表示。 舉例而言’數位相機利用光感測器擁取影像並轉換為數位訊 號後’會經過-連㈣影像處理，喊理數位影像最f見的方法， 就是將各式祕_絲⑽er，亦稱域波器）套用在數位影 像上，例如藉由過滤器將數位影像之原始單色像素依序處理成 職騎與YUY料，靖触影_行如絲觀、影像銳 利化、改變影像色調、改變影像亮度對比或是邊緣偵測等數位影 像處理。 此外’為了進行需連續用到多個猶器之數位影像處理 ne)的架構便因應而生傭線將 bufj 串起’細崎職财11之線緩衝器如 使"用1乏^細嫩。㈣崎概_線緩衝器之 限於數位編^及更嶋不糊㈣的長度係受 〜被存取的掃描方式或數位影像的長度，而線緩衝器 201133390 的排數又受限於對應之過濾器的尺寸，例如3x3過滤器或7x7過 濾器。再者’影像管線所使用的過濾器皆為固定，因此影像管線 只能用於固定的數位影像處理，可以說是不具有擴張性。此外， 若影像管線之線緩衝器不敷使用時，亦只能設法將每一個線緩衝 器逐一加大，十分地不便。 【發明内容】 為解決上述問題，本發明提供一種可選徑的影像管線裝置 (routable image pipeline device)，適用於處理一影像。 根據本發明之第一實施範例，可選徑的影像管線裝置包括一 外部記憶體、一直接記憶體存取器（Direct Mem〇jy Access , DMA )、一影像管線控制器以及一過滤器層（）。其中外 部記憶體存有待纽的影像’且雜連結於DMA。影像管線控制 (physical memoiy allocation > PMA) ,χ 及-第-陣列控制器’而實體記憶體配置具有至少—實體緩衝暫 存單兀。根據本發明之第—陣顺㈣係電性相連於實體記憶體 配置與DMA。第-陣列控制n透過DMA接收影像且第一陣列 控制器根據疏、體位址配置（addresseGnfigu論n)設定將實體緩 衝暫存單70配置為對應第一陣列控制器的一第一邏輯緩衝暫存單 元。 過滤器層則包括具有多個過濾器的一第一過遽器組，且第一 過滤器組係對應電性相連於第—陣列控制g。第—過瀘器組透過 第-陣列控制器接收影像’ _選擇性地依據第—邏輯缓衝暫存 201133390 單元以及過濾器處理影像，並透過DMA將處理過的影像回存至外 部記憶體。 根據本發明之第二實施範例，可選徑的影像管線裝置之影像 管線控制器另可包括-第二陣列控制器，且過遽器層另包括與第 二陣列控制H電性相連的—第二過瀘、H組。其中第二過遽器組包 括多個過濾'器。第二陣列控制器係根據記憶體位址配置設定將實 體緩衝暫存單元配置為一第二邏輯緩衝暫存單元，且由第一過遽 籲器組承接影像。第二陣列控制I!將接收的影像傳送予第二過滤器 組以進行處理’第二過濾H組再選擇性地依據第二邏輯緩衝暫存 單元以及第：猶驗的過濾猶理影像。第二過齡組並透過 DMA將處理過的影像回存至外部記憶體。 可選徑的影像管線裝置之實體記紐配置另可包括一緩衝切 換器。緩衝切換器電性連結於實體緩衝暫存單元、第一陣列控制 器以及第二陣列控制器，且第___陣列控制器以及第二陣列控制器 鲁係透過緩衝切換器存取實體緩衝暫存單元。 根縣發明之第三實施細，可驗_彡像管絲置可包括 外部記憶體、直接記憶體存取器、影像f線控制器以及過遽器層 (filter layer)。其中影像管線控制器包括實體記憶體配置以及多個 陣列控制器。這些陣列控制器透過DMA接收影像，且陣列控制器 將實體緩衝暫存單元配置為個別對應這些陣列控制器的多個邏輯 緩衝暫存單元。 根據本發明之第四實施範例，過㈣層包括多個過遽器組。 201133390 其中每-個過濾器组對應電性相連於一個陣列控制器，且每一過 滤器組包括至少-猶、器。這些過絲組透過對應的陣列控制器 接收影像，崎行處理。過邮層選擇性地依據這麵輯緩衝暫 存單7L，以及這些縣驗所具有之猶^處理該影像並透過 DMA將處理過的影像回存至外部記憶體。 綜上所述’根據本發明之可選徑的影像管線裝置選擇性地使 用過滤器處理影像。可選㈣影像f線裝置將實體緩衝暫存單元 集中於影像管線控制器中管理’並透過陣列控制器對實體緩衝暫 存單元進行存取。也就是說，_控㈣可依據肋執行的過滤 器將實體緩衝暫存單元配置為對應之邏輯緩衝暫存單元。 此外，陣列控制器可以將事先從實體緩衝暫存單元中所配置 出來的邏輯緩衝暫存單元’視為工作所需的緩解元為之使用。 透過將實魏肺存單元配置為邏輯緩衝暫存單元的機制，影像 的掃描方式以及過濾器並不會對實體緩衝暫存單元造成限制。再 者，擴充之實體緩衝暫存單元能提供整個可選徑的影像管線裝置 使用。 此外’進行數位影像處理時可由過濾器組中選出需要的過濾 器或是旁通線，因此組合少數的過濾器便可進行各種數位影像處 理。且藉著新增過濾器或是成對的過濾器組以及陣列控制器，玎 選徑的影像管線裝置可輕易的被擴充。 【實施方式】 以下在實施方式中詳細敘述本發明之詳細特徵以及優點，其 内容足以使任何熟習相關技藝者了解本發明之技術内容並據以實 201133390 施’且根據本說明書所揭露之内容、”專利範圍及圖式，任何 熟”者可輕易地理解本發明相關之目的及優點。 _供—種可輕㈣像管料置（_恤 P=e d— ’係_於處理至卜影像，尤其是練影像，故 能夠應用在可處理數位影像的電子駭或,魏上。以下就各實施 祀例說明本發明所提供之可選㈣影像管線裝置的可能實 熊。 [第一實施範例] μ參第1圖」，其係為根據本發明之第—實施範例之可選 徑的影像管線裝置的架構示意圖。如「第i圖」所緣示，可選徑 的影像管線裝置包括-外部記憶體2G、—直接記憶體存取器 (Direct Memory Access ’ DMA) 3〇、一影像管線控制器 4〇 以及 -過遽器層（fltolayer) 5〇。其中影像管線控· 4()包括一實體 記憶體配置（physical memory allocation，PMA) 42 以及一第一陣 列控制器44 ’且PMA 42包括至少-實體緩衝暫存單元422。過 濾、器層50包括-第-過遽器組52,且第一過濾、器組52包括一 過濾器56a以及一 3x3過濾器56b。 外部s己憶體20内部存有待處理的影像，亦提供儲存可選徑的 影像管線裝置處理過後的結果。較佳的是，外部記憶體2〇可以是 雙倍資料速率同步動態隨機存取記憶體（D0Ubie Data Rate201133390 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to an image pipeline, and more particularly to a routable image pipeline apparatus. [Prior Art] In today's daily life towel, the lion technology is very popular. Digital image is a good example. The number of bitmap images records the value of each pixel in the image in the form of an array, and the value of each pixel in the image is represented by a finite number of bits. For example, 'the digital camera uses the light sensor to capture the image and convert it into a digital signal.' It will pass through the (four) image processing, and the most common way to call the digital image is to use the various secret _ silk (10) er, also known as The domain wave filter is applied to the digital image. For example, the original monochrome pixel of the digital image is sequentially processed into a professional riding and YUY material by a filter, and the image is sharp, the image is sharpened, the image color is changed, Change image brightness contrast or digital image processing such as edge detection. In addition, in order to carry out the processing of the digital image processing ne) which requires continuous use of multiple sects, the line of bufj is shupled by the line of the squad, and the line buffer of the squadron is as thin as possible. (4) The length of the _ line buffer is limited to the number of digits and the length of the quarantine (four) is the length of the scanned mode or digital image that is accessed, and the number of rows of the line buffer 201133390 is limited by the corresponding filtering. The size of the device, such as a 3x3 filter or a 7x7 filter. Furthermore, the filters used in the image pipeline are fixed, so the image pipeline can only be used for fixed digital image processing, which can be said to be non-expandable. In addition, if the line buffer of the image pipeline is not enough, it is only inconvenient to try to increase each line buffer one by one. SUMMARY OF THE INVENTION To solve the above problems, the present invention provides a routable image pipeline device suitable for processing an image. According to a first embodiment of the present invention, the optional image pipeline device includes an external memory, a direct memory accessor (DMA), an image pipeline controller, and a filter layer ( ). Among them, the external memory has an image of New Zealand and is heterozygous to DMA. The image pipeline control (physical memoiy allocation > PMA), - and - Array controllers, and the physical memory configuration have at least - a physical buffer temporary storage unit. According to the first aspect of the present invention, the array (four) is electrically connected to the physical memory configuration and DMA. The first array control n receives the image through the DMA and the first array controller configures the physical buffer temporary storage unit 70 to correspond to a first logical buffer temporary storage unit of the first array controller according to the sparse physical address configuration (addresseGnfigu theory n) . The filter layer then includes a first set of filters having a plurality of filters, and the first filter set is electrically coupled to the first array control g. The first-passer group receives the image through the first-array controller'_ selectively processes the image according to the first-logic buffer temporary storage unit 201133390 unit and the filter, and restores the processed image to the external memory through DMA. According to a second embodiment of the present invention, the image pipeline controller of the image path device of the optional diameter may further include a second array controller, and the buffer layer further includes an electrical connection with the second array control H. Two over, H group. The second filter group includes a plurality of filters. The second array controller configures the physical buffer temporary storage unit as a second logical buffer temporary storage unit according to the memory address configuration setting, and the image is received by the first interrupter group. The second array control I! transmits the received image to the second filter group for processing. The second filtered H group is selectively responsive to the second logical buffered temporary storage unit and the filtered filter image. The second overage group restores the processed image to the external memory through DMA. The physical record configuration of the optional image pipeline device may further include a buffer switch. The buffer switch is electrically connected to the physical buffer temporary storage unit, the first array controller, and the second array controller, and the ___ array controller and the second array controller are used to access the physical buffer through the buffer switch. Save the unit. According to the third embodiment of the invention of the root county, the image tube can include an external memory, a direct memory accessor, an image f-line controller, and a filter layer. The image pipeline controller includes a physical memory configuration and a plurality of array controllers. The array controllers receive images via DMA, and the array controller configures the physical buffer scratchpad units to individually correspond to the plurality of logical buffer scratchpad units of the array controllers. According to a fourth embodiment of the invention, the over (four) layer comprises a plurality of filter sets. 201133390 Each of the filter groups is electrically connected to an array controller, and each filter group includes at least a device. These over-wire groups receive images through the corresponding array controller and process them. The postal layer selectively relies on this buffered memory list 7L, and these county inspections have the ability to process the image and restore the processed image to the external memory through DMA. In summary, the optional image line device according to the present invention selectively uses a filter to process images. Optional (4) The video f-line device centralizes the physical buffer temporary storage unit in the image pipeline controller and accesses the physical buffer temporary storage unit through the array controller. That is to say, the _ control (4) can configure the physical buffer temporary storage unit as the corresponding logical buffer temporary storage unit according to the filter executed by the rib. In addition, the array controller can use the logical buffer temporary storage unit config previously configured from the physical buffer temporary storage unit as a mitigation element required for the operation. By configuring the real Wei lung storage unit as a logical buffer temporary storage unit, the image scanning method and the filter do not limit the physical buffer temporary storage unit. Furthermore, the expanded physical buffer temporary storage unit can provide an image pipeline device for the entire optional diameter. In addition, when the digital image processing is performed, the desired filter or bypass line can be selected from the filter group, so that a combination of a small number of filters can perform various digital image processing. With the addition of filters or pairs of filter sets and array controllers, the 影像-selected image pipeline unit can be easily expanded. [Embodiment] The detailed features and advantages of the present invention are described in detail below in the embodiments, which are sufficient to enable those skilled in the art to understand the technical contents of the present invention and according to the disclosure of the present disclosure. The objects and advantages associated with the present invention are readily understood by those skilled in the art. _ _ _ can be light (four) like tube material set (_ shirt P = ed - 'system _ in the processing of the image, especially the practice of the image, it can be applied to the electronic image processing digital image, Wei Shang. Below Each embodiment illustrates a possible real bear of the optional (four) image pipeline device provided by the present invention. [First Embodiment] μ Ref. FIG. 1 is an optional path according to a first embodiment of the present invention. Schematic diagram of the image pipeline device. As shown in the "i", the optional image pipeline device includes - external memory 2G, - Direct Memory Access 'DMA', 3 images The pipeline controller 4〇 and the fltolayer layer 5〇, wherein the image pipeline control 4() includes a physical memory allocation (PMA) 42 and a first array controller 44' and PMA 42 includes at least a physical buffer temporary storage unit 422. The filter, layer 50 includes a -th-passer group 52, and the first filter group 52 includes a filter 56a and a 3x3 filter 56b. There are images to be processed inside the body 20, and storage is also provided. The result of the processed image pipeline device of the optional diameter. Preferably, the external memory 2〇 can be a double data rate synchronous dynamic random access memory (D0Ubie Data Rate)
Synchronous Dynamic Random Access Memory，DDR SDRAM，亦 簡稱為DDR)。外部記憶體20内之待處理的影像可為靜止圖像 (still image)或是視訊（video)中的一個圖框（ftame)。換句話 201133390 ，，可選徑师像管魏置能夠處理單張靜止_，亦能 處理圖框的方式處理視訊。 續 職3〇與外部記憶體2()、第__控㈣料以 器組52電性相連。DMA 3〇由 匕慮 施…+名 憶體20中讀出待處理的影 =並將雜理的職傳送至第—陣顺㈣44處理，將影像排 以、 ^早70 422可為至少-線緩衝器 (hnebuffer)，所具有的線排數多寡係依據過助之尺寸。影像再 =第-猶器組52處理後傳至DMA3q，然絲過黯料 處理後的影像存回外部記憶體2〇。 更詳細地說，第-陣列控制器44會根據記憶體位址配置 (address conflguration)設定將實體緩衝暫存單元似配置為至少 一第-邏輯緩衝暫存單元。因此第—陣列控制器44可將陣列式排 列之處理過的影像暫存於第一邏輯緩衝暫存單元中。之後第一過 渡器組52可透過第-陣列控· 44得到第—邏輯緩衝暫存單元 中的影像資料，以繼續對影像處理。其中，第一陣列控制器私可 包括- ΜχΝ陣列控制器以及一购猶器陣列（胸齡 array)。藉由ΜχΝ P車列控制器對接收到的影像排列成ΜχΝ陣列 後，傳送至ΜχΝ贼彡像處理，例如去除雜訊等。 過滤器層50以第i滤器組52所包括的7χ7過渡器施或 3x3過濾器56b對影像進行例如數位影像處理⑺獅加卿 Processing，DIP)等處理。需注意的是，於本實施範例中，第一 過濾器組52係同時包括7x7過濾器56a以及3x3過濾器56b，也 201133390 &說第-過濾、胃組52包括錄過濾、ϋ。可選徑的影像管線裝置 係選擇性地以7x7過濾器56a或3χ3過濾器56b處理影像。7χ7 過遽器56a的過濾器尺寸為7χ7 (像素），而3χ3過濾器56b的過 滤器尺寸為如。在過濾器層％之中的這些過濾器尺寸之一係相 異於這些過濾斋尺寸之另一。換句話說過濾器層5〇中的過濾器尺 寸不全部相同。 需注意的是，過濾器層5〇適用之過濾器的尺寸並不限於 3x3、5x5或是7x7。過濾器可為任意之MxN過濾器，其中Μ與 Ν為正整數。 過遽器層5G包括的過瀘'器可為-原始數據過遽器（mw filter) ' (color filter array filter > CFA filter) 或疋売度彩度飽和度過濾器（luminance_chr〇min__chr_ filter ’ YUVfilteO，或是上述各種财器的子過遽器。 接下說明第4車列控制器44根據記憶體位址配置設定，動態 地將實體緩衝暫存單元422配置為第一邏輯緩衝暫存單元的方心 -般的影像係鱗_方式存放影像之各像素祕。然而整 張影像的解析度可能大·以暫存影像之線緩魅（即實體緩衝 暫存單元422) ’因此當影像被線緩魅讀人時，影像中能被線緩 衝器保存的部分係與影像被掃描的方式有關。請同時參閱「第2八 圖」以及f 2B ®」，其分別為陣列控制器以圖框基準 (fr—based)以及磁磚基準恤_based)的翻方式示意圖。 如「第2A圖」所示，第―_控制器44相當於將影像視為 -掃描酿6〇,關絲準輯财式射贿描圖框⑼内的像 201133390 f由左至右由上至下地被存進線緩衝器中。更詳細地說，圖框 ^的掃据方式係將掃描圖框6〇的像素一列（r〇w) 一列地依序 j線緩聽巾，财器層5Q再依序處理存於賴衝器之内的部 刀〇像圖框基準的掃描方式所使用的線緩衝器的長度與掃描圖 框60的長度相同，且不會產生輸出負荷（細响^ 。 磁磚基準的掃描方式又稱為區塊基準（block-based)的掃描方 式。掃描圖框6〇被切分成多個掃描子圖框62後再被掃描，1中 母-個掃描子圖框62被稱為—個磁磚或—個區塊。磁磚基準的掃 描方式係於—個掃描子圖框62巾以_基準卿财式進行掃 描’再移往下—個掃描子圖框_續掃描。磁磚基準的掃描方式 所使用的線緩衝器的長度與掃描子圖框62的長度相同，而掃描子 圖框62的長度一般可設定為64像素或是128像素。此外 影像被套用的過濾器，磁碑基準的掃描方式於掃描子圖框幻 的交界處產生輸出負荷。 如上所述，圖框基準的掃描方式㈣的線緩衝器的長度盘掃 =圖框60相同’而磁碑基準的掃描方式所需的線緩衝器的長度與 掃描子圖框62相同。由於一般視訊的影像的解析度較低（例: 320x240) ’因此能夠以圖框基準的掃描方式處理影像。相對的， 數位相機等裝置揭取的靜止圖像通常具有較大的解析度（例如 1024x768)，因此適於使用磁碑基準的掃描方式。 但本發明所提供之可選徑的影像處理裝置並不對實體 存單元422的長度或大小進行限制。第一陣列控制器44_= 體位址配置設定將實體缓衝暫存單元422配置為邏輯緩衝暫存^ 201133390 影像。 其中：第3A圖」、「第3B圖」、「第3c圖」以及「第3d圖」， 其:第3A圖」係為根據本發明一實施範例之實體緩衝暫存單元 單元之配置示_。 例之第—邏輯緩衝暫存 於本實施範例中，實體緩衝暫存單元422之大小係64㈣6位 :例^彳__的_ _像素，骑— =立元广表示時’則邏輯緩衝暫存單元的配置可以如 —I 陣列控制器44以重新分配記憶體位址的方式將 …州 寸為_的第一邏輯緩衝暫存 早兀423’組成四個_χ8的第一邏輯緩衝暫存單元似以供第一 陣列控制器44存取影像資料。 又例如當待處理的影像關長為_像素，且每—個像 值需要以16位元表示時，邏輯緩衝暫存單元的配置可以如「第冗 圖」。第-陣列控制器44可將實體緩衝暫存單元422直接 二邏輯緩衝暫存單元423，組成兩個6例6的第-邏輯緩衝暫存 卓7L 423以供第-陣列控制器44存取影像資料。 另例如當待處理的影像的列長為像素，且每—個的 值需要以8位元表示時，邏輯緩衝暫存單元的配置可以如「_ 圖」。第-_控制器44以重新分配記憶體位址的方式將實 衝暫存單元422配置成尺寸為·χ8的第—邏輯緩衝暫γ 423，組成兩個128〇χ8的第一邏輯緩衝暫存單元奶以供一二 列控制器44存取影像資料。 ’、 車 11 201133390 則述係在貫體δ己憶體配置42只具有一個實體緩衝暫存單元 422的If况下’揭示第一陣列控制器μ如何根據記憶體位址配置 。又疋利用單-的實體緩衝暫存單元422配置成所需的第一邏輯 緩衝暫存單元423。 以下係更進-步揭不當實體記憶體配置犯至少具有多個實體 緩衝暫存單元422時，第一陣列控制器44如何根據記憶體位址配 置认定’利用多個實體緩衝暫存單元422配置成所需的第一邏輯 緩衝暫存單元423。 "月參IMA圖」、「第4B圖」、「第4C圖」以及「第4D圖」， 其中第4A圖」係為根據本發明一實施範例之實體緩衝暫存單元 之配置不,’其餘縣根據本發日林同實施細之第—邏輯緩 衝暫存單元之配置示意圖。 於本實施範例中，可選徑的影像管線裝置的實體記憶體配置 42包括三個大小同為6例6的實體緩衝暫存單元伽、概以 及 422c 〇 例如當待處理的影像的列長為64〇像素，且每一個像素制 需要以8位元⑽）表示時’邏輯緩衝暫存單元的配置可以如「^ —輪編4，細咖_方式賴 ^衝暫存早以細及概_分割成兩塊，以制所需之月 寸為6你8的第一邏輯緩衝暫存單元备备他以及鲁 如此-來’聽64㈣的第—觀緩㈣存單元低、働、徽 以及423d來供第-陣·繼44存取影像詩。 又例如當待處理的影像的列長為64〇像素，且每一個像素的 201133390 值需要幻6位元表示時’邏輯緩衝暫存單元的配置可以如「第吣 圖」。第一陣列控制器44可將實艟緩衝暫存單元幻。以及似办 直接作為第-邏輯緩衝暫存單元423a以及42%來供第一陣列控 制器44存取影像資料。 ^ 另例如當待處_影像的職為刪像素，且每_個像素的 值需要以8位元表示時，邏輯緩衝暫存單元的配置可以如「第奶 圖」第P車列控制為44可以重新分配記憶體位址的方式將實體 緩衝暫存單元422a以及概配置成尺寸為ΐ2δ㈣的第一邏輯緩 衝暫存單元423a以及423b，來供第一陣列控制器私存取影像資 -此外’第一過濾、裔組52中被選用的過濾器亦會影響到邏輯緩 衝暫存單元的分配。可雜的影像處理裝置依舰行的影像處理 内容’選擇執行第-過濾器組52的和過濾器施或是如過魔 线b。且由於對制過濾器而言，當其影像資料接收到第_ ^弟Μ個像素時，就可以開始運算。因此當以w猶^ 疋的過滤器56b處理影像時，第—過齡组％個別需要至 (=i (或稱線緩_的排數）或是㈣列的部分影像才 ==_衝器之排數為6,就可細過滤器^ 德 田7過濾器56a接收影像資料到第7列之第7個 = 而當緩衝器之排數為3，可透過>3 :厂:处理讀，且當3x3過濾器56b接收影像資料到第3 列之第3轉鰣，財叫始縣。 [弟一貫施範例] 13 201133390 請參照「第5圖」’其係為根據本發明之第二實施範例之可選 徑的影像管線裝置的架構示意圖。 、 與第一實施範例的差里虛左於. …处在於.可選徑的影像管線裝置的過 濾器層50另包括一第二過滹哭έ ,十 愿。〜且54 ’且影像管線控制器40另包Synchronous Dynamic Random Access Memory, DDR SDRAM (also referred to as DDR). The image to be processed in the external memory 20 can be a still image or a ftame in the video. In other words, 201133390, the optional tracker can handle the single frame while still processing the video. The continuation of the job is electrically connected to the external memory 2 () and the __ control (four). DMA 3 〇 匕 施 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + The buffer (hnebuffer) has a number of rows and rows depending on the size of the help. The image is again passed to the DMA3q after the processing of the first-sigma group 52, and the image processed by the silk is stored back to the external memory 2〇. In more detail, the first array controller 44 configures the physical buffer temporary storage unit as at least one first-logic buffer temporary storage unit according to the address conflguration setting. Therefore, the first array controller 44 can temporarily store the processed images of the array arrangement in the first logical buffer temporary storage unit. The first transition group 52 can then obtain the image data in the first logical buffer temporary storage unit through the first array control 44 to continue the image processing. The first array controller may include a ΜχΝ array controller and a solar array (thoracic array). The received image is arranged into an array by the ΜχΝ P train controller, and then transmitted to the thief image processing, for example, to remove noise. The filter layer 50 performs processing such as digital image processing (7) lion processing, DIP, etc. on the image by the 7χ7 transponder or the 3x3 filter 56b included in the i-th filter group 52. It should be noted that in the present embodiment, the first filter group 52 includes both the 7x7 filter 56a and the 3x3 filter 56b, and also the 2011-13090 & said first-filter, stomach group 52 includes recording filter, ϋ. The optional image line device selectively processes the image with a 7x7 filter 56a or a 3χ3 filter 56b. The filter size of the 7χ7 filter 56a is 7χ7 (pixels), and the filter size of the 3χ3 filter 56b is as follows. One of these filter sizes among the filter layers % is different from the other of these filter sizes. In other words, the filter sizes in the filter layer 5〇 are not all the same. It should be noted that the size of the filter layer 5 is not limited to 3x3, 5x5 or 7x7. The filter can be any MxN filter, where Μ and Ν are positive integers. The passer layer included in the passer layer 5G may be a "color filter array filter > CFA filter" or a chroma chroma saturation filter (luminance_chr〇min__chr_filter ' YUVfilteO, or a sub-filter of the above various financial devices. Next, the fourth train controller 44 dynamically configures the physical buffer temporary storage unit 422 as the first logical buffer temporary storage unit according to the memory address configuration setting. The heart-like image scales _ way to store the pixel secrets of the image. However, the resolution of the entire image may be large. The temporary image line is stunned (ie, the physical buffer temporary storage unit 422) 'So when the image is lined When reading a person, the part of the image that can be saved by the line buffer is related to the way the image is scanned. Please also refer to "2nd 8th" and f 2B ®", which are the frame controllers. (fr-based) and tile reference shirt _based). As shown in "Picture 2A", the __ controller 44 is equivalent to viewing the image as a -scan 6 〇, and the image in the 丝 准 准 射 射 射 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 The lower ground is stored in the line buffer. In more detail, the scanning method of the frame ^ is to scan the frame of the pixel of the frame 6〇 (r〇w) in a row, followed by the j-line to listen to the towel, and the financial layer 5Q is sequentially processed and stored in the Lai Chong The length of the line buffer used in the scanning method of the frame reference frame is the same as the length of the scanning frame 60, and the output load is not generated (fine sound ^. The scanning method of the tile reference is also called A block-based scanning method. The scanning frame 6 is divided into a plurality of scanning sub-frames 62 and then scanned, and the parent-scanning sub-frame 62 is called a tile or - Blocks. The scanning method of the tile reference is based on a scan sub-frame 62. The scan is performed by the _ benchmark clearing method and then moved to the next scan sub-frame _ continuous scan. The scanning method of the tile reference The length of the line buffer used is the same as the length of the scanning sub-frame 62, and the length of the scanning sub-frame 62 can be generally set to 64 pixels or 128 pixels. In addition, the image is applied to the filter, and the scanning of the magnetic reference is performed. The way is to generate an output load at the intersection of the scanned sub-frames. As mentioned above, the frame base Scanning method (4) The length of the line buffer is the same as that of frame 60. The length of the line buffer required for the scanning method of the magnetic tablet reference is the same as that of the scanning sub-frame 62. Since the resolution of the general video image is higher than that of the scanning method. Low (example: 320x240) 'Therefore, it is possible to process images in a frame-based scanning manner. In contrast, still images taken by devices such as digital cameras usually have a large resolution (for example, 1024x768), so they are suitable for using magnetic monuments. The scanning method of the reference. However, the image processing apparatus of the optional path provided by the present invention does not limit the length or size of the physical storage unit 422. The first array controller 44_= the body address configuration setting will be the physical buffer temporary storage unit 422. It is configured as a logical buffer temporary storage ^ 201133390 image. Among them: 3A map, 3B map, 3c map, and 3d map, FIG. 3A is an embodiment according to the present invention. The configuration of the physical buffer temporary storage unit is shown as an example. The first logical buffer is temporarily stored in the present embodiment. The size of the physical buffer temporary storage unit 422 is 64 (four) 6 bits: _ _ pixels of the example ^ __, riding - = Li Yuan When the indication is wide, the configuration of the logical buffer temporary storage unit can be such that the I-array controller 44 re-allocates the memory address to form the first logical buffer of the state inch _ as early as 423' to form four _χ8 The first logical buffer temporary storage unit is similar to the first array controller 44 for accessing the image data. For example, when the image to be processed is _pixels, and each image value needs to be represented by 16 bits, the logic The configuration of the buffer temporary storage unit may be, for example, a “redundancy map.” The first array controller 44 may directly connect the physical buffer temporary storage unit 422 to the second logical buffer temporary storage unit 423 to form two sixth-case 6-first logical buffer temporary storage. The 7L 423 is used by the first array controller 44 to access image data. For example, when the column length of the image to be processed is a pixel, and the value of each image needs to be represented by 8 bits, the configuration of the logical buffer temporary storage unit can be as "_ map". The first__ controller 44 configures the real buffer temporary storage unit 422 to the first logical buffer temporary γ 423 of size χ8 in a manner of reallocating the memory address, and constitutes two 128 〇χ 8 first logical buffer temporary storage units. The milk is used by one or two columns of controllers 44 to access image data. ', car 11 201133390 is described in the case where the body δ memory structure 42 has only one physical buffer temporary storage unit 422' to disclose how the first array controller μ is configured according to the memory address. Further, the single physical buffer temporary storage unit 422 is configured to be the first logical buffer temporary storage unit 423 required. In the following, when the physical memory configuration has at least a plurality of physical buffer temporary storage units 422, how does the first array controller 44 determine that the plurality of physical buffer temporary storage units 422 are configured according to the memory address configuration? The first logical buffer temporary storage unit 423 is required. "Monthly IMA map," 4B map, "4C map" and "4D map", wherein Fig. 4A is a configuration of a physical buffer temporary storage unit according to an embodiment of the present invention, ' The rest of the counties according to the implementation of the same day, the implementation of the detailed - logical buffer temporary storage unit configuration diagram. In this embodiment, the physical memory configuration 42 of the image pipeline device of the optional path includes three physical buffer temporary storage units, which are the same size as 6 cases, and 422c, for example, when the column length of the image to be processed is 64〇 pixels, and each pixel system needs to be expressed in 8-bit (10)) 'The configuration of the logical buffer temporary storage unit can be as follows: ^^轮轮编4, fine coffee_method _ _ _ temporary storage as early as detailed _ Divide into two pieces, to prepare the required first month of the 8th logical buffer temporary storage unit for you and Lu to do so - to listen to 64 (four) of the first - view slow (four) storage unit low, 働, emblem and 423d For the first-matrix and the 44 access to the image poem. For example, when the column length of the image to be processed is 64 pixels, and the 201133390 value of each pixel needs a magic 6-bit representation, the configuration of the logical buffer temporary storage unit It can be like "the map". The first array controller 44 can phantom the buffer buffer. And the first array controller 44 can access the image data directly as the first-logic buffer temporary storage unit 423a and 42%. ^ For example, when the position of the _image is deleted, and the value of each pixel needs to be represented by 8 bits, the configuration of the logical buffer temporary storage unit can be controlled as 44 for the "Pot" The physical buffer temporary storage unit 422a and the first logical buffer temporary storage units 423a and 423b configured to have a size of ΐ2δ(4) can be re-allocated for the first array controller to access the image resource-- A filter selected in the filter group 52 also affects the allocation of the logical buffer temporary storage unit. The miscellaneous image processing device selects and executes the filter unit 52 and the filter device according to the image processing content of the ship. And because the filter is used, when the image data receives the first pixel, the operation can be started. Therefore, when the image is processed by the filter 56b, the first-overage group % needs to individually (=i (or the number of rows of the slow _) or the partial image of the (four) column ==_ The number of rows is 6, and the filter can be fine. ^ The Deta 7 filter 56a receives the image data to the 7th column of the 7th column = and when the number of buffers is 3, it can be transmitted through the >3: factory: processing read And when the 3x3 filter 56b receives the image data to the third turn of the third column, the capital is called the county. [Despite the example] 13 201133390 Please refer to "figure 5", which is the second according to the present invention. The schematic diagram of the image pipeline device of the optional path of the embodiment is implemented. The difference between the image and the first embodiment is that the filter layer 50 of the image pipeline device of the optional diameter further includes a second pass. Cry, ten willing. ~ and 54 'and image pipeline controller 40
括一弟一陣列控制器46。並中莖-、两DD ，、τ弟一過濾器組54係與第二陣列控制 器46對應電性相連，且第二堝、清 ^4 »。組54包括3x3過濾器56c和 56d。 诚=1二陣顺制器46根據記_她義定將實體緩 ^子早疋422配置為—第二邏輯緩衝暫存單元，而配置原理已 ^-實施射揭示，請參考之，遂不再贅述。第二陣列控制器 亦可包括續陣列控制器以及咖過滤器陣列（職施r ，）’以藉由漏_控制器對接收到的影像排列成咖陣列 後，傳送至ΜχΝ過濾器陣列作影像處理。 職30由外部記憶體2〇中讀出待處理的影像，將待處理的 影像傳送至第-陣列控制器44進行麵排列的處理。第一陣列控 制器44將影像減_型式，而重轉_雜會將影像暫存於 第一邏輯緩衝暫存單元423 t。重新排列好之後，再提供予第一 過渡器組52處理。之後第二陣列控制器46由第一過濾器组^接 收其處理過的影像，以對影像進-步排列成第二财驗^所需 的陣列形式。重卿卜列程會將影像暫存於第二邏輯緩衝暫存單 元。重新排列好之後，再傳送至第二過濾器組54處理。第二過渡 器組54收到影像後’選擇性地以3x3過渡器56c或是⑹處理： 到的影像’再將影像結果傳至DMA30，然後透過DMA3〇將處理 201133390 後的影像存回外部記憶體2〇。 更佳的是，第一過濾器組52或是第二過濾器組54另可包括 一旁通線（bypass line) 58。若在第一過濾器組52之中旁通線％ 被選定並執行，則表示7x7過濾器56a以及3χ3過濾器5沾於這 次的影像處理階段中不被使用。第二過濾器組54的情況亦是同 樣。因此可選徑的影像管線裝置於一個階段的影像處理中，能夠 以下列這些組合的過濾器進行處理：7x7過濾器56a、3x3過濾器 56b 3x3過;慮态56c、3x3過渡器56d、7x7過濾器56a與3x3過 • 濾器56c、7x7過濾器56a與3x3過濾器56d、3x3過濾器56b與3x3 過慮斋56c ’以及3x3過濾、器56b與3x3過渡器56d。 旁通線58可以是第一過濾器組52或第二過濾器組54中，以 一條電線實做而成，旁通線58的概念亦可是由軟體的方式實現。 在第—過濾器組52或第二過濾器組54中若無任何的過濾器被選 疋以處理影像，即表示旁通線58被選定。其中第一陣列控制器44 以及第二陣列控制器46可一併對實體緩衝暫存單元422進行配 • 置。意即實體緩衝暫存單元422可至少被分為兩個部分，且個別 被第—陣列控制器44以及第二陣列控制器46配置為第一邏輯緩 衝暫存單元423以及第二邏輯缓衝暫存單元。 此外，第一過濾組52之過濾器處理影像之後，可不經由第二 過濾器組54 (即第二過濾器組54的旁通線58被配置命令指定）， 並透過DMA30將處理過的影像回存於外部記憶體2〇。 [弟二貫施範例] 凊參照「第6圖」’其係為根據本發明之第三實施範例之可選 15 201133390 徑的影像管線裝置的架構示意圖。 #制^例之中’可選徑的影像管線裝置包括第一陣列 =二弟二陣列控制器46、第-磁㈣ ς、，·。·、中第-陣列控制器44與第一過級组52對應電性相 連2二陣列控制器46與第二過濾器組54對應電性相連。第一 I二°。’且52與第—過濾、器組54個別只包括-個過濾器（7x7過濾 參置3 ^慮益56b)以及旁通線58。且可選徑的影像管線 係選姆地以7X7猶器恤與3x3過濾器56b處理影像。 個話心可選徑的影像管線裝置包括多個過絲組以及多 口 ’其中每一個過濾、器組對應電性相連於一個陣列控制 =這些職器組個別至少包括—_濾器以處理影像，並可包 通線5。8。每—個陣列控制器將實體緩衝暫存單元似配置為 :的邏，緩衝暫存單元，並提供給對應之過滤器組之過濾器使 结;ΐ卩車列控制1144以及第二陣列控制1146個別將實體 給-存單元幻2配置為第一邏輯緩衝暫存單元423以及第二邏 -存單元’以供第—猶器組52之W過_如以及第 ―匕濾益組54之3x3過濾器56c使用。 而^的疋’當僅有—個過濾驗的過絲被指定，且其餘 以過’慮盗組均被指定執行旁通線58時，實體緩衝暫存單元422可 $、皮配置為個對應被指定之過濾器的邏輯緩衝暫存單元。最 <再依據k麵輯緩崎存單核及這㈣為處理影像。 第—:例來說’ §配置命令指定以7χ7過濾器地處理影像時， 車歹J控制器52依據配置命令以及7><7也慮器5如配置實體缓 16 201133390 衝暫存單元422並得到第一邏輯緩衝暫存單元423。且可選徑的影 像管線裝置僅以7x7過濾器56a以及第一邏輯緩衝暫存單元423 處理影像。 更佳的是，7x7過濾器56a處理完影像之後，可透過DMA 30 將影像回存進外部記憶體2〇。 [弟四實施範例] μ參照「第7圖」，其係為根據本發明第四實施範例之可選徑 的影像管線裝置的架構示意圖。接下來藉由第四實施範例，介紹 鲁 完整的可選徑的影像處理方法。 如「第7圖」所示，可選徑的影像管線裝置包括外部記憶體 20 ' DMA30、影像管線控制器4〇以過濾器層50。其中影像管線 控制器40之實體記憶體配置42包括多個實體緩衝暫存單元422 以及一緩衝切換器（buffer switch) 424，且影像管線控制器4〇另 包括第一陣列控制器44、第二陣列控制器46以及一第三陣列控制 态48。而過濾器層5〇包括第一過濾器組52、第二過濾器組54以 • 及一第三過濾器組55。 其中，第一過濾器組52包括7x7過濾器56a、3x3過濾器56b 以及3x3過濾器56c ;第二過濾器組54包括3x3過濾器56d以及 5χ5過濾器56e ;第三過濾器組55包括3x3過濾器56f以及3x3 過濾器56g。且7x7過濾器56a係為原始數據過濾器；3x3過濾器 56b、3x3過濾器56d以及3x3過濾器56f係為CFA過濾器；3x3 過濾器56c、5x5過濾器56e以及3x3過濾器56g係為YUV過濾 器。 17 201133390 岛请⑽!丨㈣控制态48同樣可包括MxN陣列控制器以及ΜχΝ _flltera卿）’以藉由MxN陣列控制輯接收到 的影像排舰細陣職，傳送至MxN魏轉職彡像處理。 舉例而吕，當數位相機擷取影像並將其處理$彻色p門 ㈤〇rspaee)格式的影像時，可驗的影像管線裝影= 原始數據，並制全部的過義處理影像。處理的過程可分為= 個階段’依序是：處理影像的縣數據（亦可稱為縣階段，即 啤）；將影像轉換成RGB色彩空間的格式（亦可稱為腦 階段以X及將RGB色彩空間格式的影像轉換為彻 式（亦可稱為YUV階段）。 可選徑的影像官線裝置於不同的影像處理階段中，可選用不 同的猶器來處理影像。在每―階段開始處理影像之前，可選炉 的影像管線裝置接收配置命令，以得知於此階段中要㈣個_ 些過滤器處的猶ϋ處理影像。更進_步地說，由於在每一個階 段中所選關财器可能不同，陣列處理器需依據需求來重新將 實體緩衝暫存單元422重新配置為合適的邏輯緩衝暫存單元。且 在每’段的處理結束後，處理過的影像均會被回存於外部記 憶體20。 ° 假設數位械以磁磚鮮的掃財式被存取影像（靜止圖 像）。首先於原始階段時，僅有第-過渡器組52的7χ7過遽器瓜 被選用，第二過濾' 器組54以及第三顯器組55均執行旁通線° %。 因此第-陣列控制器44依據掃描方式以及>7過濾器將實體 緩衝暫存單it 422配置為第-邏輯緩衝暫存單元423，且第一陣列 18 201133390 控制器44係透過緩衝切換器424存取實體緩衝暫存單元幻2。則 可選徑的影像官線裝置以7x7過濾器56a以及第一邏輯緩衝暫存 單兀423處理影像’再把7x7過濾器5如處理過的影像透過〇μα 30回存於外部記憶體2〇。 接著於RGB階段時，第一陣列控制器、44、第二陣列控制器 46以及第三陣列控制器48依據掃描方式以*⑽喊器56卜5二 以及56f’將實體緩衝暫存單元422重新配置為第一邏輯緩衝暫存 單元423、第二邏輯緩衝暫存單元以及第三邏輯緩衝暫存單元。可 _ ㈣的景嫌官雜置由外部記紐2G讀出經原始階段處理過後的 影像，再依序以3x3過遽器56b、56d以及财配合第一邏輯緩衝 暫存單元423、第二邏輯緩衝暫存單元以及第三邏輯_暫存單元 處理影像，並將處理完的影像回存於外部記憶體2〇。 最後於yuv p皆段時，帛一陣列控制器44、第二陣列控制器 46以及第三陣列控制器48依據掃描方式以及3χ3過渡器細、的 過濾β 56e以及3x3過濾器56g’將實體緩衝暫存單元422重新配 • 置為第-邏輯緩衝暫存單元423、第二邏輯_暫存單元以及第三 邏輯緩㈣存單元。可選制影像管_置由外部記憶體2〇如 經原始階段以及RGB階段處理過後的影像，再依序以的過渡哭 56c、5χ5過濾器56e以及3χ3職器％配合第一邏輯緩衝^ 單元423H輯緩衝暫存單相及第三緩衝暫存單元處理 影像，並將全部處理完成的影像回存於外部記憶體如。An array controller 46 is included. The middle stem-, two-DD, and τ-one filter sets 54 are electrically connected to the second array controller 46, and the second 清, qing ^4 ». Group 54 includes 3x3 filters 56c and 56d. Cheng = 2 two-arranged controller 46 according to the record _ she will set the entity to slow down the early 422 configuration as the second logical buffer temporary storage unit, and the configuration principle has been ^- implementation of the disclosure, please refer to it, no longer Narration. The second array controller may further include a continuation array controller and a coffee filter array (for the application of the image filter array) to arrange the received images into a coffee grid array by the drain controller, and then transmit the image to the ΜχΝ filter array for image processing. deal with. The job 30 reads out the image to be processed from the external memory 2, and transfers the image to be processed to the first array controller 44 for surface alignment processing. The first array controller 44 subtracts the image from the image, and the image is temporarily stored in the first logical buffer temporary storage unit 423t. After rearranging, it is then provided to the first transitioner group 52 for processing. The second array controller 46 then receives the processed images from the first filter group to arrange the images into the array form required for the second verification. The image will be temporarily stored in the second logical buffer temporary storage unit. After rearranging, it is transferred to the second filter group 54 for processing. After receiving the image, the second transitioner group 54 selectively processes the image by the 3x3 transitioner 56c or (6): the image is transmitted to the DMA 30, and then the image processed after 201133390 is stored back to the external memory through the DMA3. Body 2〇. More preferably, the first filter set 52 or the second filter set 54 may further include a bypass line 58. If the bypass line % is selected and executed in the first filter group 52, it means that the 7x7 filter 56a and the 3χ3 filter 5 are not used in the image processing stage of this time. The same is true for the second filter group 54. Therefore, the image pipeline device of the optional diameter can be processed by the following combination of filters in one stage of image processing: 7x7 filter 56a, 3x3 filter 56b 3x3 over; state 56c, 3x3 transition 56d, 7x7 filter The 56a and 3x3 filters 56c, 7x7 filters 56a and 3x3 filters 56d, 3x3 filters 56b and 3x3 filter 56c' and 3x3 filters, 56b and 3x3 transitions 56d. The bypass line 58 may be in the first filter group 52 or the second filter group 54 and implemented as a single wire. The concept of the bypass line 58 may also be implemented in a software manner. If none of the filters in the first filter group 52 or the second filter group 54 are selected to process the image, the bypass line 58 is selected. The first array controller 44 and the second array controller 46 can be configured with the physical buffer temporary storage unit 422. That is, the physical buffer temporary storage unit 422 can be divided into at least two parts, and is configured by the first array controller 44 and the second array controller 46 as the first logical buffer temporary storage unit 423 and the second logical buffer temporary. Save the unit. In addition, after the filter of the first filter group 52 processes the image, the processed image may be returned through the DMA 30 without passing through the second filter group 54 (ie, the bypass line 58 of the second filter group 54 is specified by the configuration command). Stored in external memory 2〇. [Different Example] Referring to "Fig. 6", it is a schematic diagram of the structure of an optional image line device of the 2011 20119090 diameter according to the third embodiment of the present invention. The image pipeline device of the optional path includes a first array = two second array controller 46, a first magnetic (four) ς, . The intermediate array controller 44 is electrically connected to the first supergroup 52. The two array controllers 46 are electrically connected to the second filter group 54. The first I two. And 52 and the filter unit 54 individually include only one filter (7x7 filter 3^bene 56b) and a bypass line 58. The image path of the optional path is selected to process the image with a 7X7 vestibule and a 3x3 filter 56b. The image line device of the voice-selectable path comprises a plurality of wire sets and a plurality of ports, wherein each of the filters and the groups are electrically connected to an array control=these groups individually include at least a filter to process images, And can pass the line 5. 8. Each array controller configures the physical buffer temporary storage unit as: a logical, buffered temporary storage unit, and provides a filter for the corresponding filter group; the brake train control 1144 and the second array control 1146 Individually, the entity-storage unit phantom 2 is configured as a first logical buffer temporary storage unit 423 and a second logical-storage unit 'for the first----------------------------------- Filter 56c is used. And when the only one filter is specified, and the rest is specified to execute the bypass line 58, the physical buffer temporary storage unit 422 can be configured as a corresponding The logical buffer temporary storage unit of the specified filter. The most <and according to the k-faced slow-save single core and this (four) for processing images. First—: For example, when the configuration command specifies that the image is processed with a 7χ7 filter, the rutting controller J is configured according to the configuration command and 7><7<7> And obtaining the first logical buffer temporary storage unit 423. The optional image pipeline device processes the image only with the 7x7 filter 56a and the first logical buffer temporary storage unit 423. More preferably, after the 7x7 filter 56a has processed the image, the image can be restored to the external memory via the DMA 30. [Fourth Embodiment Example] μ refers to "Fig. 7" which is a schematic structural view of an image path apparatus of an optional diameter according to a fourth embodiment of the present invention. Next, with the fourth embodiment, the image processing method of Lu's complete optional path is introduced. As shown in Fig. 7, the optional image line device includes an external memory 20' DMA30, an image line controller 4, and a filter layer 50. The physical memory configuration 42 of the image pipeline controller 40 includes a plurality of physical buffer temporary storage units 422 and a buffer switch 424, and the image pipeline controller 4 further includes a first array controller 44 and a second Array controller 46 and a third array of control states 48. The filter layer 5 includes a first filter group 52, a second filter group 54 and a third filter group 55. Wherein, the first filter group 52 includes a 7x7 filter 56a, a 3x3 filter 56b, and a 3x3 filter 56c; the second filter group 54 includes a 3x3 filter 56d and a 5χ5 filter 56e; and the third filter group 55 includes 3x3 filtering. The 56f and the 3x3 filter 56g. And the 7x7 filter 56a is a raw data filter; the 3x3 filter 56b, the 3x3 filter 56d, and the 3x3 filter 56f are CFA filters; the 3x3 filter 56c, the 5x5 filter 56e, and the 3x3 filter 56g are YUV filters. Device. 17 201133390 Island please (10)! 丨 (4) Control state 48 can also include MxN array controller and _ _fllteraqing) 'to receive images from the MxN array control series, and transfer to the MxN Wei transfer job image processing . For example, when a digital camera captures an image and processes it in an image of the color (p) 〇rspaee format, the image pipeline is imaged = raw data, and all the images are processed. The process of processing can be divided into = stages [sequentially: county data for processing images (also known as county stage, ie beer); format for converting images into RGB color space (also known as brain stage with X and Converts images in RGB color space format to slash (also known as YUV phase). The optional image of the official line device can be used in different image processing stages, and different sects can be used to process the image. Before starting to process the image, the image pipeline device of the optional furnace receives the configuration command to know that at this stage, (four) _ some filters are still processing the image. Further, in each stage, because in each stage The selected gateway may be different, and the array processor needs to reconfigure the physical buffer temporary storage unit 422 as a suitable logical buffer temporary storage unit according to requirements. After the processing of each segment, the processed image will be processed. It is stored back in the external memory 20. ° It is assumed that the digital device is accessed by the tile-sweeping image (still image). First, in the original stage, only the 7χ7 filter of the first-transition group 52 Melon is selected, Both the filter set 54 and the third display set 55 perform the bypass line %. Therefore, the first-array controller 44 configures the physical buffer temporary storage unit it 422 as the first-logic buffer according to the scan mode and the >7 filter. The temporary storage unit 423, and the first array 18 201133390 controller 44 accesses the physical buffer temporary storage unit phantom 2 through the buffer switch 424. The optional image official line device uses the 7x7 filter 56a and the first logical buffer The storage unit 423 processes the image and then restores the processed image of the 7x7 filter 5 to the external memory 2 through the 〇μα 30. Then, in the RGB phase, the first array controller 44 and the second array controller 46 And the third array controller 48 reconfigures the physical buffer temporary storage unit 422 as the first logical buffer temporary storage unit 423, the second logical buffer temporary storage unit, and the first by the *(10) spoofing 56b 5 and 56f' according to the scanning mode. Three logic buffer temporary storage unit. Can be _ (four) of the scene suspect miscellaneous reading from the external record 2G read through the original stage of the processed image, and then in order to 3x3 filter 56b, 56d and financial cooperation first logic buffer Storage unit 423, second The buffer temporary storage unit and the third logical_temporary unit process the image, and the processed image is stored in the external memory 2〇. Finally, when the yuv p is segmented, the first array controller 44 and the second array control The processor 46 and the third array controller 48 reconfigure the physical buffer temporary storage unit 422 as the first logical buffer temporary storage unit 423 according to the scanning mode and the 3χ3 transitioner fine filtering β 56e and 3x3 filter 56g′ Two logical_temporary storage unit and third logical slow (four) storage unit. Optional image tube _ is set by external memory 2, such as the image processed by the original stage and RGB stage, and then the transition is crying 56c, 5χ5 The filters 56e and 3χ3 cooperate with the first logical buffer unit 423H to buffer the temporary single-phase and the third buffer temporary storage unit to process the image, and store all the processed images in the external memory.
再舉例而言，當攝雜欲將魏轉_RGB 時，可選徑的影綠線裝置僅進行RGB階段的影像二更二 19 201133390 地說’可選徑的影像管線裝置可關框基準的掃描方式存取影 ’且僅以3x3過滤器56b、56d、56f以及對應之第—處理視訊 像 之圖框時，可選徑的影像管線裝置僅以邏輯緩衝暫存單元423、第 二邏輯緩衝暫存單元以及第三邏輯緩衝暫存單元處理影像（視訊 的各個’）’並將處理完的f彡像贿於外部記憶體2〇。 值得-提狀’藉由上述之可選徑的影像管料置的έ士構， 可選徑的影像管職置巾㈣十分㈣地騎擴充。只要將新的 過漉器加㈣前組中，可驗的影像f線裝置便能執行新的參 像處理。當想要在-個處理階段中以更多的過濾、器處理影像時，/籲 則可擴充新的過濾器組以及對應之陣列控制器。 而當可選徑的影像管線裝置的實體緩衝暫存單元犯2不敷使 用時’亦可例如添加新的線緩衝器以加大實體緩衝暫存單元422 的總容量’或是將舊的實體緩衝暫存單元奶替換為容量更大的 貫體緩衝暫存單元422。如上㈣，陣顺繼能喃彳分配位址 的方式將實體緩衝暫存單元422配置為邏輯緩衝暫存單城，再 將邏輯緩衝暫存私提供給韻ϋ錢。換句話說，猶器透過 陣，控制n以存取實體_暫存單元422。因此的實體緩衝暫 存单几422均能透過邏輯緩衝暫存單元提供給所有的過濾、器，十 分地簡便。 月ί…、第8圖」’其係為根據本發明一實施範例之緩衝切換 盗的架構示意圖。實體記憶體配置42中具有緩衝切換器424、實 體缓，存單元422a、棚以及徽。Μ過濾器恤以及祕 過滤器可分別透過第-陣列控制器44以及第二陣列控制器 20 201133390 46 ’以讀寫線存取實體缓衝暫存單元422a、422b以及422c。緩衝 切換器424則係簡單地依據第一陣列控制器44以及第二陣列控制 器46所分配的位址，切換讀寫線與實體緩衝暫存單元422a、422b 以及422c之間的連結。如此一來，位於不同過濾器組之7χ7過濾 益56a以及3χ3過濾器56b便能夠同時存取對應之邏輯緩衝暫存 單元。也就是說，緩衝切換器424更增加了實體緩衝暫存單元422 的讀寫頻寬。 其中讀寫線可以例如是16位元或是32位元的匯流排線 • (bus)，可依頻寬需求配置。例如3x3過濾器56b可能僅需使用 16位兀的匯流排線，而7χ7過濾器5知則需要使用％位元的匯流 排線。 此外’當只用 .個實體緩衝暫存單元422提供給多個陣列控 ^器時亦可於可選徑的影線裝置巾配置_域器424。例如 虽發生第-陣顺制器44以及第二陣列控制器％同時要對實體 緩衝暫存單it 422發出要求㈣卿)之特殊情況時，緩衝切換器 =4此夠擔任仲裁的角色’去分配要先讓哪一個陣列控制器進行存 。綜上所述’雜本翻之可選徑的祕管魏置 各過濾器組中的過濾器處理影像。可選徑的影像管 …置將貫體_暫存早元集中於影像管線控制器中管理 ^緩衝^崎她_鳴_=== k衝暫存早疋配置為邏輯緩衝暫存單元的機 21 201133390 限制。再象器並不會對實體緩衝暫存單元造成 整個可選徑的影：裝，便能簡單的擴張 器，像處理時可由過㈣組中選«要的猶 以及陣歹伊制哭^。且錯著新增過遽器或是成對的過遽器組 雖缺纽° 触易地擴充可選徑的影像管線裝置。 …务明以前述之較佳實施例揭露如上，秋 疋本發明，任何孰羽 〜、尤非用以限 内，當可作此，:=#者，在不脫離本發明之精神和範圍 本說明” 飾，因此本發日狀專娜護範圍須視 曰斤附之申請專利範圍所界定者為準。 【圖式簡單說明】 1置^2據本發㈣一實施範例之可選徑的影像管線 示意Ϊ ;2Α圖係為根據本發明一實施範例之圖框基準的掃描方式 示意^ ;2Β圖係為根據本發明一實施範例之磁磚基準的掃描方式 酉己置圖圖係為根據本發明一實施範例之實體緩衝暫存單元之 第3Β圖係為根據本發明一實範 元之配置示意圖； 匕弟―邏輯緩衝暫存單 二：根據本發明另一實施範例之第-邏輯緩衝暫存 22 201133390 邏輯緩衝暫存 第3D圖係為根據本發明又一實施範例之第 單元之配置示意圖； 配置圖料根據本發明-實施範例之實體緩騎存單元之 _弟犯圖係為根據本發明一實施範例之第一 το之配置示;|圖； ㈣智存早 一第4C圖係為根據本發明另一實施範例之第一 早7〇之配奸冑目； 第4D圖係為根據本發明又一實施範例之第— 單元之配i示_ ; 卿^存 第5圖係為根據本發明之第二實施範例之可選徑的 震置的架構示意圖； 第6圖係為根據本發明之第三實施範例之可選獲的 裝置的架構示意目； Ί謂 第7圖係為根據本發明第四實施範例之可選徑的影像管 置的架構示意圖；以及 ' ' 第8圖係為根據本發明一實施範例之緩衝切換器的架 土 圖。 “再不思 【主要元件符號說明】 20 外部記憶體 30 直接記憶體存取器 40 影像管線控制器 23 201133390 42 實體記憶體配置 422，422a，422b，422c 實體緩衝暫存單元 423，423a，423b，423c，423d 第一邏輯緩衝暫存單元 424 44 46 48 50 52 54 55 56aFor another example, when the whispering turns the wei to _RGB, the optional green line device only performs the RGB phase of the image. 2 201133390 says that the 'optional diameter image pipeline device can close the frame reference. When the scan mode accesses the image and only uses the 3x3 filters 56b, 56d, 56f and the corresponding image processing video frame, the image pipeline device of the optional path only uses the logical buffer temporary storage unit 423 and the second logical buffer. The temporary storage unit and the third logical buffer temporary storage unit process the image (each of the video's') and bribe the processed image to the external memory. It is worthwhile to pick up the gentleman's structure of the image tube material with the above-mentioned optional diameter, and the image tube position of the optional diameter (4) is very (4). As long as the new filter is added to the (four) front group, the verifiable image f-line device can perform new image processing. When you want to process images with more filters and processes in one processing stage, /click to expand the new filter group and the corresponding array controller. When the physical buffer temporary storage unit of the image path device of the optional path is used 2, it is also possible to add a new line buffer to increase the total capacity of the physical buffer temporary storage unit 422 or to use the old entity. The buffer temporary storage unit milk is replaced with a larger capacity internal buffer temporary storage unit 422. As shown in (4) above, the physical buffer temporary storage unit 422 is configured as a logical buffer temporary storage unit, and the logical buffer temporary storage is provided to the rhyme. In other words, the semaphore passes through the array and controls n to access the entity_temporary unit 422. Therefore, the physical buffer temporary storage list 422 can be provided to all the filters and devices through the logical buffer temporary storage unit, which is simple and convenient. </ RTI> Fig. 8 is a schematic diagram of a buffer switching pirate according to an embodiment of the present invention. The physical memory configuration 42 has a buffer switch 424, a solid buffer, a storage unit 422a, a shed, and an emblem. The Μ filter shirt and the secret filter can access the physical buffer temporary storage units 422a, 422b, and 422c through the first array controller 44 and the second array controller 20 201133390 46 '. The buffer switch 424 simply switches the link between the read/write line and the physical buffer temporary storage units 422a, 422b, and 422c according to the address assigned by the first array controller 44 and the second array controller 46. In this way, the 7χ7 filter benefit 56a and the 3χ3 filter 56b located in different filter groups can simultaneously access the corresponding logical buffer temporary storage unit. That is to say, the buffer switch 424 further increases the read/write bandwidth of the physical buffer temporary storage unit 422. The read/write line can be, for example, a 16-bit or 32-bit bus bar (bus), which can be configured according to bandwidth requirements. For example, the 3x3 filter 56b may only need to use a 16-bit bus line, while the 7χ7 filter 5 requires a % bit bus line. In addition, when only one physical buffer buffer unit 422 is provided to a plurality of array controllers, the field device 424 can also be configured in the optional path. For example, although the first-stage sequencer 44 and the second array controller % have to issue a special request for the physical buffer temporary storage unit it 422 (four), the buffer switcher=4 is sufficient for the role of arbitration to allocate Which array controller should be saved first. In summary, the filter of the filter set in each filter group is processed. Optional path image tube... Set the body _ temporary storage early in the image pipeline controller management ^ buffer ^ saki her _ _ = = = k rush temporary storage early configuration as a logical buffer temporary storage unit 21 201133390 Limitation. The re-imager does not cause the entire buffer path of the physical buffer temporary storage unit: it can be simply expanded, and the process can be selected from the (4) group and the desired. And the wrong addition of the 遽 or the pair of 遽 组 虽 ° ° ° ° ° ° ° 扩充 扩充 扩充 扩充 扩充 扩充 扩充 扩充 扩充 扩充 扩充 扩充 扩充 扩充 扩充It is to be noted that the above-described preferred embodiments disclose the above, and the present invention, any of the 孰 〜 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 孰 孰 孰 孰 孰 孰 孰 孰 孰 孰 孰Note: The scope of this issue shall be subject to the definition of the patent application scope of the application. [Simplified description of the diagram] 1 set 2 according to the present invention (4) The image pipeline is shown in FIG. 2 is a scanning mode schematic diagram of a frame reference according to an embodiment of the present invention; FIG. 2 is a scanning method of a tile reference according to an embodiment of the present invention. The third diagram of the physical buffer temporary storage unit according to an embodiment of the present invention is a schematic diagram of the configuration of a real model according to the present invention; the younger-logical buffer temporary storage list 2: the first logical buffer according to another embodiment of the present invention Storage 22 201133390 Logic buffer temporary storage 3D is a schematic diagram of the configuration of the first unit according to another embodiment of the present invention; the configuration map according to the present invention - the embodiment of the physical slow-moving unit is based on Invention The configuration of the first το of the example; | Fig.; (4) The first 4C of the present invention is the first episode of the first morning according to another embodiment of the present invention; the fourth figure is based on the present invention. The first embodiment of the present invention is a schematic diagram of the arrangement of the optional path according to the second embodiment of the present invention; FIG. 6 is a schematic diagram of the present invention according to the present invention. The schematic diagram of the optional device of the third embodiment is shown in FIG. 7 is a schematic diagram of the structure of the image tube of the optional path according to the fourth embodiment of the present invention; and ' '8 is based on this An earth-moving diagram of a buffer switcher according to an embodiment of the present invention. "Nothing to think about [Major component symbol description] 20 External memory 30 Direct memory accessor 40 Image pipeline controller 23 201133390 42 Physical memory configuration 422, 422a, 422b , 422c physical buffer temporary storage unit 423, 423a, 423b, 423c, 423d first logical buffer temporary storage unit 424 44 46 48 50 52 54 55 56a
緩衝切換器 第一陣列控制器 第二陣列控制器 第三陣列控制器 過濾器層 第一過濾器組 第二過濾器組 第三過濾器組 7x7過滤器 56b，56c，56d，56f，56g 3χ3 過濾、器 56e 5x5過濾器Buffer Switcher First Array Controller Second Array Controller Third Array Controller Filter Layer First Filter Group Second Filter Group Third Filter Group 7x7 Filters 56b, 56c, 56d, 56f, 56g 3χ3 Filter , 56e 5x5 filter
58 旁通線 60 掃描圖框 62 掃描子圖框 2458 Bypass line 60 Scanning frame 62 Scanning sub-frame 24