201110248 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種製造半導體晶片封裝模組之方法，特 別係關於-種不需要提供具有預形成晶片接收槽來接收晶 片之基板，而可將晶片安置於晶片載體之製造半導體晶片 封裝模組之方法。 【先前技術】 將積體電路晶片安置於印刷電路板的技術，傳統上都會 到晶片載體。在此技術中’積體電路晶片係被提供電性 用 接觸墊，而晶片係被安置於晶片載體上晶片載體可包含 扇出式(fan out)電路’傳統上為多層電路，形成於介電材 料上。晶體載體的上方安置有晶片，以及適合藉由錫球將 晶片連接於印刷電路板的球形陣列。在某些例子中，晶片 載體可載有一個以上之晶片 晶片載體彼此連接。 若有需要，該等晶片可藉由 美國公開之專利申請案第2〇〇8/〇197469號及第 2_/〇13_2號皆提供了—種將積 載體的方法。在此方法中’積體電路晶片(未封裝之晶粒) 的背面係被施加點著材料，以藉由拾取-放置精密對準系 統接合至基板之預形成晶片接收槽内。為了確保積體電路 晶片結合至基板，後續通常會再進行真空固化。接著，彈 性介電層會填人於積體電路晶片與槽之間的空隙，接 抽真空以除去氣泡。 雖然上述方法可減少封裝的厚度並增加通量，然 1416I9.doc 201110248 背面需施加黏著材料，且需要抽真空 0曰片固定於基 板，不會因後續的彈性介觉層之充填有―絲的移動。此 外，為了去除彈性介電層充填時可能產生的氣泡 行抽真空程序。 也黑進 因此，便冀望有-種製造半導體晶片封裝模組的方法， 能夠有較佳的生產效率，但不會犧牲掉晶片封裝模组 低尺寸的優點。 【發明内容】 本發明係提供—種製造半導體晶片封裝模組的方法。在 =法中，係提供一晶片載體，其包含具有對準標記及載 體膜形成於其上的基板。晶片 子口取_放置精密對準201110248 VI. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a semiconductor chip package module, and more particularly to a substrate that does not need to provide a pre-formed wafer receiving groove for receiving a wafer, but A method of fabricating a semiconductor wafer package module in which a wafer is placed on a wafer carrier. [Prior Art] The technique of placing an integrated circuit chip on a printed circuit board has conventionally been to a wafer carrier. In this technique, an 'integrated circuit chip is provided with an electrical contact pad, and the wafer is placed on the wafer carrier. The wafer carrier can include a fan out circuit' which is conventionally a multilayer circuit formed in a dielectric On the material. A wafer is placed over the crystal carrier, and a spherical array suitable for attaching the wafer to the printed circuit board by solder balls. In some examples, the wafer carrier can carry more than one wafer wafer carrier to each other. If necessary, the wafers can be provided by the methods disclosed in U.S. Patent Application Serial No. 2/8/1974, and No. 2//13. In this method, the back side of the integrated circuit wafer (unpackaged die) is applied with a material to be bonded into the preformed wafer receiving trench of the substrate by a pick-and-place precision alignment system. In order to ensure that the integrated circuit wafer is bonded to the substrate, vacuum curing is usually performed later. Next, the elastic dielectric layer fills the gap between the integrated circuit chip and the trench, and a vacuum is applied to remove the air bubbles. Although the above method can reduce the thickness of the package and increase the flux, the adhesive material needs to be applied on the back surface of the 1416I9.doc 201110248, and the vacuum plate is required to be fixed on the substrate, and the subsequent elastic layer is not filled with silk. mobile. In addition, in order to remove the bubble generation process which may occur when the elastic dielectric layer is filled. Therefore, it is also possible to have a method of manufacturing a semiconductor chip package module, which can have better production efficiency without sacrificing the advantages of the low size of the chip package module. SUMMARY OF THE INVENTION The present invention provides a method of fabricating a semiconductor wafer package module. In the = method, a wafer carrier is provided which includes a substrate having alignment marks and a carrier film formed thereon. Wafer sub-port _ placement precision alignment
尔統置放於載體膜上。接著，B 片係被壓入至該载體膜， 的頂面至少大致上與該載體膜的頂面共平面的程 : 广固化以使該载體膜完全固化。前述步驟完成 :二Γ供電性連接(觉路)的步驟，其可包括：形成 "電層於5亥晶片與該載體. 膜上’形成至少-開口於該 =介電層以露出至少該晶片之一部份；形成至少一再分 re-dlstnbut1〇n Iayer, 該;Γ形成第二介電層於該再分佈層及㈣ 成至夕％ 口於該第二介電層以露出至少 4份的該再分佈層；月彡 ，〆成導電金屬（包含球下金屬層， UBM)於開口中以經由 由再刀佈層提供電性連接至該晶片。 右需要’可進一步逸杆主 步驟。若將本發明古内連接製程及其它方法 法用於在單一載體膜上同時處理多個 I41619.doc 201110248 a曰片’可另包含切片步驟以將多個晶片分成單— 在形成導電金屬後，需要封裝、其它内連接製程及其它方 v驟此切片步驟會在該等步驟後實施。 根據本發明方择^ 』 土板不需要晶片接收槽。因此，介電 材料不需要充填至晶片與槽 /、價壁間的空間，因而不需要後續 真工程序以去除充填彈性介電材料過程中可能產生的 氣泡。其結果為，本發明方法能夠更有生產效率，= :彈性介電材料充填至槽中所產生的氣泡，其產率可提 升。 【實施方式】 :下實施例將對本發明作進一步之說明唯非用以限制 圍’任何熟悉本發明技術領域者，在不違背本 發明之精神下所得以達成之修飾及變化，均屬本發明之範 圍。 以下不同貫施例中 4 — 之特徵為申睛專利範圍中引述的元件 的貫例’且在不偏離申喑衰南丨铲阁& & τ明專利範圍的情況下，可彼此結合 為貫施例。 圖1Α至11 ’係顯示本發明一眚# / | 赞月貫把例之各種操作及其順 序。 :圖以所不，係提供晶片載體，其包含基板2及形成於 基板2上之載體膜4。基板2可由具有低熱膨脹隸（C寧 有機、玻璃、陶瓷、或$夕材 ^材枓、·且成。較佳地，基板2為具 有咼玻璃轉移溫度之有她罝 ^ ^ ^ 有機基板，例如環氧樹脂型的FR5或 雙馬來醯亞胺三嗓·」 . imide triazjne，BT)型基板。基 141619.doc 201110248 可讓物件在厂’Γ 為矩形’如面板。載體膜4應由 2物件在麗力及/或加熱下壓入，且可進—步藉由加敎 ^化步驟來硬化之材料所組成（如由模製化合物組成之 L、）。例如，載體膜4可由聚對笨二甲酸乙二酯（pFT)、 聚四氟乙婦(鐵氟龍)、聚酿亞胺或環氧 ㈣膜4的厚度係根據要被壓人於其中的晶片厚度^決 疋。例如，若晶片的厚度為約1〇〇微米，載體膜的厚度庫 大於100微米》 〜 在圖中’晶片6係被放置於載體膜4上。晶片6可以以 所需的位置放置或分佈在載體膜4上。為了達到此目的， 本發明領域中任何已知的技術皆可使用’例如，拾取·放 置對準系統。在一實施例令’黏合機，如精密對準之黏晶 機，可用來將晶片6點合至載體膜4。在—實施例中，黏著 材料(如膠帶)可施加於晶片6的背面或施加於載體膜4想要 的位置上’以使該晶片6連結至該載體膜4。若係多個晶片 進行處理’可使用具有對準圖樣於其上之對準工具（板）。 圖樣膠知可印刷於工具上（用於黏晶粒的表面），接著藉由 ❹具有覆晶（flip chip)功能之拾放精密對準系統將晶片 們以想要的間隔重分佈在工具上’再以圖樣膠將晶片黏在 工具上。接續，晶片黏著材料可印在晶片背面。黏合機接 著可用於將載體膜4結合至晶片的背面。 晶片6，通常為電子元件，為半導體晶粒，其有時會稱 作積體電路晶片或主動元件。在一些實施例中，晶片以 另一種形式的電子元件，如被動元件，例如電阻器、電容 Ϊ41619.doc 201110248 器或電感器。 當晶片6放置於載體膜4上後，如圖lc所示，晶片6會被 壓入至載體膜4,至晶片6的頂面係至少大致上與載體膜4 的表面共平面。晶片6的相當部份係埋入於該載體膜4中。 晶片6的表面可高於載體膜4的表面之程度係根據晶片^的 厚度決定。例如，晶片6的頂面可高於載體膜4的表面約晶 片6厚度的約0%至2〇%，較佳為晶片6厚度的約ι〇%，再較 佳為晶片6厚度的約5%。在一實施例中，晶片6的頂面與 載體膜4表面的差不超過約3微米。此步驟係可藉由壓縮 機，例如熱壓縮機、真空層壓機或晶圓黏合機在適當的壓 力及視情況地加熱上進行。施加的壓力及溫度係根據载體 膜4所使用的材料而定。例如，在i 〇〇至丨5〇〇c的溫度設定 及0.6托的腔室真空壓力設定下，晶片係可成功地藉由施 加1公斤/平方公分的附加壓力6〇秒埋入典型的載體膜。 在晶片6被埋入載體膜4後，載體膜4可被固化以硬化。 在一實施例中’載體膜4可在約250°C固化。對於環氧樹脂 為基材之載體膜’其固化溫度通常介於1〇〇至20〇(>c ;對於 聚醯亞胺為基材之載體膜’其固化溫度通常介於2〇〇至 370°C ;對於丙烯酸類為基材之載體膜，其固化溫度通常 介於100至250°C。 接著，可進行一系列的步驟以提供電性連接（電路）至該 晶片6。如圖1D至11所示，其步驟可包括但不限於：形成 第一介電層8於該晶片6及該載體膜4上；形成開口 10於該 第一介電層8以露出該晶片6的至少一部份；形成再分佈層 1416I9.doc 201110248 12於開口 ι〇中；形成第二介電層14於該再分佈層12、開口 10及第一介電層8上；形成開口16於該第二介電層14以露 出該再分佈層12的至少一部份；形成接觸墊18(球下金屬 層’ UBM)於該再分佈層]2上；以及形成導電金屬2〇於該 接觸要18上。 本發明領域中任何已知的技術皆可利用以實施上述步 驟。例如’介電層8及14可藉由旋轉塗佈或印刷，及在需 要時可配合後續的熱固化製程來形成。微影與触刻製程可 用來在介電層8及14中形成開口 10及16。濺鍍或電鍍製程 與微影及蝕刻製程一起可在開口 1〇及16形成圖案化的再分 佈層12及接觸墊18。導電金屬2〇可包含錫球或錫塊。在一 實施例中，錫球可藉由球置放或錫糊狀物印刷技術形成接 觸於該接觸墊18。此步驟可進一步包含再流動步驟以形成 錫球。 用於第一介電層8之介電材料應具有與載體膜4相容或類 似之物理性質，或該兩者之材料的選擇應使第一介電層8 與載體膜4可緊密地彼此黏合而不會在後續的操作中剝 離。舉例而言，介電材料應與载體膜4的材料具有接近的 熱膨脹係數（CTE)。介電材料可包含聚對苯二甲酸乙二酯 (PET)、聚四氟乙烯（鐵氟龍）、聚醯亞胺或環氧樹脂型材 料。再分佈層12的材料可包含可藉由濺鍍形成之邊或 Ti/Al/Ti，及可藉由電錢形成之Cu/Ai^Cu/Ni/Au。該接觸 墊18可包含Au、A1或Cu或其組合。該導電金屬2〇可為錫 塊或錫球，由此領域t已知的材料組成。舉例而言，導電 I416l9.doc 201110248 金屬 20 可包含 Al/Niv/Cu、Ti/NiV/Cu、TiW/Au 亦 Ti/Cu/Ni。 & —若有需要’在導電金屬形成後，可進一步實施封裝及其 匕内連接製程以及其它處理步驟。若本發明係用於在單一 載體膜上同時處理多個晶片，可另外包含切割步驟以將多 個晶片分成個別的晶片。若在導電金屬形成後，有需要進 -步實施封袭及其它内連接製程以及其它處理步驟 步驟會在該等步驟實施後進行。 ° 在導電金屬形成後，可進行測 疋仃判忒。右早一载體膜上係處 理多個晶片，多個晶片可名丨 曰乃J在測试後再切割為個別的晶片 如此領域中所了解，本發明 方法可應用於包含多晶片的 半導體日日片模組或單一載體膜 的多個 僅,4不兩個晶片，根據本發 知月的方法也可應用於包含單一 晶片或兩個晶片以上的半導體晶片模組。 以下申請專利範圍係用以界定 t 介疋本發明之合理保護範圍。 然應明瞭者，技藝人士其t 士义 …目 發明之揭示所可達成之種種 r , 个赞明合理之保護範圍。 【圖式簡單綱】 第1A至II圖為構成過程中之丰 導體日日片封裝模組之橫截 面’顯不根據本發明之方法步驟。 圖中相對應的元件係以相同的桿 ,,^ 』加琥表不。圖尹的尺寸並 非根據實際尺寸。 【主要元件符號說明】 2 基板 14I6I9.doc 201110248 4 載體膜 6 晶片 8 第一介電層 10 開口 12 再分佈層 14 第二介電層 16 開口 18 接觸墊 20 導電金屬 14l619.docThe system is placed on the carrier film. Next, the B-sheet is pressed into the carrier film, the top surface of which is at least substantially coplanar with the top surface of the carrier film: broadly cured to completely cure the carrier film. The foregoing steps are completed: a step of supplying a power connection (sensing path), which may include: forming an electrical layer on the 5 kPa wafer and the carrier. Forming at least - opening the dielectric layer to expose at least the film Forming at least one portion of the wafer; forming a second dielectric layer on the redistribution layer and (iv) forming a second dielectric layer on the second dielectric layer to expose at least 4 portions The redistribution layer; the germanium, the conductive metal (including the under-ball metal layer, UBM) is in the opening to provide electrical connection to the wafer via the re-blade layer. Right need 'can further break the main step. If the inventive intra-ligation process and other methods are used to simultaneously process a plurality of I41619.doc 201110248 a slabs can be further included in a single carrier film to divide a plurality of wafers into single sheets - after forming a conductive metal, The package, other internal connection processes, and other steps will be performed after these steps. According to the invention, the slab does not require a wafer receiving groove. Therefore, the dielectric material does not need to be filled into the space between the wafer and the trench/valence wall, and thus no subsequent procedural procedures are required to remove bubbles that may be generated during the filling of the elastic dielectric material. As a result, the method of the present invention can be more productive, =: the bubble generated by the filling of the elastic dielectric material into the tank can be improved in productivity. The following examples are intended to be illustrative of the present invention and are not intended to limit the scope of the invention, and the invention may be practiced without departing from the spirit and scope of the invention. The scope. In the following different examples, 4 - is characterized by the example of the components quoted in the scope of the patent application, and can be combined with each other without deviating from the scope of the application of the smashing shovel && Throughout the case. Figures 1A through 11' show the various operations of the present invention and the sequence thereof. The figure is provided as a wafer carrier comprising a substrate 2 and a carrier film 4 formed on the substrate 2. The substrate 2 may have a low thermal expansion (C-Ning, glass, ceramic, or ceramic material). Preferably, the substrate 2 has an organic substrate having a glass transition temperature. For example, an epoxy resin type FR5 or a bismaleimide triazole "imide triazjne, BT) type substrate. Base 141619.doc 201110248 allows objects to be 'squared' at the factory, such as panels. The carrier film 4 should be pressed by 2 articles under Lili and/or heat, and can be further composed of a material hardened by a ruthenium addition step (e.g., L consisting of a molding compound). For example, the carrier film 4 may be made of a polyethylene terephthalate (pFT), a polytetrafluoroethylene (Teflon), a poly-imine or an epoxy (tetra) film 4 according to the thickness to be pressed therein. The thickness of the wafer is determined. For example, if the thickness of the wafer is about 1 Å, the thickness of the carrier film is greater than 100 μm. 〜 In the figure, the wafer 6 is placed on the carrier film 4. The wafer 6 can be placed or distributed on the carrier film 4 at a desired position. To this end, any known technique in the art of the invention can be used, e.g., a pick and place alignment system. In an embodiment, a bonding machine, such as a precision aligned die bonder, can be used to bond wafer 6 to carrier film 4. In an embodiment, an adhesive material (e.g., tape) may be applied to the back side of the wafer 6 or to the desired position of the carrier film 4 to bond the wafer 6 to the carrier film 4. If multiple wafers are processed, an alignment tool (plate) having an alignment pattern thereon can be used. The pattern gel can be printed on the tool (for the surface of the bonded die), and then the wafers are redistributed on the tool at desired intervals by means of a pick-and-place precision alignment system with flip chip function. 'Add the wafer to the tool with a pattern glue. Successively, the wafer adhesive material can be printed on the back side of the wafer. The bonding machine can then be used to bond the carrier film 4 to the back side of the wafer. The wafer 6, typically an electronic component, is a semiconductor die, which is sometimes referred to as an integrated circuit die or active component. In some embodiments, the wafer is in another form of electronic component, such as a passive component, such as a resistor, capacitor Ϊ41619.doc 201110248 or an inductor. After the wafer 6 is placed on the carrier film 4, as shown in Figure 1c, the wafer 6 is pressed into the carrier film 4, and the top surface of the wafer 6 is at least substantially coplanar with the surface of the carrier film 4. A substantial portion of the wafer 6 is embedded in the carrier film 4. The extent to which the surface of the wafer 6 can be higher than the surface of the carrier film 4 is determined by the thickness of the wafer. For example, the top surface of the wafer 6 may be higher than the surface of the carrier film 4 by about 0% to 2% by weight of the wafer 6, preferably about ι% of the thickness of the wafer 6, and more preferably about 5 of the thickness of the wafer 6. %. In one embodiment, the difference between the top surface of the wafer 6 and the surface of the carrier film 4 is no more than about 3 microns. This step can be carried out by a compressor, such as a thermal compressor, a vacuum laminator or a wafer bonder, under appropriate pressure and optionally heating. The pressure and temperature applied are based on the materials used for the carrier film 4. For example, at a temperature setting of i 〇〇 to 丨 5 〇〇 c and a chamber vacuum pressure setting of 0.6 Torr, the wafer system can be successfully embedded in a typical carrier by applying an additional pressure of 1 kg/cm 2 for 6 sec. membrane. After the wafer 6 is buried in the carrier film 4, the carrier film 4 can be cured to be hardened. In one embodiment, the carrier film 4 can be cured at about 250 °C. For an epoxy resin-based carrier film, the curing temperature is usually between 1 〇〇 and 20 〇 (>c; for a polyimide-based substrate carrier film), the curing temperature is usually between 2 〇〇 and 370 ° C; for acrylic substrate-based carrier film, the curing temperature is usually between 100 and 250 ° C. Next, a series of steps can be performed to provide an electrical connection (circuit) to the wafer 6. As shown in Figure 1D The steps may include, but are not limited to, forming a first dielectric layer 8 on the wafer 6 and the carrier film 4; forming an opening 10 in the first dielectric layer 8 to expose at least one of the wafers 6. Forming a redistribution layer 1416I9.doc 201110248 12 in the opening ι; forming a second dielectric layer 14 on the redistribution layer 12, the opening 10 and the first dielectric layer 8; forming an opening 16 in the second Dielectric layer 14 to expose at least a portion of the redistribution layer 12; forming a contact pad 18 (sub-ball metal layer ' UBM) on the redistribution layer 2; and forming a conductive metal 2 on the contact 18 Any of the techniques known in the art can be utilized to implement the above steps. For example, 'dielectric layers 8 and 14 can be borrowed. It can be formed by spin coating or printing, and if necessary, with a subsequent thermal curing process. The lithography and etch process can be used to form openings 10 and 16 in dielectric layers 8 and 14. Sputter or electroplating processes and micro The shadow and etch processes together form a patterned redistribution layer 12 and contact pads 18 at openings 1 and 16. The conductive metal 2 can comprise solder balls or tin bumps. In one embodiment, the solder balls can be placed by balls A release or tin paste printing technique is formed to contact the contact pad 18. This step may further comprise a reflow step to form a solder ball. The dielectric material for the first dielectric layer 8 should have compatibility with the carrier film 4 or A similar physical property, or a combination of the two, should be such that the first dielectric layer 8 and the carrier film 4 can be tightly bonded to each other without being peeled off in subsequent operations. For example, the dielectric material should be loaded with The material of the body film 4 has a close coefficient of thermal expansion (CTE). The dielectric material may comprise polyethylene terephthalate (PET), polytetrafluoroethylene (Teflon), polythenimine or epoxy resin. Material. The material of redistribution layer 12 may comprise a material that can be formed by sputtering Side or Ti/Al/Ti, and Cu/Ai^Cu/Ni/Au which can be formed by electricity money. The contact pad 18 may comprise Au, A1 or Cu or a combination thereof. The conductive metal 2〇 may be a tin block Or a solder ball, which is composed of a material known in the art. For example, the conductive material I416l9.doc 201110248 metal 20 may comprise Al/Niv/Cu, Ti/NiV/Cu, TiW/Au and Ti/Cu/Ni. - If necessary, after the formation of the conductive metal, the package and its internal connection process and other processing steps can be further implemented. If the invention is used to simultaneously process a plurality of wafers on a single carrier film, an additional cutting step can be included Multiple wafers are divided into individual wafers. If the conductive metal is formed, it is necessary to carry out the stepping and other internal joining processes and other processing steps, which are performed after the steps are implemented. ° After the conductive metal is formed, the measurement can be performed. A plurality of wafers are processed on the right carrier film, and a plurality of wafers can be diced into individual wafers after testing. As is known in the art, the method of the present invention can be applied to semiconductor days including multi-wafers. A plurality of wafer modules or a single carrier film may be applied to a semiconductor wafer module including a single wafer or more than two wafers according to the method of the present invention. The following patent claims are intended to define a reasonable scope of the invention. However, it should be understood that the skilled person has a variety of r that can be achieved by the disclosure of the invention. [Simple diagram of the drawing] Figs. 1A to II show the cross section of the conductor day-day package module in the process of forming, which is not according to the method steps of the present invention. The corresponding components in the figure are the same rod, and ^ 』 The size of Tu Yin is not based on the actual size. [Main component symbol description] 2 Substrate 14I6I9.doc 201110248 4 Carrier film 6 Wafer 8 First dielectric layer 10 Opening 12 Redistribution layer 14 Second dielectric layer 16 Opening 18 Contact pad 20 Conductive metal 14l619.doc