201039032 六、發明說明： ' 【發明所屬之技術領域】 本發明是有關於一種元件陣列基板，且特別是有關於 一種能應用於顯示面板的主動元件陣列基板。 【先前技術】 隨者科技進步’液晶顯示器（Liquid Crystal Display, LCD)及電漿顯示器（Plasma Display Panel，PDP)等平面 〇 顯示器（flat panel display)已逐漸取代陰極射線管顯示器 (Cathode Ray Tube, CRT )，而成為目前市面上常見的顯示 器’其中又以液晶顯示器為現今顯示器的主流商品。 目前較為普遍的液晶顯示器大多為薄膜電晶體液晶顯 示器（Thin Film Transistor Liquid Crystal Display TFT-LCD )其主要元件包括薄膜電晶體陣列基板、彩色減 光基板、位在薄膜電晶體陣列基板與彩色濾光基板之間的 〇 液晶層以及背光模組’其中薄膜電晶體陣列基板通常需要 經過微影、蝕刻與濺鍍等多道程序來製造，所以薄膜電晶 體陣列基板在製造上需要相當高昂的花費。 因此，對於薄膜電晶體陣列基板，很多製造液晶顯示 器的工廠不僅會提高薄膜電晶體陣列基板的品質，同時更 會盡量降低薄膜電晶體陣列基板在製造過程中發生報麼的 機率，以減少製造成本，增加產品的良率（yield)。 201039032 【發明内容】 - 本發明提供一種主動元件陣列基板，其能應用於顯示 器中。 本發明提出一種主動元件陣列基板，其包括一基板、 一畫素陣列（pixel array )以及一虛晝素群組（dummy pixel assembly)。基板具有一顯示區（display area)與一位於顯 示區旁的非顯示區（non-display area )，而非顯示區具有多 個虛畫素區（dummy pixel region )。晝素陣列配置於顯示 ® 區内，而虛晝素群組配置於非顯示區内，並電性連接晝素 陣列。虛畫素群組包括多個電晶體，而這些電晶體分別配 置於這些虛晝素區内。其中一個虛畫素區内的電晶體的數 量為多個。 在本發明一實施例中，其中一個虛畫素區内的電晶體 的數量與另一個虛晝素區内的電晶體的數量不同。 在本發明一實施例中，各虛畫素區内的電晶體的數量 〇 為多個。 在本發明一實施例中，各虛晝素區内的電晶體的數量 都相同。 在本發明一實施例中，這些電晶體皆為薄膜電晶體。 在本發明一實施例中，上述虛晝素群組更包括多個虛 晝素電極（dummy pixel electrode)。各虛晝素電極配置於 其.中·一個虛晝素區内’並電性連接至少一個電晶體。 在本發明一實施例中，在其中一個虛晝素區内，虛晝 201039032 -素電極所電性連接的電晶體的數量為多個。 ’ 纟本&明—實施例中’上述晝素陣列包括多條掃插線 (scan Hne )、多條資料線（_ π 這些掃描㈣這較料料配置賴㈣心這—Γ畫Γ單 元配置於顯不區内’並電性連接這些掃描線與這些資料線。 在本發明只施例中，這些掃描線延伸至非顯示區， 而虛晝素群組更包括一與這些資料線並排的虛資料線 (dummy data line )。虛資料線位於這些配置在非顯示區内 的掃描線的上方。多個虛晝素區位於虛資料線與其相鄰的 資料線之間’並且被位於非顯示區内的這些掃描線所隔開。 在本發明一實施例中，多個電晶體沿著虛資料線排列。 在本發明-實施例中，這些資料線延伸至非顯示區， 而虛晝素群組更包括一與這些掃描線並排的虛掃描線 (dummy scan line)。虛掃描線位於這些配置在非顯示區内 的資料線的下方。多個虛晝素區位於虛掃描線與其相鄰的 〇 掃描線之間，並且被位於非顯示區内的這些資料線所隔開。 在本發明-實施例中，多個電晶體沿著虛掃插線排列。 綜上所述，本發明的主動元件陣列基板所包括的畫素 陣列可以驅動液晶層内的液晶分子，進而產生影像，故本 發明的主動元件陣列基板能應用於顯示器中。 為讓本發明之上述特徵能更明顯易懂，下文特舉實施 例，並配合所附圖式，作詳細說明如下。 201039032 【實施方式】 - 圖1A是本發明一實施例之主動元件陣列基板的俯視 示意圖。請參閱圖1A，主動元件陣列基板100包括一基板 110、一晝素陣列120以及一虛晝素群組130,其中基板110 可為玻璃基板，並可具有透光性。基板110具有一顯示區 112與一非顯示區114。非顯示區114位於顯示區112旁， 而顯示區112與非顯示區114皆在基板110的同一表面上。 晝素陣列120與虛晝素群組130皆在基板110的同一 表面上，其中晝素陣列120配置於顯示區112内，而虛晝 素群組130配置於非顯示區114内，並電性連接晝素陣列 120。晝素陣列120包括多條掃描線122、多條資料線124 以及多個晝素單元126。這些描描線122、資料線124以及 這些晝素單元126皆配置顯示區112内，而這些晝素單元 126電性連接這些掃描線122與這些資料線124。 各個晝素單元126包括一電晶體126a以及一電性連接 Ο 電晶體126a的晝素電極126b。這些電晶體126a例如是薄 膜電晶體，並且皆具有閘極（gate )、源極（source )與汲 極（drain )。晝素電極126b可為透明導電層，其材料例如 是銦錫氧化物（Indium Tin Oxide，IT0 )或銦辞氧化物 (Indium Zinc Oxide, IZ0)。 承上述，這些電晶體126a的閘極分別電性連接這些掃 描線122，源極分別電性連接這些資料線124，而汲極分別 電性連接這些晝素電極126b。因此，這些掃描線122可以 7 201039032 'Μ啟或Μ這些電晶體126a’以控制資料線124輸出電壓 ， 給晝素電極126b。如此’液晶層内的液晶分子能夠被這些 晝素電極126b所驅動’以產生影像，故主動元件陣列基板 100可以應用於顯示器中。 其次，晝素陣列120可以更包括多個儲存電容（storage capacitor，Cst) 128。詳細而言，這些晝素電極12补會延伸 至掃描線122的上方，即晝素電極12邰與掃描線122部分 重疊，而晝素電極126b與掃描、線122重疊的部分則形成儲 存電容Π8,如圖1A所示。當資料線124輸出電壓給晝素 電極126b時，儲存電容128可以儲存電能’以維持驅動液 晶分子的電壓。 再者，圖1A所示的這些儲存電容128是架構於掃描線122 上的儲存電容（Cst on gate)，而在其他未繪示的實施例中， 儲存電容128也可以是架構於共用線 (common line)上的儲 存電容（Cst on common)。另外，就結構而言，這些儲存電 〇 容128可以是金屬層/絕緣層/銦錫氧化物層（metal / insulator / ITO, Mil)結構的儲存電容，或是金屬層/絕緣層/金屬層（metai / insulator / metal，MIM )結構的儲存電容。 圖1B是圖1A中的主動元件陣列基板的局部放大示意 圖。請參閱圖1A與圖1B，非顯示區114具有多個虛晝素 區114a，而虛晝素群組13〇包括多個電晶體132，其中這 些電晶體132分別配置於這些虛晝素區U4a内，而各個虛 畫素區114a内的電晶體132的數量為至少一個。 201039032 承上述，在所有的虛晝素區114a中，其中一個虛晝素 區114a内的電晶體132的數量為多個。也就是說，這些虛 晝素區114a其中之一内的電晶體132賴量為二個以上。 在本實施例中，各個虛晝素區U4a内的電晶體的數量 為多個，且可以都相同。以圖1A與圖1B為例，各個虛晝 素區114a内皆含有五個電晶體132。201039032 VI. Description of the invention: 'Technical field to which the invention pertains>> The present invention relates to an element array substrate, and more particularly to an active device array substrate that can be applied to a display panel. [Prior Art] The flat panel display such as Liquid Crystal Display (LCD) and Plasma Display Panel (PDP) has gradually replaced the cathode ray tube display (Cathode Ray Tube, CRT) has become a common display on the market today. Among them, liquid crystal displays are the mainstream products of today's displays. At present, the most common liquid crystal displays are Thin Film Transistor Liquid Crystal Display (TFT-LCD). The main components thereof include a thin film transistor array substrate, a color light-reducing substrate, a thin film transistor array substrate and color filter. The liquid crystal layer between the substrates and the backlight module. The thin film transistor array substrate usually needs to be manufactured by a plurality of processes such as lithography, etching and sputtering, so the thin film transistor array substrate requires a relatively high cost in manufacturing. Therefore, for a thin film transistor array substrate, many factories that manufacture liquid crystal displays not only improve the quality of the thin film transistor array substrate, but also minimize the probability of the thin film transistor array substrate being reported during the manufacturing process, thereby reducing the manufacturing cost. , increase the yield of the product. 201039032 SUMMARY OF THE INVENTION - The present invention provides an active device array substrate that can be applied to a display. The invention provides an active device array substrate comprising a substrate, a pixel array and a dummy pixel assembly. The substrate has a display area and a non-display area adjacent to the display area, and the non-display area has a plurality of dummy pixel regions. The pixel array is configured in the display ® area, and the imaginary group is disposed in the non-display area and electrically connected to the pixel array. The virtual pixel group includes a plurality of transistors, and these transistors are respectively disposed in these imaginary regions. The number of transistors in one of the virtual pixels is plural. In an embodiment of the invention, the number of transistors in one of the imaginary regions is different from the number of transistors in the other imaginary region. In an embodiment of the invention, the number of transistors θ in each of the virtual pixel regions is plural. In an embodiment of the invention, the number of transistors in each imaginary region is the same. In an embodiment of the invention, the transistors are all thin film transistors. In an embodiment of the invention, the imaginary group further includes a plurality of dummy pixel electrodes. Each of the imaginary electrodes is disposed in a imaginary region and is electrically connected to at least one of the transistors. In an embodiment of the invention, the number of transistors electrically connected to the dummy electrode in the one of the virtual regions is one or more. ' 纟本 & Ming - in the embodiment 'the above-mentioned pixel array includes a plurality of scan lines (scan Hne), a plurality of data lines (_ π these scans (four) which is more than the material configuration Disposed in the display area and electrically connected to the scan lines and the data lines. In the embodiment of the invention, the scan lines extend to the non-display area, and the imaginary group further includes a side by side with the data lines. Dummy data line. The virtual data line is located above the scan lines disposed in the non-display area. A plurality of virtual elements are located between the virtual data line and its adjacent data line' and are located in the non-display area. The scan lines in the display area are separated. In an embodiment of the invention, a plurality of transistors are arranged along the dummy data line. In the present invention-embodiment, these data lines extend to the non-display area, and are imaginary The prime group further includes a dummy scan line alongside the scan lines. The virtual scan lines are located below the data lines disposed in the non-display area. The plurality of virtual elements are located on the virtual scan line. Neighboring 〇 scan line between and The data lines located in the non-display area are separated. In the present invention-embodiment, a plurality of transistors are arranged along the dummy sweep line. In summary, the pixels included in the active device array substrate of the present invention are included. The array can drive the liquid crystal molecules in the liquid crystal layer to generate images, so the active device array substrate of the present invention can be applied to the display. In order to make the above features of the present invention more obvious, the following specific embodiments and cooperation 1A is a top plan view of an active device array substrate according to an embodiment of the present invention. Referring to FIG. 1A, the active device array substrate 100 includes a substrate 110 and a substrate. The array 120 and the imaginary group 130, wherein the substrate 110 can be a glass substrate and can be translucent. The substrate 110 has a display area 112 and a non-display area 114. The non-display area 114 is located beside the display area 112. The display area 112 and the non-display area 114 are all on the same surface of the substrate 110. The pixel array 120 and the imaginary group 130 are all on the same surface of the substrate 110, wherein the pixel array 120 is matched In the display area 112, the imaginary group 130 is disposed in the non-display area 114, and is electrically connected to the pixel array 120. The pixel array 120 includes a plurality of scanning lines 122, a plurality of data lines 124, and a plurality of 昼The pixel unit 126. The trace lines 122, the data lines 124, and the pixel units 126 are all disposed in the display area 112, and the pixel units 126 are electrically connected to the scan lines 122 and the data lines 124. Each of the pixel units 126 includes A transistor 126a and a halogen electrode 126b electrically connected to the germanium transistor 126a. The transistors 126a are, for example, thin film transistors, and each has a gate, a source and a drain. The halogen electrode 126b may be a transparent conductive layer made of, for example, Indium Tin Oxide (IT0) or Indium Zinc Oxide (IZ0). In the above, the gates of the transistors 126a are electrically connected to the scan lines 122, the sources are electrically connected to the data lines 124, and the drains are electrically connected to the pixel electrodes 126b. Therefore, these scan lines 122 can be used to control the output voltage of the data line 124 to the halogen electrode 126b. Thus, liquid crystal molecules in the liquid crystal layer can be driven by these halogen electrodes 126b to generate an image, so that the active device array substrate 100 can be applied to a display. Second, the pixel array 120 can further include a plurality of storage capacitors (Cst) 128. In detail, the complement of the halogen electrode 12 extends above the scan line 122, that is, the pixel electrode 12A partially overlaps the scan line 122, and the portion where the pixel electrode 126b overlaps with the scan and the line 122 forms a storage capacitor Π8. , as shown in Figure 1A. When the data line 124 outputs a voltage to the halogen electrode 126b, the storage capacitor 128 can store the electrical energy ' to maintain the voltage of the driving liquid crystal molecules. Moreover, the storage capacitors 128 shown in FIG. 1A are storage capacitors (Cst on gates) on the scan line 122. In other embodiments not shown, the storage capacitors 128 may also be on a common line ( Storage capacitor (Cst on common) on common line). In addition, in terms of structure, the storage capacitors 128 may be metal/insulating/indium-tin oxide (Metal/ insulator/ITO, Mil) structured storage capacitors, or metal/insulation/metal layers. (metai / insulator / metal, MIM) storage capacitors. Fig. 1B is a partially enlarged schematic view of the active device array substrate of Fig. 1A. Referring to FIG. 1A and FIG. 1B, the non-display area 114 has a plurality of imaginary element regions 114a, and the imaginary group 13 〇 includes a plurality of transistors 132, wherein the transistors 132 are respectively disposed in the imaginary element areas U4a. The number of the transistors 132 in each of the virtual pixel regions 114a is at least one. 201039032 In view of the above, in all of the virtual regions 114a, the number of the transistors 132 in one of the imaginary regions 114a is plural. That is to say, the number of transistors 132 in one of these imaginary halogen regions 114a is two or more. In the present embodiment, the number of transistors in each of the imaginary halogen regions U4a is plural and may be the same. Taking FIG. 1A and FIG. 1B as an example, each of the dummy regions 114a contains five transistors 132.
這些掃描線U2與這些資料線m皆延伸至非顯示區 而虛晝素群組13〇可以更包括一虛掃描線⑼與一虛 肓料線136。虛掃描、線134與這些掃描線122並排，並位 於這些配置在非顯示區114内的f料線124的下方，而虛 資料線m與這些資料線124並排，並位於這些配置在= 顯示區114内的掃描線122的上方。 在1B所示的實_巾，對所有的虛晝素區 a而η虛晝素區114a位於虛資料線136盘 ”料線124之間，並且被位於非顯示區 描線m所隔開。另一些虛晝素區U4a則位於^知 與其相鄰的掃描線122之間，並且被 田:34 的這些資料線124所隔開。 Mm 114内 一穴a个印小叼1拖例中， ::包括虛掃描㈣或虛資料 =!描，134而未包括虛資料線叫所❹ 間素UMa皆位於虛掃推線m與其相鄰的掃描線以 且被位於非顯不區114内的這些資料、線m所隔 201039032 ^之，當虛畫素群組130僅包括虛資料線136而未包 括虛掃插線134時，所有的虛晝素區114a皆位於虛資料線 咖與其相鄰的資料線124之間，並且被位於非顯示區u4 内的這些掃描線122所隔開。 由此可知，多個虛晝素區114a可以位於虛掃描線134 與其相鄰的掃描線122之間，並且被位於非顯示區ιΐ4内 =資料線m所隔開，而且多個虛畫素區叫也可以位於The scan lines U2 and the data lines m extend to the non-display area, and the imaginary group 13〇 may further include a virtual scan line (9) and a virtual feed line 136. The dummy scans, lines 134 are juxtaposed with the scan lines 122, and are located below the f-feed lines 124 disposed in the non-display area 114, and the dummy data lines m are juxtaposed with the data lines 124, and are located in the = display area. Above the scan line 122 within 114. In the real towel shown in FIG. 1B, the yttrium region 114a is located between the dummy data lines 136 and the material line 124, and is separated by the non-display area m. Some of the imaginary element areas U4a are located between the scanning lines 122 adjacent to them and are separated by the data lines 124 of the field: 34. In the case of a hole in the Mm 114, a small print 1 is dragged: : including virtual scan (4) or virtual data =! description, 134, but not including the virtual data line, the UMA is located in the virtual scan line m and its adjacent scan line and is located in the non-display area 114. The data and line m are separated by 201039032. When the virtual pixel group 130 includes only the dummy data line 136 and does not include the virtual sweep line 134, all the virtual element areas 114a are located adjacent to the virtual data line. The data lines 124 are separated by the scan lines 122 located in the non-display area u4. It can be seen that the plurality of dummy elements 114a can be located between the dummy scan lines 134 and the scan lines 122 adjacent thereto. And is located in the non-display area ιΐ4 = data line m, and multiple virtual pixel areas can also be located
Ο =料線136與其相鄰的資料線124之間，並且被位於非 ，，、、頁不區114内的掃描線122所隔開。 在本實施例中，對所有的電晶體132而言 Ο Λ 人 . 匕 ^Ο = the feed line 136 is between its adjacent data line 124 and is separated by scan lines 122 located in the non-,,,, page no area 114. In this embodiment, it is 对 对 for all the transistors 132. 匕 ^
1 >6. J ^ 一二电 I 玲沿著虛賁料線136排列，而另一 4b電 線m排列，如圖1A與圖1B-所示^ Γ，畫因素可以僅包括虛掃描線134或虛她 因此’在其他树示的實施例中，所有的電晶體丄 以只沿著虛掃描、線134或虛資料線136排列。 =素群組13G可錢包料做4素電極138。 電極138配置於其中—個虛晝素區u4a内，而. 旦素區114a内含有一個虛晝素電極138，如圖以 =1B所示。因此，這些虛畫素電極i 3 8個別配置於這些 ; = 内。此外，虛晝素電極138⑽料 ;: 電極126b相同。 各個虛晝素電極⑽電性連接至少一個電 而端視單一個虛畫素區114 θ0 ^ Μ所3有的電晶體132 ^ 201039032 量，虛晝素電極138亦可以電性連接多個電晶體m。換 句話說，在其中一個虛晝素區_内，虛畫素電極⑽所 電性連接的電晶體132的數量可以是多個。以圖认以及 圖為例，各個虛畫素電極138電性連接多個電晶體132。 圖2是圖1B中線w的剖面示意圖。為了詳細介紹電 晶體132的結構，以下脾晰人国。 傅以下絲合圖1B與圖2,進行詳細的說 明。請參閱圖與圖2，這些電晶體132可以是一種薄膜 ο 電晶體，其_各個電晶體132包括一源極s、一沒極D、 -閉極G以及-通道層（cha㈣Uayer)c，而主動元件陣 列基板⑽更包括-絕緣層1〇2以及一平坦層—⑽ layer) 104 。 配置於基板11〇上，並電性連接掃描線⑵或 虛拎描線134，而絕緣層1〇2覆蓋閘極G，且可 料絕緣材料所製成。通道層c配置於絕緣層1〇2 I，並 ο 位於閘極G上方。因此’絕緣層1〇2配置在~;極G與通道 層C之間，讓閘極G不會直接與通道層c電性導通。 源極S與沒極D皆配置於通道層c與絕緣層脱上， 其中源極S電性連接資料線124或虛資料線136，而沒極〇 則電性連接虛晝素電極138。平坦層1〇4覆蓋在源極s 二!:Γc上，且可以是由高分子材料所製成。平括 層具有一開口（*) V，而虛畫素電極⑶ 坦層104上，其中虛畫素電極138透 ；” 汲極D。 V而電性連接 11 201039032 - 承上述，閘極G、源極S與汲極D皆可以是金屬層， ^ 而通道層C可以是半導體層，其材料例如是多晶矽（poly silicon )或非晶石夕（amorphous silicon )。此外，在本實施 例中’電晶體132可以更包括一歐姆接觸層（Ohm contact layer) Ο，其配置於源極S與通道層C之間，以及汲極d 與通道層C之間。 在本實施例中，這些電晶體132的通道長度L、通道 寬度W與外觀比實質上可以是彼此相等，其中此外觀比是 〇 指通道寬度W與通道長度L的比值，也就是W/L。當然， 在其他實施例中，其中一個電晶體132的通道長度l、通 道寬度W或外觀比亦可以與另一個電晶體132不同。 圖3是本發明另一實施例之主動元件陣列基板的俯視 示意圖。請參閱圖3,本實施例的主動元件陣列基板2〇〇 與前述實施例的主動元件陣列基板100相似，惟差異在 於.在主動元件陣列基板200中’其中一個虛畫素區H4a 0 内的電晶體132的數量與另一個虛畫素區114a内的電晶體 132的數量不同。 詳細而言’主動元件陣列基板200包括基板11〇、晝 素陣列120以及一虛晝素群組230，其中晝素陣列12〇配 置於顯示區112内’而虛晝素群組230包括多個電晶體 132、虛掃描線134以及虛資料線136。這些電晶體132分 別配置於這些虛晝素區114a内，而各個虛晝素區114a内 所含有的電晶體132的數量不盡相同。 12 201039032 - 以圖3為例，圖3繪示出五個虛晝素區U4a，而各個 - 虛晝素區ll4a内所含有的電晶體132的數量並不相同，例 如有的虛畫素區114a内含有五個電晶體132 ,而有的虛晝 素區114a内含有三個電晶體132。另外，在這些虛畫素= 114a中，有的虛晝素區114a内的所有電晶體132僅沿著虛 資料線136排列，而有的虛晝素區114a内的所有電晶體13^ 則是只沿著虚掃描線134排列，如圖3所示。 ❹ 综上所述，在本發明的主動元件陣列基板中，由於其 中一個虛畫素區内的電晶體的數量為多個，因此，在液晶 顯示器的製造過程中，或是在液晶顯示器運作的時候，當 發生靜電放電（Electrostatic Discharge，ESD )或有突波產 生時’本發明能增加靜電或突波進入至虛畫素區内的機 會，以減少畫素陣列發生損壞的機率。 由此可知’本發明能增加主動元件陣列基板的靜電防 ❹ 護能力’降低主動元件陣列基板在製造過程中發生報廢的 機率，以減少製造成本，增加產品的良率。此外，各個虛 晝素區内的電晶體的數量可以是多個。'如此，本發明可以 有效地增加主動元件陣列基板的靜電防護能力，以更進— 步地增加產品的良率。 雖然本發明以前述實施例揭露如上，然其並非用以限 定本發明，任何熟習相像技藝者，在不脫離本發明之精神 和範圍内，所作更動與潤飾之等效替換’仍為本發明之專 13 201039032 利保護範圍内。 .【圖式簡單說明】 圖1A是本發明一實施例之主動元件陣列基板的俯視示意 圖。 圖1B是圖1A中的主動元件陣列基板的局部放大示意圖。 圖2 是圖1B中線I-Ι的剖面示意圖。 圖3 是本發明另一實施例之主動元件陣列基板的俯視示 意圖。 【主要元件符號說明】 100 、 200 主動元件陣列基板 102 絕緣層 104 平坦層 110 基板 112 顯不區 114 非顯示區 114a 虛晝素區 120 晝素陣列 122 掃描線 124 資料線 126 晝素單元 126a ' 132 電晶體 126b 晝素電極 128 儲存電容 14 201039032 130 、 230 虛晝素群組 134 虛掃描線 136 虛資料線 138 虛晝素電極 C 通道層 D 汲極 G 閘極 L 通道長度 0 歐姆接觸層 S .源極 V 開口 w 通道寬度 151 >6. J ^ One and two electric I Ling are arranged along the virtual material line 136, and the other 4b electric wires m are arranged, as shown in FIG. 1A and FIG. 1B-, the drawing factor may only include the virtual scanning line 134. Or she is thus 'in other illustrated embodiments, all of the transistors are arranged along only the virtual scan, line 134 or virtual data line 136. = Prime group 13G can be made into a 4-cell electrode 138. The electrode 138 is disposed in the imaginary element region u4a, and the dansin region 114a contains a defyanin electrode 138 as shown in =1B. Therefore, these virtual pixel electrodes i 3 8 are individually arranged in these ; Further, the imaginary electrode 138 (10) material;: the electrode 126b is the same. Each of the imaginary electrodes (10) is electrically connected to at least one of the electrodes, and the imaginary electrode 138 can be electrically connected to the plurality of transistors by the amount of the transistor 132 ^ 201039032. m. In other words, the number of the transistors 132 electrically connected to the dummy pixel (10) may be plural in one of the imaginary regions. Taking the figure and the figure as an example, each of the virtual pixel electrodes 138 is electrically connected to the plurality of transistors 132. Figure 2 is a schematic cross-sectional view of line w in Figure 1B. In order to describe in detail the structure of the transistor 132, the following spleen is known. The following is a detailed description of Fig. 1B and Fig. 2 . Referring to FIG. 2 and FIG. 2, the transistors 132 may be a thin film ο transistor, and each of the transistors 132 includes a source s, a gate D, a closed gate G, and a channel layer (cha) Uyer. The active device array substrate (10) further includes an insulating layer 1〇2 and a flat layer (10) layer 104. It is disposed on the substrate 11 and electrically connected to the scan line (2) or the dummy trace 134, and the insulating layer 1〇2 covers the gate G and is made of an insulating material. The channel layer c is disposed on the insulating layer 1〇2 I and is located above the gate G. Therefore, the insulating layer 1〇2 is disposed between the ? pole G and the channel layer C, so that the gate G is not directly electrically connected to the channel layer c. The source S and the immersion D are disposed on the channel layer c and the insulating layer. The source S is electrically connected to the data line 124 or the dummy data line 136, and is not connected to the imaginary electrode 138. The flat layer 1〇4 is overlaid on the source s 2!: Γc, and may be made of a polymer material. The flat layer has an opening (*) V, and the virtual pixel electrode (3) is on the layer 104, wherein the virtual pixel electrode 138 is transparent;" the drain D. V and the electrical connection 11 201039032 - according to the above, the gate G, The source S and the drain D may each be a metal layer, and the channel layer C may be a semiconductor layer, and the material thereof is, for example, poly silicon or amorphous silicon. Further, in the present embodiment, ' The transistor 132 may further include an Ohm contact layer 配置 disposed between the source S and the channel layer C, and between the drain d and the channel layer C. In this embodiment, the transistors The channel length L, the channel width W, and the aspect ratio of 132 may be substantially equal to each other, wherein the aspect ratio is the ratio of the channel width W to the channel length L, that is, W/L. Of course, in other embodiments, The channel length l, the channel width W or the aspect ratio of one of the transistors 132 may be different from the other transistor 132. Fig. 3 is a top plan view of an active device array substrate according to another embodiment of the present invention. Active device array substrate 2 of the embodiment The 〇〇 is similar to the active device array substrate 100 of the foregoing embodiment except that the number of the transistors 132 in one of the dummy pixel regions H4a 0 in the active device array substrate 200 is different from the other dummy pixel region 114a. The number of the transistors 132 is different. In detail, the active device array substrate 200 includes a substrate 11A, a halogen array 120, and a imaginary group 230, wherein the pixel array 12 is disposed in the display region 112. The halogen group 230 includes a plurality of transistors 132, dummy scan lines 134, and dummy data lines 136. These transistors 132 are respectively disposed in the imaginary crystal regions 114a, and the transistors contained in the respective imaginary region 114a are included. The number of 132 is different. 12 201039032 - Taking FIG. 3 as an example, FIG. 3 illustrates five imaginary region U4a, and the number of transistors 132 contained in each imaginary region 1144 is not the same. For example, some of the virtual pixel regions 114a contain five transistors 132, and some of the dummy regions 114a contain three transistors 132. In addition, among these virtual pixels = 114a, some of the virtual regions 114a All of the transistors 132 within the imaginary data line 136 Columns, and all of the transistors 13^ in the imaginary region 114a are arranged only along the dummy scan line 134, as shown in FIG. 3. In summary, in the active device array substrate of the present invention, Since there are a plurality of transistors in one of the virtual pixel regions, when an electrostatic discharge (ESD) or a surge occurs during the manufacture of the liquid crystal display or during operation of the liquid crystal display. When produced, the present invention increases the chance of static or glitch entering the virtual pixel region to reduce the chance of damage to the pixel array. It can be seen that the present invention can increase the electrostatic protection capability of the active device array substrate to reduce the probability of the active device array substrate being scrapped during the manufacturing process, thereby reducing the manufacturing cost and increasing the yield of the product. Further, the number of transistors in each imaginary region may be plural. Thus, the present invention can effectively increase the electrostatic protection capability of the active device array substrate to further increase the yield of the product. While the present invention has been described above in the foregoing embodiments, it is not intended to limit the invention, and the equivalents of the modification and retouching of the present invention are still in the present invention without departing from the spirit and scope of the invention. Specialized 13 201039032 within the scope of protection. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a plan view schematically showing an active device array substrate according to an embodiment of the present invention. FIG. 1B is a partially enlarged schematic view of the active device array substrate of FIG. 1A. Figure 2 is a schematic cross-sectional view of line I-Ι in Figure 1B. Figure 3 is a top plan view of an active device array substrate in accordance with another embodiment of the present invention. [Main component symbol description] 100, 200 active device array substrate 102 insulating layer 104 flat layer 110 substrate 112 display region 114 non-display region 114a imaginary region 120 pixel array 122 scan line 124 data line 126 pixel unit 126a ' 132 transistor 126b halogen electrode 128 storage capacitor 14 201039032 130 , 230 imaginary group 134 virtual scan line 136 virtual data line 138 imaginary electrode C channel layer D drain G gate L channel length 0 ohmic contact layer S Source V opening w channel width 15