200952176 九、發明說明： 【發明所屬之技術領域】 本發明是關於積體電路製作，且特別是關於一種適 用於高電壓操作之半導體裝置及其製造方法。 【先前技術】 近年來，隨著半導體積體電路製造技術的發展，對於 參 形成於單一晶片上之控制器、記憶體、低電壓操作電路以 及1¾電壓操作電路等構件的需求也隨之增加，藉以製作出 更高積集度之單一晶片系統。 於單一晶片系統内，通常採用了如雙擴散金氧半導體 (double-diffused metal oxide semiconductor，DMOS)裝置 以及絕緣閘極雙極性電晶體(IGBT)等高電壓構件，以改善 功率轉換效率並減少電量的損耗。DMOS裝置具有低功率 損耗及高速操作等優點，因而成為高電壓構件應用選擇之 - - r\ DMOS裝置大體分類為橫向型DMOS(lateral DMOS， LDMOS)裝置以及垂直型 DMOS(verticalDMOS，VDMOS) 裝置等兩類。VDMOS裝置的製備通常牽涉到磊晶製程的 使用，而LDMOS裝置的製備則不一定需要使用磊晶製程 可採用標準互補型金氧半導體(CMOS)製程，因此具有較佳 之製程整合性。然而，相較於VDMOS裝置，LDMOS裝 置具有較高之導通電阻（Rds_on)以及需要較大之元件間 距(pitch)。因此隨著單一晶片系統尺寸的縮小趨勢，便需 96-072/T0492A-A41668-TW/Final 6 200952176 要針對LDMOS裝置之高導通電阻及元件間距進行改 善’以提升其應用性。 請參照第1圖，顯示了一種習知水平型雙擴散金氧半 導體(LDMOS)裝置之剖面情形。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit fabrication, and more particularly to a semiconductor device suitable for high voltage operation and a method of fabricating the same. [Prior Art] In recent years, with the development of semiconductor integrated circuit manufacturing technology, there has been an increase in demand for components such as controllers, memories, low voltage operation circuits, and voltage operation circuits formed on a single wafer. In order to produce a single wafer system with higher integration. High-voltage components such as double-diffused metal oxide semiconductor (DMOS) devices and insulated gate bipolar transistors (IGBTs) are commonly used in a single wafer system to improve power conversion efficiency and reduce power consumption. Loss. DMOS devices have the advantages of low power loss and high-speed operation, and thus become the application of high-voltage components. - r\ DMOS devices are generally classified into lateral DMOS (lateral DMOS, LDMOS) devices and vertical DMOS (vertical DMOS, VDMOS) devices. Two types. The fabrication of VDMOS devices typically involves the use of epitaxial processes, while the fabrication of LDMOS devices does not necessarily require the use of epitaxial processes. Standard complementary metal oxide semiconductor (CMOS) processes are available, resulting in better process integration. However, compared to VDMOS devices, LDMOS devices have higher on-resistance (Rds_on) and require larger component pitch. Therefore, as the size of a single wafer system shrinks, 96-072/T0492A-A41668-TW/Final 6 200952176 is required to improve the high on-resistance and component pitch of the LDMOS device to improve its applicability. Referring to Figure 1, a cross-sectional view of a conventional horizontal double diffused gold-oxide semiconductor (LDMOS) device is shown.
如第1圖所不’ LDMOS裝置主要包括·一 P型梦基底 100 ’其一部内設置有一 N型井區1〇2。於N型井區102 與P型石夕基底100交接處之表面則分別設置有一場氧化物 φ (field oxide，FOX)104 ’因而藉由此些場氧化物104而大體 芩義了設置LDMOS裝置之主動區。此些場氧化物1〇4係 藉由習知場氧化物法所形成。位於場氧化物104間内的N 型井區102内則設置有一 P型基體卬0€^)區1〇6,其係形成 於N型井區102之一部内且大體鄰近位相對左侧之場氧化 物104。於P型基體區1〇6内另外設置有一 N-區113、一 N+區114S以及一 P+區116，其中N-區113係為一淺掺雜 區（lightly doped region)，而 P+區 116 係相鄰於 N+區 114S • 且此二區域係為P型基體區106表面所露出以作為源極和 基體之接觸區。於P型基體區106與右側之場氧化物104 間之N型井區1〇2内則另外設置有一 N+區114D，以作為 汲極。介於場氧化物104的N型井區102之表面之一部上 則形成有一閘堆疊物G，以作為一閘極之用，其包括依序 堆疊於N型井區1〇2表面上之閘介電層U0、閘電極1〇8。 於閘堆疊物G内之閘介電層11〇與閘電極ι〇8之對稱侧邊 上則設置有間隔物112。閘堆疊物G在此部分覆蓋j>型基 體區106且覆蓋了 N-區113。 96-072/T0492A-A41668-TW/Final 7 200952176 在此，於第1圖所示之LDMOS裝置中，標號L顯示 了通道長度（channel length)，係定義為N-區113至位於閘 堆疊物G下方之P型基體區106 —側之距離。另外標號P 顯示元件間距(pitch)，係定義為N+區114S與P+區116交 接處至另一 N+區114D之中點間之距離。然而，如此水平 地設置於P型基底100上表面上之閘堆疊物G恐不利於 元件間距P之縮減，因此亦不利於LDMOS裝置之導通電 阻（Rds_on)的降低。 【發明内容】 本發明提供了一種半導體裝置及其製造方法，適合於 高電壓構件之應用與製備。 依據一實施例，本發明之半導體裝置，包括： 一基底，具有一第一導電性；複數個隔離結構，設置 於該基底之表面；一井區，設置於該些隔離結構間之該基 底内，具有相反於該第一導電性之一第二導電性以及一露 出表面；一基體區，設置於該井區之一部中，具有相同於 該基底之該第一導電性以及一凹表面；一閘堆疊物，設置 於該基底之一部上，部分覆蓋該井區之該露出表面與該基 體區之該凹表面；一汲極區，設置於該井區之另一部中且 未為該閘堆疊物所覆蓋，具有該第二導電性；一源極區， 設置於該基體區之一部中，具有該第二導電性；以及一基 體接觸區，設置於該基體區之另一部中，具有該第一導電 性且鄰近該源極區。 依據另一實施例，本發明之半導體裝置之製造方法， 96-072/T0492A-A41668-TW/Final 8 200952176 包括： 提供一半導體基底，其内設置有一井區，其中該半導 體基底具有一第一導電性，而該井區具有相反於該第一導 電性之一第二導電性與一露出表面；於該半導體基底之表 面上形成複數個隔離結構，其中該些隔離結構之一係形成 於該井區内之該半導體基底之上；形成圖案化之一遮蔽層 於該半導體基底上，以露出位於該井區内之該隔離結構； Φ 施行一離子佈植程序，以該遮蔽層作為餘刻罩幕，以於該 井區内之該隔離結構之下方形成一基體區，該基體區具有 一第一導電性；施行一餘刻程序，以該遮蔽層作為餘刻罩 幕，餘刻去除該井區内之該隔離結構，以露出該基體區， 其中該基體區具有低於鄰近之該半導體基底之一凹表面； 去除該遮蔽層；形成圖案化之一閘堆疊物，部分覆蓋該基 體區之該凹表面以及鄰近該基體區之該井區之表面；於該 基體區之一部内以及該井區之一部内分別形成一源極區與 .一汲極區，其中該源極區與該汲極區並未為該閘堆疊物所 覆蓋且具有該第二導電性；以及於該基體區之另一部内形 成一基體接觸區，該基體接觸區相鄰於該源極區且未為該 閘堆疊物所覆蓋並具有該第一導電性。 為了讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖示，作 詳細說明如下： 【實施方式】 請參照第2〜7圖所示之一系列示意圖，分別顯示了依 96-072/T0492A-A41668-TW/Final 9 200952176As shown in Fig. 1, the LDMOS device mainly includes a P-type dream substrate 100', and an N-type well region 1〇2 is disposed in one portion thereof. The surface of the intersection of the N-type well region 102 and the P-type Shixi base 100 is provided with a field oxide (FOX) 104 ', and thus the LDMOS device is substantially deprecated by the field oxides 104. Active area. These field oxides 1〇4 are formed by a conventional field oxide method. A P-type substrate 〇0€^) region 1〇6 is disposed in the N-type well region 102 located between the field oxides 104, which is formed in one of the N-type well regions 102 and is substantially adjacent to the left side. Field oxide 104. An N-zone 113, an N+ zone 114S and a P+ zone 116 are additionally disposed in the P-type base region 1〇6, wherein the N-region 113 is a lightly doped region, and the P+ region 116 is Adjacent to the N+ region 114S • and the two regions are exposed to the surface of the P-type base region 106 as a contact region between the source and the substrate. An N+ region 114D is additionally provided in the N-well region 1〇2 between the P-type base region 106 and the field oxide 104 on the right side as a drain. A gate stack G is formed on one of the surfaces of the N-type well region 102 of the field oxide 104 for use as a gate, which is sequentially stacked on the surface of the N-well region 1〇2. The gate dielectric layer U0 and the gate electrode 1〇8. A spacer 112 is disposed on the symmetrical side of the gate dielectric layer 11A and the gate electrode ι8 in the gate stack G. The gate stack G partially covers the j> type substrate region 106 and covers the N-region 113. 96-072/T0492A-A41668-TW/Final 7 200952176 Here, in the LDMOS device shown in Fig. 1, the symbol L shows the channel length, which is defined as the N-region 113 to the gate stack. The P-type base region 106 under G is the side distance. Further, the symbol P shows the pitch of the element, which is defined as the distance between the point where the N+ region 114S intersects the P+ region 116 to the other N+ region 114D. However, the gate stack G disposed horizontally on the upper surface of the P-type substrate 100 is disadvantageous in that the element pitch P is reduced, and thus is disadvantageous for the reduction of the on-resistance (Rds_on) of the LDMOS device. SUMMARY OF THE INVENTION The present invention provides a semiconductor device and a method of fabricating the same, which are suitable for application and fabrication of high voltage components. According to an embodiment, a semiconductor device of the present invention includes: a substrate having a first conductivity; a plurality of isolation structures disposed on a surface of the substrate; and a well region disposed in the substrate between the isolation structures Having a second conductivity opposite to the first conductivity and an exposed surface; a substrate region disposed in one of the well regions, having the same first conductivity and a concave surface of the substrate; a gate stack disposed on a portion of the substrate, partially covering the exposed surface of the well region and the concave surface of the base region; a drain region disposed in another portion of the well region and not being Covered by the gate stack, having the second conductivity; a source region disposed in one of the base regions and having the second conductivity; and a substrate contact region disposed on the other of the substrate regions The portion has the first conductivity and is adjacent to the source region. According to another embodiment, a method of fabricating a semiconductor device of the present invention, 96-072/T0492A-A41668-TW/Final 8 200952176 includes: providing a semiconductor substrate having a well region disposed therein, wherein the semiconductor substrate has a first Conductive, and the well region has a second conductivity opposite to the first conductivity and an exposed surface; forming a plurality of isolation structures on the surface of the semiconductor substrate, wherein one of the isolation structures is formed on the Overlying the semiconductor substrate in the well region; forming a patterned shielding layer on the semiconductor substrate to expose the isolation structure in the well region; Φ performing an ion implantation process, using the shielding layer as a residual a mask for forming a base region under the isolation structure in the well region, the base region having a first conductivity; performing a process of engraving, using the shielding layer as a residual mask, and removing the The isolation structure in the well region to expose the substrate region, wherein the substrate region has a concave surface lower than the adjacent one of the semiconductor substrates; removing the shielding layer; forming a patterned gate a stack partially covering the concave surface of the base region and a surface of the well region adjacent to the base region; forming a source region and a drain region in a portion of the base region and a portion of the well region Wherein the source region and the drain region are not covered by the gate stack and have the second conductivity; and a base contact region is formed in the other portion of the substrate region, the substrate contact region being adjacent to The source region is not covered by the gate stack and has the first conductivity. The above and other objects, features, and advantages of the present invention will become more apparent and understood. A series of schematic diagrams shown in Figure 7 shows the 96-072/T0492A-A41668-TW/Final 9 200952176
w ^實施例之水平型雙擴散金氧半導體(LDMOS)裝 障形，藉以製備出具有較低導通電阻之LDMOS 裝置。 明參照第2圖，首先提供一半導體基底200,其内設 置有井區2〇2’井區202之導電性相異於基底2〇〇之導 電挫其摻雜濃度例如介於1012〜1013原子/每平方公分。 在此半導體基底200例如為磊晶層基底絕緣層上覆矽 φ ( SO〗）基底或塊狀碎基底。半導體基底200具有一第一 導電性，例如為P型或N型導電性，且較佳地為P型導 電性，其摻雜濃度例如介於1〇ιι〜1〇π原子/每平方公分。 井區202可藉由習知離子佈植方法並採用適當之遮罩（未 顯不）所形成。接著’於半導體基底200上坦覆地形成一 塾氧化物層204以及一墊氮化物層2〇6，其依序堆疊於半 導體基底200上。接著藉由一微影與蝕刻程序（皆未顯 示）’以於墊氧化物層2〇4與墊氮化物層2〇6内形成數個 ❹ 開口’以分別部分露出其下方之半導體基底200。在此， 開口係繪示為位於兩侧之開口 〇ρ1以及居中之開口 0P2 ’其中開口 〇P2之尺寸略大於開口 〇Pl之尺寸，但 並不以此為限’開口 0P2之尺寸亦可等同於或小於開口 0P1之尺寸。開口 OP1分別露出其下方之半導體基底200 及井區202之一部’而口 〇P2則僅露出井區2〇2之一部。 上述墊氧化物層204之材質例如為二氧化矽，而墊氮化 物層206之材質例如為氮化妙。 請參照第3圖，接著於開口 〇pl與開口 〇p2内分別 96-072/T0492A-A41668-TW/Final 200952176 形成隔離結構208a與208b。而於形成隔離結構208a與 208b之後，形成圖案化之遮罩層210並露出隔離結構 208b及其鄰近之墊氮化物層206。接著施行一離子佈植 程序212 ’以於隔離結構208b下方之井區202内形成一 基體（body)區214，基體區214具有相同於基底200之導 電性’其掺雜濃度例如介於1〇12〜1〇14原子/每平方公分。 如第3圖所示，隔離結構208a與208b係繪示為場氧化 ❹ 物（field oxide,FOX)，其係由熱氧化法所形成，但隔離結 構208a與208b並不以場氧化物加以限制，其亦可採用 如淺溝槽隔離物（shallow trench isolation，STI)之其他隔 離結構。基體區214亦可早於隔離結構208a與208b前 先行形成’其可藉由搭配適當遮罩以及N型或P型離子 的使用而形成。上述罩幕層210之材質例如為光阻材料。 請參照第4圖，接著藉由一蝕刻程序（未顯示）以去除 隔離結構208b後，接著姓刻去除遮罩210、塾氮化物層 ❹ 206以及墊氧化物層204等膜層，進而露出了隔離結構 208a以及基體區214之表面250。在此，基體區214之 表面為低於半導體基底200表面之一凹面250，此凹面 250為圓滑化之表面，因而使得基體區214具有大體u 型之一剖面情形。接著則於半導體基底200上依序形成 閘介電層216與一導電層218’藉以順應地覆蓋半導體基 底200、凹面250與隔離結構208a之表面。如第4圖所 示’閘介電層216之形成方式例如為熱氧化法，因此其 材質可為氧化矽材質，且先前形成於第一井區2〇2内之 96-072/T0492A-A41668-TW/Final 11 200952176 基體區214於閘介電層216形成時將進一步擴散而形成 了一經擴散之基體區214’，而閘介電層216與導電層218 則順應地依序形成於半導體基底200上而具有部分凹陷 與部分凸起之表面。導電層218之材質則可為經掺雜之 多晶矽或矽化鎢之金屬材料。 請參照第5圖，接著，形成一圖案化之罩幕層（未顯 示）於導電層218上，並露出部分導電層218。接著施行 一蝕刻程序（未顯示）以移除為此圖案化之罩幕層所露 出之導電層218與閘介電層216部分，進而分別於半導 體基底200之一部上形成兩分隔之閘堆疊物G1與G2， 其分別部份覆蓋基體區2141之一部並露出閘堆疊物G1與 G2間之基體區214’部分。接著形成一圖案化之遮罩層 220，以部分露出閘堆疊物G1與G2及其間之基體區 214’。接著施行離子佈植程序222，以摻雜具有相同於井 區202導電性之摻質，以於基體區214'之一部内形成淺 摻雜區224。離子佈植程序222所採用之摻雜濃度例如介 於1012〜1013原子/每平方公分。 請參照第6圖，於去除圖案化之罩幕層220後，接 著於閘堆疊物G1與G2之對應側壁上分別形成一間隔物 226。接著藉由適當佈植遮罩（未顯示）之應用，以摻雜具 有相同於井區202導電性之摻質於基體區214'與井區202 内，以分別形成一源極區228s與一汲極區228d，所採用 之摻雜濃度例如介於1〇14〜1〇15原子/每平方公分。接著藉 由另一適當佈植遮罩（未顯示）之應用，以摻雜具有相異於 96-072/T0492A-A41668-TW/Final 12 200952176 井區202導電性之摻質於基體區214,内，以形成一基體 接觸區230，其所採用之摻雜濃度例如介於1〇i4〜1〇i5原 子/每平方公分’且此基體接觸區23〇大體位於兩個源極 區228s中間’而源極區228s分別鄰近淺摻雜區224並 接觸之。 如第6圖所示’在此LDMOS裝置係繪示為具有兩對 應設置之LDMOS元件’其係相對基體接觸物23〇而鏡 ❻ 像對稱地設置於半導體基底200之上。在此，於第6圖所 示之LDMOS裝置中’標號L'顯示了各LDMOS元件之通 道長度(channel length) ’係苳義為淺摻雜區224至位於閘 堆疊物G1與G2下方之P型基體區214’的一侧之距離。另 外標號P’則顯示了各LDMOS元件之元件間距(pitch)，係 定義為基體接觸區230與各源極區228s之交界處至汲極區 228d之中點間之距離。因此，參照第6圖所示結果，由 於基體區214’具有低於鄰近半導體基板200表面之一凹 ❹ 面，因而使得後續形成之閘堆疊物G1與G2可部分地設 置於上述凹面之上而非整體水平地座落於半導體基底 200之上，進而縮減了位於半導體基板200上之閘堆疊物 G1與G2之水平長度。因此，相較於第1圖所示之LDMOS 裝置，如第6圖所示之LDMOS裝置内之元件間距P可 進一步獲得縮減，如此可降低其導通電阻（Rds-on)。 再者，由於基體區214’係於閘堆疊物G1與G2形成 之前先行形成，因此對於第6圖所示之LDM0S裝置内 之LDMOS元件之通道長度L’可藉由於定義閘堆疊物G1 96-072/T0492A-A41668-TW/Final 13 200952176 與G2之蚀刻步·驟而控制，因此可較精準地控制其通道長 度L’，且可藉由基體區214'内不同場氧化層寬度的調整 而形成不同通道長度的元件。 請繼續參照第7圖，接著可坦覆地形成一層間介電 層230於第6圖所示之結構上。接著於層間介電層230 之内形成數個電性獨立之導電接觸物232d與232s，以分 別接觸各汲極228d、基體接觸區230與各源極區228s。 ^ 接著於層間介電層230上形成數條電性獨立之導線 234,此些導線234分別覆蓋了導電接觸物232d與232s， 進而與其下方之LDMOS元件之一部形成電性連結關 係。上述導電接觸物232d與232s以及導線234可藉由 習知接觸物與導線之製程所形成，其材質可為如經摻雜 之多晶矽、鎢或鋁等導電材料。在此，導電接觸物232s 則同時接觸了基體接觸區230及相鄰之源極228s。 雖然本發明已以較佳實施例揭露如上，然其並非用以 • 限定本發明’任何熟習此技藝者，在不脫離本發明之精神 和範圍内’當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖顯示了習知之水平型雙擴散金氧半導體 (LDMOS)裝置之剖面情形；以及 第2〜7圖為一系列示意圖，分別顯示了依據本發明一 實施例之水平型雙擴散金氧半導體(LDM〇s)裝置於不同製 作步驟中之剖面情形。 96-072/T0492A-A41668-TW/Final 200952176 【主要元件符號說明】 100〜P型矽基底； 102〜N型井區； 104〜場氧化物； 106〜P型基體區； 108〜問電極， 110〜閘介電層； 112〜間隔物； 113〜N-區， 114S、114D〜N+區； 116〜卩+區； L〜通道長度； P〜元件間距； G、Gl、G2〜閘堆疊物； 200~半導體基底； 202〜井區； 204〜墊氧化物層； 206〜墊氮化物層； 208a、208b〜隔離結構； 210〜罩幕層； 212〜離子佈植程序； 214〜基體區； 214'〜經擴散之基體區； 216、216a〜閘介電層； 96-072/T0492A-A41668-TW/Final 200952176 218、218a〜導電層； 220〜遮罩層； 222〜離子佈植程序； 224〜淺摻雜區； 226〜間隔物； 22 8 s〜源極區， 2 2 8 d〜 >及極區， 230〜基體接觸區； 232s、232d〜導電接觸物 234〜導線； 250〜基體區之表面/凹面 OP1、OP2-開口； L’〜通道長度； P1〜元件間距。The horizontal double-diffused metal oxide semiconductor (LDMOS) of the embodiment is formed to form an LDMOS device having a lower on-resistance. Referring to FIG. 2, a semiconductor substrate 200 is first provided, in which the conductivity of the well region 2〇2' well region 202 is different from that of the substrate 2, and the doping concentration thereof is, for example, 1012 to 1013 atoms. / per square centimeter. The semiconductor substrate 200 is, for example, an Δφ (SO) substrate or a bulk substrate on the epitaxial layer insulating layer. The semiconductor substrate 200 has a first conductivity, for example, P-type or N-type conductivity, and is preferably P-type conductivity, and its doping concentration is, for example, 1 〇 ι to 1 〇 π atoms per square centimeter. The well region 202 can be formed by conventional ion implantation methods and using a suitable mask (not shown). Next, a tantalum oxide layer 204 and a pad nitride layer 2 are formed on the semiconductor substrate 200, which are sequentially stacked on the semiconductor substrate 200. A plurality of 开口 openings ′ are then formed in the pad oxide layer 2〇4 and the pad nitride layer 2〇6 by a lithography and etching process (none of which are shown) to partially expose the semiconductor substrate 200 therebelow. Here, the opening is shown as an opening 〇ρ1 on both sides and a centered opening OP2', wherein the size of the opening 〇P2 is slightly larger than the size of the opening 〇P1, but not limited thereto, the size of the opening 0P2 may also be equivalent. At or less than the size of the opening 0P1. The opening OP1 exposes one of the semiconductor substrate 200 and the well region 202 below it, respectively, and the port P2 exposes only one of the well regions 2〇2. The material of the pad oxide layer 204 is, for example, cerium oxide, and the material of the pad nitride layer 206 is, for example, nitriding. Referring to Fig. 3, isolation structures 208a and 208b are formed in the opening 〇pl and the opening 2p2, respectively, 96-072/T0492A-A41668-TW/Final 200952176. After forming the isolation structures 208a and 208b, the patterned mask layer 210 is formed and the isolation structure 208b and its adjacent pad nitride layer 206 are exposed. An ion implantation process 212' is then performed to form a body region 214 in the well region 202 below the isolation structure 208b. The substrate region 214 has the same conductivity as the substrate 200. The doping concentration is, for example, 1 〇. 12 to 1 〇 14 atoms / per square centimeter. As shown in Fig. 3, the isolation structures 208a and 208b are depicted as field oxides (FOX) formed by thermal oxidation, but the isolation structures 208a and 208b are not limited by field oxides. It can also use other isolation structures such as shallow trench isolation (STI). The base region 214 may also be formed prior to the isolation structures 208a and 208b. This may be formed by the use of a suitable mask and the use of N-type or P-type ions. The material of the mask layer 210 is, for example, a photoresist material. Referring to FIG. 4, after the isolation structure 208b is removed by an etching process (not shown), the mask layer, the tantalum nitride layer 206, and the pad oxide layer 204 are removed by the surname, thereby exposing The isolation structure 208a and the surface 250 of the base region 214. Here, the surface of the base region 214 is a concave surface 250 that is lower than the surface of the semiconductor substrate 200, and the concave surface 250 is a rounded surface, thereby making the base region 214 have a substantially u-shaped profile. Then, a gate dielectric layer 216 and a conductive layer 218' are sequentially formed on the semiconductor substrate 200 to compliantly cover the surfaces of the semiconductor substrate 200, the concave surface 250, and the isolation structure 208a. As shown in FIG. 4, the formation of the gate dielectric layer 216 is, for example, a thermal oxidation method, so that the material thereof may be a yttrium oxide material, and 96-072/T0492A-A41668 previously formed in the first well region 2〇2. -TW/Final 11 200952176 The base region 214 is further diffused to form a diffused base region 214' when the gate dielectric layer 216 is formed, and the gate dielectric layer 216 and the conductive layer 218 are sequentially formed on the semiconductor substrate in a compliant manner. 200 has a partially concave and partially convex surface. The material of the conductive layer 218 may be a metal material of doped polysilicon or tungsten telluride. Referring to Figure 5, a patterned mask layer (not shown) is formed over conductive layer 218 and a portion of conductive layer 218 is exposed. An etching process (not shown) is then performed to remove portions of the conductive layer 218 and the gate dielectric layer 216 exposed for the patterned mask layer, thereby forming two separate gate stacks on one portion of the semiconductor substrate 200, respectively. The objects G1 and G2 partially cover a portion of the base region 2141 and expose portions of the base region 214' between the gate stacks G1 and G2, respectively. A patterned mask layer 220 is then formed to partially expose the gate stacks G1 and G2 and the base region 214' therebetween. Ion implantation step 222 is then performed to dope dopants having the same conductivity as well 202 to form shallow doped regions 224 in one of the regions 214'. The doping concentration used in the ion implantation process 222 is, for example, 1012 to 1013 atoms/cm 2 . Referring to Fig. 6, after the patterned mask layer 220 is removed, a spacer 226 is formed on the corresponding sidewalls of the gate stacks G1 and G2, respectively. The doping with the conductivity of the well region 202 is then doped into the base region 214' and the well region 202 by application of a suitable implant mask (not shown) to form a source region 228s and a respectively. The doping concentration of the drain region 228d is, for example, between 1 〇 14 and 1 〇 15 atoms/cm 2 . A dopant having a conductivity different from that of the 96-072/T0492A-A41668-TW/Final 12 200952176 well region 202 is then doped to the substrate region 214 by the application of another suitable implant mask (not shown). The substrate contact region 230 is formed to have a doping concentration of, for example, 1 〇i 4 〜1 〇 i 5 atoms per square centimeter and the substrate contact region 23 〇 is substantially located in the middle of the two source regions 228 s. The source regions 228s are adjacent to and in contact with the shallow doped regions 224, respectively. As shown in Fig. 6, the LDMOS device is shown as having two corresponding LDMOS devices which are disposed symmetrically on the semiconductor substrate 200 with respect to the substrate contacts 23A. Here, in the LDMOS device shown in FIG. 6, 'label L' shows the channel length of each LDMOS device, which is a shallow doped region 224 to P below the gate stacks G1 and G2. The distance of one side of the type of base region 214'. Further, the reference P' shows the component pitch of each LDMOS device, which is defined as the distance between the boundary between the substrate contact region 230 and each source region 228s to the point in the drain region 228d. Therefore, referring to the result shown in Fig. 6, since the base region 214' has a concave surface which is lower than the surface of the adjacent semiconductor substrate 200, the subsequently formed gate stacks G1 and G2 can be partially disposed on the concave surface. The non-integral level is seated on the semiconductor substrate 200, thereby reducing the horizontal length of the gate stacks G1 and G2 on the semiconductor substrate 200. Therefore, compared with the LDMOS device shown in Fig. 1, the element pitch P in the LDMOS device as shown in Fig. 6 can be further reduced, so that the on-resistance (Rds-on) can be lowered. Furthermore, since the base region 214' is formed before the gate stacks G1 and G2 are formed, the channel length L' of the LDMOS device in the LDMOS device shown in FIG. 6 can be defined by defining the gate stack G1 96- 072/T0492A-A41668-TW/Final 13 200952176 The etching step with G2 is controlled, so that the channel length L' can be controlled more precisely, and the width of the different field oxide layers in the substrate region 214' can be adjusted. Form components with different channel lengths. Continuing to refer to Fig. 7, a layer of interlayer dielectric layer 230 can be formed over the structure shown in Fig. 6. A plurality of electrically independent conductive contacts 232d and 232s are then formed within the interlayer dielectric layer 230 to contact the respective drains 228d, the substrate contact regions 230, and the source regions 228s, respectively. Then, a plurality of electrically independent wires 234 are formed on the interlayer dielectric layer 230. The wires 234 respectively cover the conductive contacts 232d and 232s, thereby forming an electrical connection relationship with a portion of the LDMOS device below. The conductive contacts 232d and 232s and the wires 234 may be formed by a process of a conventional contact and a wire, and may be made of a conductive material such as doped polysilicon, tungsten or aluminum. Here, the conductive contact 232s simultaneously contacts the substrate contact region 230 and the adjacent source 228s. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a cross-sectional view of a conventional horizontal double diffused metal oxide semiconductor (LDMOS) device; and Figs. 2 to 7 are a series of schematic views showing levels according to an embodiment of the present invention, respectively. The type of double diffused metal oxide semiconductor (LDM〇s) device is used in different fabrication steps. 96-072/T0492A-A41668-TW/Final 200952176 [Description of main components] 100~P type germanium substrate; 102~N type well region; 104~ field oxide; 106~P type base region; 108~Q electrode, 110-gate dielectric layer; 112~ spacer; 113~N-region, 114S, 114D~N+ region; 116~卩+ region; L~channel length; P~ component spacing; G, Gl, G2~ gate stack 200~semiconductor substrate; 202~well region; 204~pad oxide layer; 206~pad nitride layer; 208a, 208b~isolation structure; 210~ mask layer; 212~ ion implantation process; 214~substrate region; 214'~ diffused substrate region; 216, 216a~ gate dielectric layer; 96-072/T0492A-A41668-TW/Final 200952176 218, 218a~ conductive layer; 220~ mask layer; 222~ ion implantation program; 224~ shallow doped region; 226~ spacer; 22 8 s~ source region, 2 2 8 d~ > and polar region, 230~substrate contact region; 232s, 232d~ conductive contact 234~ wire; Surface/concave surface OP1, OP2-opening of the base region; L'~channel length; P1~ element spacing.
96-072/T0492A-A41668-TW/Final96-072/T0492A-A41668-TW/Final