W-FENAL-TW-20080118 200933755 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種半導體製程，且特別是有關於一 種晶片封裝製程及其結構。 【先前技術】 在現今高度整合的時代，半導體工業是技術成熟度高 ❹ 料業，也因應市場的需求，朝向多it化的市場發展各式 各樣的晶片封裝結構，例如光電相關產品 光元件（影像感測器）等，均可以半導體製程來製作^以 有效地降低成本。 圖1是習知-種晶片封裝結構的剖面示意圖。請參考 圖1，在晶片100的主動面1〇2上製作多個凸塊11〇以及 凸塊底金屬層 108 (Under Bump Metallurgy，UBM)。將製 作完成的晶片100翻覆之後，以晶片1〇〇的主動面1〇2上 的凸塊110與基板的接塾122電性連接，以構成一晶 片封裝結構130。其中，凸塊110例如是印刷的銲料凸塊、 電鍵的導電凸塊。此外，凸塊110亦可以是利用打線接合 製程所形成的金凸塊（或銅凸塊）。然而，在晶片1〇〇上 形成金凸塊時，打線接合設備對晶片1〇〇所施加的外力要 控制彳于當，否則晶片100内的積體電路將受損而無法正常 運作。 *' 此外，在晶圓階段製作凸塊底金屬層、銲料凸塊、電 艘凸塊或金凸塊的風險高，良率必須嚴格控制，而且重工 200933755 W-FINAL-TW-20080118 的難易度都會直接反應於成本及工時上。因此，如何減少 重工率並加快凸塊的製作工時，以提高產能，實乃本發明 之重點。 【發明内容】 本發明提供-種晶片封裝製程及結構，藉由在基板上 &作結線凸塊，以提高產能。 本發明提出一種晶片封裝製程。首先，提供一基板， =基板具有多個接墊。接著，通過—打線製程於該些接塾 董f應形成多個結線凸塊。平面化每—結線凸塊的頂端。 進行覆晶結合步驟’以將晶片與基板電性連接。 在本發明之-實施例中，覆晶結合步驟之後，進行一 =膠步驟’以包覆至少部分該些結線凸塊。封膠步驟包含 '入一底膠於該晶片與該基板之間。 在本發明之一實施例中，打線製程包括：提供—銲 你’接著’將銲線的一端加熱融化，使得鋅線的 』成-球塊；接著，將球塊壓到這些接墊之一上 由绳與金線切離。鲜線材料可選自由金、銀、銅 成的群組。 殂 在本發明之-實施例中，平面化這些結線凸塊 3進行-化學機械研磨製程。在另—實施例中，平= ^結線凸塊_端包括_—治具壓平這些結線凸塊的 在本發明之一實施例中，進行覆晶結合步驟包括··進 200933755 W-FINAL-TW-20080118 行-對位步驟，以將晶片對位於這些結線凸塊；接著對 晶片進行鏡接合，以使晶片上的多個銲塾與這些結線凸 塊固接。其中，對晶片進行熱屢接合之前，更包括形成一 焊料於晶片的輝墊上。此外，熱壓接合的步驟中更包含以 一超音波震動。 本發明提出-種晶片封裝結構，其包括一基板、多個 結線凸塊以及-晶片。基板具有多個接塾。多個結線凸塊 ❹㈤置於這些接墊上，而結線凸塊為具有至少-階梯表面的 塔形結構，且結線凸塊的頂端為一平面。晶片藉由這些結 線凸塊與這些接墊電性連接。 本發明將結線凸塊配置於基板的各個接墊上，因此不 需在晶圓階段製作凸塊底金屬層、銲料凸塊、電鑛凸塊或 金凸塊等結構’以降低風險。此外，在基板上製作結線凸 塊的成本低且良率高，能有效地降低重工率，進而提高產 月fci 0 為讓本發明之上述特徵和優點能更明顯易懂，下文特 1 舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 圖2A〜圖2D是本發明一實施例之晶片封裝製程及其 結構的示意圖。請參考下列步驟： 首先，第一步驟是提供一基板2〇〇，而基板2〇〇具有 多個接墊202以及形成於這些接墊2〇2上的多個結線凸塊 (stud bump) 210。結線凸塊21〇可通過一打線製程對應 W-FINAL-TW-20080118 200933755 形成於每一接墊202上。 第二步驟是平面化每一結線凸塊210的頂端214以成 為一平面214a。平面化結線凸塊210例如是進行一化學機 械研磨製程或利用一治具壓平結線凸塊21〇的頂端214 ^ 第二步驟是進行覆晶結合步驟，以將晶片220與基板 200電性連接。 八 請參考圖2A，在本實施例的第一步驟中，基板2〇〇 〇 是封裝載板，例如是具有多層線路的印刷電路板或由積層 線路所开>成的電路板。在基板2〇〇上形成多個結線凸塊21〇 的步驟是進行每一結線凸塊21〇之打線製程，其步驟如 下.由打線機提供一銲線；接著，將銲線的一端加熱 融化，使得金線的該端形成一球塊；將球塊壓到接墊 上，以形成具有階梯表面212的塔形結構，·最後，將 球塊與金線切離。如此重複打線製程，即可形成多個結 線凸塊210於這些接墊2〇2上，而結線凸塊21〇的形狀為 • 具有至少一階梯表面212的塔形結構，其截面積由下而上 依序遞減。形成結線凸塊21〇的銲線材料可選自由金、銀、 銅、銘組成的群組。 在基板200上形成結線凸塊210的風險低，相對於習 知在晶片上形成金凸塊’打線機對晶片所施加的外力可能 會造成晶片内的積體電路受損而無法正常運作。此外，在 基板200上製作結線凸塊21〇的成本低且良率高’能有效 地降低重工率，以提高產能。 明參考圖2B ’在本實施例的第二步驟中，由於結線 200933755 W-FINAL-TW-20080118 凸塊210與金線切離時所殘留的線頭將使結線凸 頂端214過於尖銳’因此進行一化學機械^磨製$以〇的 磨墊磨平結線凸塊210的頂端214以成兔一丞^ ’以研 提高平整度。在另-實施财，結線 亦可經由一治具壓平的方式以成為一平面214&。只嗎214W-FENAL-TW-20080118 200933755 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor process, and more particularly to a wafer packaging process and structure thereof. [Prior Art] In today's highly integrated era, the semiconductor industry is a technology maturity industry, and in response to market demand, the development of a variety of chip package structures, such as optoelectronic related products, in a multi-instant market. (Image sensor), etc., can be fabricated by a semiconductor process to effectively reduce costs. 1 is a schematic cross-sectional view of a conventional wafer package structure. Referring to FIG. 1, a plurality of bumps 11 and an under bump metallurgy (UBM) are formed on the active surface 1〇2 of the wafer 100. After the completed wafer 100 is overturned, the bumps 110 on the active surface 1〇2 of the wafer 1 are electrically connected to the pads 122 of the substrate to form a wafer package structure 130. The bump 110 is, for example, a printed solder bump or a conductive bump of a key. In addition, the bumps 110 may also be gold bumps (or copper bumps) formed by a wire bonding process. However, when a gold bump is formed on the wafer 1 , the external force applied to the wafer 1 by the wire bonding apparatus is controlled to be detrimental, otherwise the integrated circuit in the wafer 100 will be damaged and will not function properly. *' In addition, the risk of making bump metal layers, solder bumps, electric bumps or gold bumps at the wafer stage is high, the yield must be strictly controlled, and the difficulty of Heavy Industry 200933755 W-FINAL-TW-20080118 It will directly reflect the cost and working hours. Therefore, how to reduce the rework rate and speed up the production time of the bumps to increase the production capacity is the focus of the present invention. SUMMARY OF THE INVENTION The present invention provides a wafer packaging process and structure for improving throughput by using a bump on a substrate. The invention proposes a wafer packaging process. First, a substrate is provided, and the substrate has a plurality of pads. Then, through the wire-bonding process, a plurality of wire bumps should be formed on the joints. Plane the top of each of the line bumps. A flip chip bonding step is performed to electrically connect the wafer to the substrate. In an embodiment of the invention, after the flip chip bonding step, a =glue step is performed to coat at least a portion of the junction bumps. The encapsulation step includes 'entering a primer between the wafer and the substrate. In an embodiment of the invention, the wire bonding process includes: providing - welding you 'then' to heat and melt one end of the wire to cause the zinc wire to become a ball; then, pressing the ball to one of the pads The rope is cut away from the gold wire. The fresh wire material can be selected from the group of gold, silver and copper.殂 In the embodiment of the present invention, the junction bumps 3 are planarized to perform a chemical mechanical polishing process. In another embodiment, the flat = ^ junction bump _ end includes _ - the fixture is used to flatten the junction bumps. In one embodiment of the invention, the flip chip bonding step includes: · 200933755 W-FINAL- TW-20080118 Row-alignment step to place the wafer pairs on the junction bumps; then mirror bonding the wafers to secure the plurality of solder bumps on the wafer to the junction bumps. Wherein, before the thermal bonding of the wafer, a solder is formed on the glow pad of the wafer. In addition, the step of thermocompression bonding further includes an ultrasonic vibration. The present invention provides a wafer package structure including a substrate, a plurality of junction bumps, and a wafer. The substrate has a plurality of interfaces. A plurality of junction bumps 五(5) are placed on the pads, and the junction bumps are tower structures having at least a stepped surface, and the top ends of the junction bumps are a plane. The wafer is electrically connected to the pads by the wire bumps. According to the present invention, the junction bumps are disposed on the respective pads of the substrate, so that it is not necessary to fabricate a bump metal layer, a solder bump, an electric ore bump or a gold bump at the wafer stage to reduce the risk. In addition, the cost of making the bumps on the substrate is low and the yield is high, and the rate of rework can be effectively reduced, thereby increasing the yield month fci 0 so that the above features and advantages of the present invention can be more clearly understood. The preferred embodiment, in conjunction with the drawings, is described in detail below. [Embodiment] Figs. 2A to 2D are schematic views showing a wafer packaging process and a structure thereof according to an embodiment of the present invention. Please refer to the following steps: First, the first step is to provide a substrate 2, and the substrate 2 has a plurality of pads 202 and a plurality of junction bumps 210 formed on the pads 2〇2 . The wire bumps 21A can be formed on each of the pads 202 by a one-wire process corresponding to W-FINAL-TW-20080118 200933755. The second step is to planarize the top end 214 of each of the junction bumps 210 to form a plane 214a. The planarization junction bump 210 is, for example, a chemical mechanical polishing process or a top end 214 of a flattening wire bump 21 by a jig. The second step is to perform a flip chip bonding step to electrically connect the wafer 220 to the substrate 200. . Referring to Fig. 2A, in the first step of the embodiment, the substrate 2 is a package carrier, such as a printed circuit board having a multilayer wiring or a circuit board formed by a laminated circuit. The step of forming a plurality of bonding bumps 21 on the substrate 2 is to perform a wire bonding process for each of the bonding bumps 21, the steps of which are as follows: a bonding wire is provided by the wire bonding machine; then, one end of the bonding wire is heated and melted The end of the gold wire is formed into a ball; the ball is pressed onto the pad to form a tower structure having a stepped surface 212, and finally, the ball is cut away from the gold wire. By repeating the wire bonding process, a plurality of junction bumps 210 can be formed on the pads 2〇2, and the shape of the junction bumps 21〇 is a tower structure having at least one stepped surface 212, the cross-sectional area of which is Decrease in order. The wire bonding material forming the wire bump 21 可选 can be selected from the group consisting of gold, silver, copper, and Ming. The risk of forming the bumps 210 on the substrate 200 is low, and the external force applied to the wafer by the wire bonder on the wafer may be damaged by the external force applied to the wafer and may not function properly. Further, the cost of fabricating the bumps 21 on the substrate 200 is low and the yield is high, and the rework rate can be effectively reduced to increase the productivity. Referring to FIG. 2B', in the second step of the embodiment, the wire stub remaining when the bump 210 is cut away from the gold wire will be too sharp due to the knot line 200933755 W-FINAL-TW-20080118. A chemical machine is used to grind the top end 214 of the knot bump 210 with a rubbing pad to form a rabbit to improve the flatness. In another implementation, the knot can also be flattened by a fixture to become a plane 214 & Only 214
接者，請參考圖2C，在本實施例的第三步驟 作完成的晶片220翻覆之後，使其主動面^2朝’將製 行覆晶接合的步驟，其包括：首先，進行一對位L以進 將晶片220對位於這些結線凸塊21〇上；接菩，程，以 進行熱壓接合，以使晶片220上的多個鮮墊224 ^β、^^= 線凸塊210的頂端固接。其中，對晶片22〇進行熱=二二 之前，更可形成一銲料226於晶片220的這些銲墊、224接口 以使結線凸塊210藉由銲料226能更穩固地共晶接合。上’ 1 =熱壓接合時，更可以一超音波震動來;加:屬: e 最後，請參考圖2D，完成覆晶接合步驟之後 _ 一封膠步驟’以包覆結線凸塊21G。封膠步_如利^ 膠的方式填入底膠230於晶片220與基板2〇〇之間，而底 膠230經固化之後，包覆於結線凸塊21〇的 丨 -晶片封裝結構240的穩定性。 曰加 一由以上的說明可知，本發明的晶片封裝結構24〇包括 一基板200、多個結線凸塊210、一晶片22〇以及一底膠 23〇’而晶片220藉由這些結線凸塊210與基板2〇〇電性^ 接，以達到電性構裝的功效。此外，結線凸塊21〇為具有 200933755 W-FINAL-TW-20080118 至少一階梯表面212的塔形結構，其頂端214經由磨平或 壓平的方式成為一平面214a，以提高這些結線凸塊21〇的 平整度。 綜上所述’由於本發明將結線凸塊配置於基板的各個 接墊上，因此不需在晶圓階段製作凸塊底金屬層、銲料凸 塊、電鍍凸塊或金凸塊等結構，以降低風險◊此外，在基Referring to FIG. 2C, after the wafer 220 completed in the third step of the embodiment is overturned, the active surface 2 is subjected to a flip chip bonding step, which includes: first, performing a pair of bits L is placed on the pair of bumps 21 ; on the bumps 21, and is subjected to thermocompression bonding so that the plurality of fresh pads 224 ^β on the wafer 220 are at the top of the line bumps 210 Secured. Wherein, before the heat of the wafer 22 is performed, the solder 226 is formed on the pads 224 of the wafer 220 to make the junction bumps 210 more stably eutectic bonded by the solder 226. When the upper 1 = hot press bonding, a supersonic vibration can be applied; plus: gen: e Finally, please refer to FIG. 2D, after the flip chip bonding step is completed, the _ a glue step ′ is used to coat the wire bump 21G. The encapsulation step is filled with the primer 230 between the wafer 220 and the substrate 2, and the underfill 230 is cured, and then coated on the germanium-wafer package structure 240 of the junction bump 21〇. stability. As can be seen from the above description, the chip package structure 24 of the present invention includes a substrate 200, a plurality of junction bumps 210, a wafer 22 and a primer 23', and the wafer 220 is formed by the junction bumps 210. It is electrically connected to the substrate 2 to achieve the effect of electrical assembly. In addition, the wire bump 21 is a tower structure having at least one step surface 212 of 200933755 W-FINAL-TW-20080118, and the top end 214 is flattened or flattened into a plane 214a to improve the wire bumps 21 The flatness of the cockroach. In summary, since the present invention arranges the junction bumps on the respective pads of the substrate, it is not necessary to fabricate the bump bottom metal layer, the solder bumps, the plating bumps or the gold bumps at the wafer stage to reduce the structure. Risk ◊ in addition, in the base
板上製作結線凸塊的成本低且良率高，能有效地降低重工 率，進而提高產能。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作些許之更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。 【圖式簡單說明】 意圖。 封裝製程及其 圖1是習知一種晶片封裝結構的剖面示 圖2A〜圖2D是本發明一實施例之晶片 結構的示意圖。 【主要元件符號說明】 100 ·晶片 102 :主動面 108 :凸塊底金屬層 110 :凸塊 200933755 W-FINAL-TW-20080118 基板 接墊 晶片封裝結構 基板 接墊 結線凸塊 階梯表面 頂端 :平面 晶片 主動面 銲墊 銲料 底膠 晶片封裝結構 11The cost of making the bumps on the board is low and the yield is high, which can effectively reduce the rework rate and increase the productivity. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. [Simple description of the schema] Intention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a conventional wafer package structure. FIGS. 2A to 2D are schematic views showing a wafer structure according to an embodiment of the present invention. [Main component symbol description] 100 · Wafer 102 : Active surface 108 : Bump bottom metal layer 110 : Bump 200933755 W-FINAL-TW-20080118 Substrate pad Wafer package structure Substrate pad Junction block Step surface Top: Planar wafer Active surface solder pad solder base chip package structure 11