200906037 九、發明說明： 【發明所屬之技術領域】 有補償機制之變頻電路，係 之時機並提供補物電力波= 調整輸出，並g電路制其輪出模式以便於負載變動時 應器如第^圖所示包括—===節能 1目的；一般之電源供 單元15 一— 人側登机早兀U、一變壓器12、一脈波調變 單元更可^ 13以及連胁二:域輪_之—喊料，該回授 =W7t 141與，回授單元142，該—次側整流 由一次側概至二如12 ’該_12將電力 單元15提供之工作週期讲;3換為穩定直流輸出，而該脈波調變 墓、S㈣f〜就開關早幻3控制該變壓器12 一次側之 元⑷提供調變單元15可依該電流回授單元141及電壓回授單 响，但調降她工因作週期訊號之責任週期（duty cyde 有八底限’因此為更進一步節能，產辈I絡展 低而使上或向下波動； ^ —9 ^ rMethod and „s f〇r 」’關作可機賴關單元之動作頻 ☆ f僅可膽該_單元之工作週期訊號空佔比，更可 造-=低於r號之頻率’降低該開關單元切換時產生之損耗，達到更 動，:有耗二能動然難由於頻率是_載變 的聲曰、且變，式即施電路難以與功因校正電路及脈波調變電路整合·另 -類跳週__路如翻專鄉丽69狀「_祕福^ 5 200906037 _Gn」’ _作__轉換龍之 ^刀為-正㈣式（n_aI mGde)與—脈衝模式（bwst職^)，在重 tltTT J (outputpowersensingunit) ^輸出端負賴絲調舰波寬度，#負_賴錄度，該創作將 ^持^有脈波寬度，__某魏_脈波，湖電路透研低脈波寬 二2加遮f週期長度’達到降低損耗的目的，而脈衝模式之技術有明 職時之_干擾職生_換辭噪音會隨著頻率 裁愈賴’且使用者可明顯的聽到輕載卫作切換噪音，而且負 = 成輪出龍突降以及電路反應過度產生之波浪狀^ 步明顧\之第6圖與第8圖所示）；因而上述之習知創作具有不同 之低頻或差頻噪音等不足之處，必須改良上述之問題，以求更進 V，、其他電路整合並且降低使用者之不適感。 【發明内容】 發明!知之變頻方式會產生鮮不同步、電壓過度補償之問題，本 目的即在於提供—可依貞載魏喊頻之電路，且於頻率變動 變單元輸出之功週期訊號，可明 時對輸出之電壓造成之影響。 _ 雜^明t種具有補償機制之變頻電路，係應用於具有除頻模式之電 ==^應器至少具有一回授單元產生-回授訊號令-脈波調 «輸出之工作週期訊號，藉此調整一變壓器二次側 ==^調„元觸由—參考轉職一參考解减以及該= 頻電路可調二:加重或減輕時，該具有補償機制之變 且穩定鐵相仏參考^丰訊號及參考頻率訊號以達到隨負載調整工作頻率 判一 /日_用出，功效；其中該具有補償機制之變頻電路係包括一負載 訊號以及—位準調變單元，該負载判斷單元係依該回授 戍除頻模定是否輸出—_峨以決定該變頻電料作於正常模式 係取得—第一時脈訊號，並於正常模式時輪出-元將兮塗主夺良訊號相同之參考頻率訊號，又於除頻模式時，該除頻單 謂該弟—日·峨辦除以—魏後產生—第二時脈職，並且輸出與 200906037 該第二時脈訊號相同頻率之參考頻率訊號，而該位準調變單元係輸出 考位準訊號，並定義該參考位準訊號之一常態位準，其中該位準調變單 償早①以及—斜率產生器’該斜率產生11於接收該變頻訊號時令 〇貝凡產生-補償電流以改變該參考位準訊號，並令該參考準 =緩衝時間中回復該常態位準，以達到變頻時暫態補償與穩定輸出心力 【實施方式】 ^本伽之詳細及技抽容，職配合圖式說明如下： -雷3圖’本發明—種具有補償機制之變頻電路2，係用以調整 ===之脈波調變單元15輸出之卫作週期訊號vg， 疋15係參考辦峨呢一參 作週期訊號VG，該電源供應瞻二次侧整= ，並且輸出一參 ==連取得該回授訊號 元15 於λ a 號一參考鮮訊號W至該脈波調變單 側轉換至"出ΪΓ亥一次側整流單元11後由該變壓器12之一次 單元1、3控制，而^門關單至該變塵器12二次侧之電力大小係由該開關 15輸出之工作週期13啟閉之工作週期係受控於該脈波調變單元 元14漆吐％ 而該變壓器12二次侧輸出端連接一回授單 整該脈波調變單元15 該具= 調變單元22，該負载判斷單H斷早疋21、一除頻單元23以及一位準 於正常Γ 回授訊號WB之大小而選擇運作 於正常模式^得―第―*職①-並 仰，又於除賴式時械訊號CLK1 _之參考頻率訊號 以-整數财早兀23將鄉CLK丨之頻率除 CLK2相同頻率之夂考2脈訊號CLK2，並且輸出與該第二時脈訊號 位準訊號w，蝴該參；雜出該參考 變單元22係於正當心:株虎吸之一常態位準，其中該位準調 常模式及除頻模式間變換時產生一補償電流以調整該參 7 200906037 考位準訊號VR，令該脈波調變單元15隨之 償正常模式與除頻模式變換時電壓輸出之變動楚缸作週期訊號VG以補 請參閱第4圖與第5圖，該等圖式所 電路圖，該具有補償機制之變頻電路2係 構方塊圖與實施 單元22罐嫌鮮元23所誠，財該鱗 =位準調變 產生器221以及—補償單元222，變頻時該負栽 凡匕括一斜率 號Vs，該位準調變單元22之斜率產生H栽判斷^以輸出-變頻訊 令該補償單元222產生—補償電流以改變該參號Vs觸發後即 考準位訊號VR於-緩衝時間中回復該位準調變單元^虎^並=參 準’以達到變頻時暫態補償與穩定輸出 =二之位 212 > 213 ^ 數邏輯閘，該比較器A 211具有一正輪入端、一;==複 f a 2n，J^ 21=;m213丨’該比較11 a 211之輸出纖該d型正反器 (Q (CLK) — (CLK)她型正反器212之時脈控制端 (LK)係接收该參考頻率訊號w，該D型正 、 w 5 ^2i； 較益A 211之負輸出端，另—端則卺 切換途_ g ^ I正反15 212之負輸出端控制而 二換^該-第-疋電壓源214與一第二定電壓源215，且該第一定電壓 遷細if 一第一基準電壓’而該第二定電壓源215定義一第二基準電 且有補触^ WB與娜-基準職或紅鮮龍比較，當該 ς =機制之變頻電路2運作於正常模式時，若該回授訊㉚VFB小於 ^ 土準電壓’職具有補償機歡魏電路2由正常模式轉換為除頻 於麵赋時’若軸授職WB大_第二鮮，則由除 ^式轉換為正常模式’該D型正反器犯之運作邏輯為該技術領域者所 V y，此不再贅述’該D型正反器212之正輸入端輸出一狀態訊號 而3亥D型正反器212之輸出經過複數邏輯開運算後形成-變頻訊號200906037 IX. Invention: [Technical field of invention] The frequency conversion circuit with compensation mechanism is the timing and provides the supplementary power wave = adjust the output, and the g circuit makes its turn-out mode so that the load changes as the first ^ The figure includes -=== energy saving 1 purpose; general power supply unit 15 1 - person side boarding early U, a transformer 12, a pulse wave modulation unit can be more than 13 and even threat 2: domain wheel _-- shouting, the feedback = W7t 141 and the feedback unit 142, the secondary side rectification from the primary side to the second as 12 'the _12 will be the working cycle provided by the power unit 15; 3 for stable DC output, and the pulse modulation tomb, S (four) f ~ on the switch early magic 3 control the transformer 12 primary side of the element (4) provides the modulation unit 15 according to the current feedback unit 141 and voltage feedback single ring, but down She works as a cycle of responsibility for the cycle signal (duty cyde has an eight-limit limit), so it is further energy-saving, and the generation of I is low, causing upward or downward fluctuations; ^ —9 ^ rMethod and „sf〇r ” The operating frequency of the machine can be ☆ f can only be biliary _ unit duty cycle No. of space ratio, it can be made -= below the frequency of r number' to reduce the loss generated when the switching unit is switched, to achieve more change: the consumption of two can be difficult because the frequency is _ load-changing sonar, and change, It is difficult to integrate with the power factor correction circuit and the pulse wave modulation circuit. Another type of jumping week __路如翻乡乡69" "_秘福^ 5 200906037 _Gn"' _ __ conversion dragon The ^ knife is - positive (four) type (n_aI mGde) and - pulse mode (bwst job ^), in the heavy tltTT J (outputpowersensingunit) ^ output end negative silk adjustment ship wave width, #负_赖录度, the creation will ^ Hold ^ pulse width, __ a Wei _ pulse wave, lake circuit through the low pulse width 2 2 plus cover f cycle length 'to achieve the purpose of reducing loss, and the pulse mode technology has a clear job _ interference _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Figure 6 and Figure 8); therefore, the above-mentioned conventional creations have different deficiencies such as low frequency or difference frequency noise, and must be improved. The above problems, in order to more integration into V ,, and other circuits to reduce the discomfort to the user. SUMMARY OF THE INVENTION Invented! Knowing the frequency conversion method will produce the problem of fresh asynchronous and over-compensation of voltage. The purpose of the present invention is to provide a power cycle signal that can be outputted according to the frequency of the frequency-changing unit. The impact on the output voltage in the future. _ Miscellaneous ^ The variable frequency circuit with compensation mechanism is applied to the electric power with frequency division mode ==^ The reactor has at least one feedback unit generation-return signal command-pulse tone «output work cycle signal, By adjusting the secondary side of a transformer ==^ 调 ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ^Function signal and reference frequency signal to achieve one/day _ use and efficiency with load adjustment operating frequency; wherein the frequency conversion circuit with compensation mechanism includes a load signal and a level modulation unit, the load judgment unit According to the feedback, the frequency modulation mode determines whether to output - _ 峨 to determine that the frequency conversion electric material is obtained in the normal mode to obtain the first clock signal, and in the normal mode, the round-out signal will be the same as the main signal. The reference frequency signal, in the de-frequency mode, is the same as the frequency of the second clock signal of 200906037, which is generated by the second-time pulse division. Reference frequency signal, and the bit is adjusted The unit outputs a test position signal, and defines a normal level of the reference level signal, wherein the level modulation is compensated for 1 and the slope generator generates the peak when the frequency signal is received. Where-compensation current is generated to change the reference level signal, and the reference level = return to the normal level in the buffering time to achieve transient compensation and stable output power during frequency conversion [Embodiment] ^Details and techniques of the gamma The pumping capacity and job cooperation diagram are as follows: - Lei 3 diagram 'The invention is an inverter circuit 2 with a compensation mechanism for adjusting the output period signal vg of the pulse wave modulation unit 15 of ===, 疋The 15-series reference device is used as the periodic signal VG, and the power supply is supplied with the secondary side =, and the output is one parameter == even the feedback signal element 15 is obtained from the λ a number and the reference fresh signal W to the pulse wave. The modulation is converted to the "outside the primary side rectification unit 11, and is controlled by the primary unit 1, 3 of the transformer 12, and the power level of the secondary side of the transformer 12 to the secondary side of the dust collector 12 is controlled by the switch 15 output work cycle 13 work cycle of opening and closing is subject to The pulse modulation unit 14 is smear %, and the secondary side output of the transformer 12 is connected to a single feedback unit. The pulse modulation unit 15 has a modulation unit 22, and the load is judged to be H. 21. A frequency dividing unit 23 and a bit aligning with the size of the normal Γ feedback signal WB are selected to operate in the normal mode ^ ― ― ― _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The frequency signal is divided into two signals CLK2 of the same frequency of CLK2 except for the frequency of the integer CLK, and the output is synchronized with the second clock signal level signal w, and the reference is changed. Unit 22 is in the forefront: the normal level of the strain is sucked, and a compensation current is generated when the shift between the normal mode and the frequency-division mode is adjusted to adjust the reference signal VR of the test unit 200906037, so that the pulse wave The modulation unit 15 compensates for the change of the voltage output when the normal mode and the frequency division mode are changed. The cylinder is used as the periodic signal VG to supplement the circuit diagrams of FIG. 4 and FIG. 5, the circuit diagram of the patterns, the frequency conversion with the compensation mechanism. Circuit 2 system block diagram and implementation unit 22 cans of fresh elements 23, the scales = level modulation generator 221 and compensation unit 222, when the frequency conversion is performed, the slope includes a slope number Vs, and the slope of the level modulation unit 22 generates an H-branch judgment to output-frequency conversion command. 222 generates - compensating the current to change the parameter Vs, then the calibration signal VR returns to the level modulation unit in the -buffering time ^^^^================================================================== The second bit 212 > 213 ^ number logic gate, the comparator A 211 has a positive wheel end, one; == complex fa 2n, J ^ 21 =; m213 丨 'the comparison 11 a 211 output fiber d Type flip-flop (Q (CLK) — (CLK) The clock control terminal (LK) of her type flip-flop 212 receives the reference frequency signal w, which is positive, w 5 ^ 2i; Negative output, the other end is switched _ g ^ I positive and negative 15 212 negative output control and two replacement ^ the first - first voltage source 214 and a second constant voltage source 215, and the first The voltage is shifted by a first reference voltage' and the second constant voltage source 215 defines a second reference voltage and has a complementary touch ^WB compared with the Na-base or red fresh dragon, when the ς = mechanism of the frequency conversion When the road 2 is operating in the normal mode, if the feedback is 30VFB is less than ^ the quasi-voltage 'the job has the compensation machine Hua Wei circuit 2 from the normal mode to the frequency division in the face Fu's if the axis is awarded WB big _ second fresh , the conversion mode is changed to the normal mode. The operation logic of the D-type flip-flop is the V y of the technical field, and the description will not be repeated. The positive input terminal of the D-type flip-flop 212 outputs a state signal. And the output of the 3H D-type flip-flop 212 is formed by a complex logic operation to form an -inverted signal
S 200906037 =3Τ7ί23 231 μ複數邏輯閘，該τ型正 反器231亦具有一觸發端⑺、一時脈控制端（cl幻、一正 正L與其中該觸發端⑺連接該負载判斷單元21中月D型 反器212之正輸出端取得該狀態訊號％，該時脈控制端（c 脈’而該T型正反器231之運作邏輯亦為該技術領 域者所S知’不再贅述，該複數邏輯簡連接該負載 正^謂之負輸出端、該Τ型正反器231之正輸出端⑼並接中收= 時脈織CLK1而產生該參考頻率訊號w ;該位準 -斜率產^ 221，以及包含—第—補償迴路與—第二補償迴路 儿222，其令該第-補償迴路係由一第一電流源幻以及一第一偏 Vrefi組成，該第二補償迴路係由—第二電流源&、—第 ㈣S 200906037 = 3Τ7ί23 231 μ complex logic gate, the τ type flip-flop 231 also has a trigger terminal (7), a clock control terminal (cl magic, a positive positive L and the trigger terminal (7) connected to the load determination unit 21 in the month The positive output terminal of the D-type inverter 212 obtains the state signal %, and the clock control terminal (c pulse 'and the operation logic of the T-type flip-flop 231 is also known to those skilled in the art'. The complex logic is connected to the negative output terminal of the load, and the positive output terminal (9) of the 正-type flip-flop 231 is connected to receive the clock signal CLK1 to generate the reference frequency signal w; the level-slope is generated ^ 221, and including a - first compensation loop and - a second compensation loop 222, the first compensation circuit is composed of a first current source illusion and a first bias Vrefi, the second compensation loop is - Two current sources &, - (4)
Vref2以及-電阻器R4組成，其中該第一電流源幻與第二電流幻為 電流控制雜源，該第-補償迴路與第二補償迴路之間更包括1開關元件 SW1以及-二極體rn，其中該開關元件SW1係受控於該D型正反器加 之負輸出端’該斜率產生器221可為—數位計數器，該數位計數器^每一 輸出端皆連接-電阻器，而該數位計數器更具有一時脈輸入端接收一第三 時脈訊號CLK3，令贿位計數器以該第三時脈訊號CLK3之頻率倒數並 由複數輸出端輸出脈波，該數位計數器輸出之脈波控制該補償單元22 動作。 請-併參閱第5圖與第6圖，當負載為輕載時，為減少損耗而運作於 頻率較低之除頻模式’除頻模式中該負載判斷單元21之切換關213之 -端連接於該第-定電壓源2M (本實施例設定為α2ν)，該回授訊號 VFB大於該第-定電壓源214時該比較器ΑΉ1輸出為高準位，而該d型 正反器212輸出之狀態訊號VL為高準位，此時該除頻單元23之τ型正 反器231職生一第二時脈訊號CLK2，藉丁型正反器231之輸出特性，將 該第-時脈訊號όχι辦除以2讀纽鱗二雜贿clk2，複數 邏輯閘連接該負載判斷單元21中D型正反器m之負輸出端、該第二時 脈訊號CLK2與該第一時脈訊號CLK1後運算產生該參考頻率訊號w， 且該參考頻率訊號VF之頻率與該第二時脈訊號CLK2之頻率相同，此時 200906037 该位準調變單元22係由該補償單元222第二 電έ為固疋，即形成-參考位準訊號w之常態位準·當 WB下降至低於該第—定電壓源214之電壓，則 = 今D型正^12諸“之輸出反向而切換至該第二定電舰215，並且 1 繼耐咖，紅輸出端後 而輸出=ί 互斥或閘(X〇R _之兩輸入端不相同 丁型正及^立之㈣脈波’形成一變頻訊號^，此時該除頻單元23之 咖丨_之參；時脈訊號 中斜率以哭k 卩口復正常減，而該位準調變單元22 器更且有ϋ計數器受該贿訊號％之觸發，而該數位計數 221以Μ Y輸人端接收該第三時脈序號似3，並令該斜率產生器 形續物自織嫌胁輸出脈波， 2間該數位計數器之輸出端與該第，電源 對應之”—電流，使該第—補償迴路之第—電流源χι輸出一 仙型正:哭Γ第一電流源X1與第二電流源幻間之開關元件swi因 著該第電之負f，高準位而導通，使該第二電流源X2亦隨 電阻器R4㈣私❿纟電流’且該第二電流源D產生之電流經過該 载再二變小出端形成改變該參考位準訊號呢之負補償電流；當負 (本^化使'"回授訊號侧上升至高於該第二定龍源215之電壓 2_條相，該切換 複數舰疋電壓源214，該除頻單元23之Τ型正反請與 號CLK1、反器212輸出之狀態訊號凡以及該第一時脈訊 邏輯問輸出頻率齡=气生該第二時脈訊號⑽，並且經由複數 該位準調變單元2、2 ^二寺 K2相同之參考頻率訊號VF，此時 輸出脈斜率產生器221再次受該變頻訊號Vs觸發而倒數並 «源VrefT之^^原X1亦同樣依據該數位計數器輸出端與該第一偏 壓差產生對應之電流，由於該D型正反器212之負輸出 200906037 端為低準位，該開關元件SW1斷開，因而該第一電流源χι之電流經過一 二極體D1鰣_職—正婦錢，藉此膽該參考辦訊號1^ 本發明之斜率產生器221可為-數位計數器，以該第三時脈訊 CLK3之頻率倒數並輸出脈波，令第一麵迴路與第二補償迴路形成步進 上升或下降之補償電流，而該斜率產生器221亦可為包括至少—電容=之 ，放電迴路，且該電容H充放電咖之輕變化㈣鱗—職迴路之 流輸出大小；本發明具有除頻之讀令該電源供應料_勉重載時以 不同之頻率工作’更可設定該除頻單元23將該第—時脈訊號除以 整數（如2或3或4等），以此產生該第二時脈訊號CLK2之頻率 以降低工作祕，域由紅娜錢或貞補償電齡齡考位準 =於·模式之暫態具有蚊之平均斜率贿該常態轉，並於暫態^ j回设常祕準之_形賴緩衝時間，令該電源供魅之輸出電壓波 動降到最低，達職頻時健補償與穩定輸出之功效，並且本發明利用= $方式令辭變化係麵該第—時脈峨⑽經過除法運算而產生頻 率較低之帛二時脈_ CLK2 ’使_狀鮮仍可與縣之鮮同步， 如此即具備可與其他電路整合為一積體電路之優點。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任 何熟習此技，在獨離本發明之精神和範_，崎狀些許更動與 潤飾，皆應涵蓋於本發明中，因此本路 、 範圍所界定者為準。本發明之保護範圍當視後附之中請專利 ，應已充分符合新穎性 懇請貴局核准本件發 綜上所述，本發明較習知之創作增進上述功效 及進步性之法定創新專利要件，爰依法提出申請% 明專利申請案，以勵創作，至感德便。 11 200906037 【圖式簡單說明】 第1圖係習知電路架構圖。 第2圖係習知電路波形圖。 第3圖係本發明之應用電路架構圖。 第4圖係本發明之變頻電路架構方塊圖。 第5圖係本發明之實施電路圖。 第6圖係本發明實施電路之節點波形圖。 【主要元件符號說明】 11 ........次側整流單元 12 .......變壓器 13 .......開關單元 14 .......回授單元 141 .......電流回授單元 142 .......電壓回授單元 15 .......脈波調變單元 2 .......具有補償機制之變頻電路 21 .......負載判斷單元Vref2 and - resistor R4, wherein the first current source illusion and the second current imaginary are current control sources, and the first compensation circuit and the second compensation circuit further comprise a switching element SW1 and a diode rn The switching element SW1 is controlled by the D-type flip-flop plus a negative output terminal. The slope generator 221 can be a digital counter, and each digital counter is connected to a resistor, and the digital counter is connected. The clock input terminal receives a third clock signal CLK3, and causes the bribe counter to count down the frequency of the third clock signal CLK3 and output a pulse wave from the complex output terminal, and the pulse wave output by the digital counter control the compensation unit 22 action. Please-see also Figures 5 and 6, when the load is lightly loaded, in order to reduce the loss, the lower frequency mode is used to reduce the loss. In the de-frequency mode, the load judging unit 21 switches the end 213 end-to-end connection. The comparator ΑΉ1 output is at a high level, and the d-type flip flop 212 output is at the first constant voltage source 2M (the embodiment is set to α2ν). The feedback signal VFB is greater than the first constant voltage source 214. The state signal VL is at a high level. At this time, the τ type flip-flop 231 of the frequency dividing unit 23 generates a second clock signal CLK2, and the output characteristic of the butyl type flip-flop 231 is used to the first clock. The signal όχι is divided by 2 to read the new scale two bribe clk2, the complex logic gate is connected to the negative output terminal of the D-type flip-flop m in the load judging unit 21, the second clock signal CLK2 and the first clock signal CLK1 The post-operation generates the reference frequency signal w, and the frequency of the reference frequency signal VF is the same as the frequency of the second clock signal CLK2. At this time, the 200906037 the level modulation unit 22 is the second power of the compensation unit 222. Solid state, that is, the normal level of the reference level signal w is formed. When the WB falls below the first constant voltage source The voltage of 214, then = the current D type is ^12 "the output is reversed and switched to the second fixed ship 215, and 1 followed by the resistance, the red output and then the output = ί mutual exclusion or gate (X〇 The input terminals of R _ are different from the D-type and the (4) pulse wave 'forms a variable frequency signal ^, at this time, the frequency-dividing unit 23's 丨 _ parameter; the slope of the clock signal is crying k 卩 口Normally, the level shifting unit 22 is more triggered by the bribe number %, and the digit count 221 receives the third clock number like 3 by the 输Y input terminal, and makes the slope The generator-shaped continuum self-weaving the flank output pulse wave, and the output end of the two digital counters corresponds to the first power source, and the current source makes the first current source χι output a positive type: The switching element swi of the first current source X1 and the second current source is turned on by the negative f of the first electric current, and is turned on by the high level, so that the second current source X2 also follows the current of the resistor R4 (four). And the current generated by the second current source D forms a negative compensation current for changing the reference level signal through the second and second smaller output terminals; when negative ( ^化"'s feedback signal side rises to a voltage 2_ phase higher than the second constant source 215, the switching complex ship voltage source 214, the frequency division unit 23 is positive and negative, please contact the number CLK1 The status signal output by the counter 212 and the first time logic logic output frequency age = gas generated the second clock signal (10), and the same level modulation unit 2, 2 ^ two temple K2 is the same Referring to the frequency signal VF, the output pulse slope generator 221 is again triggered by the variable frequency signal Vs and counts down and the source X1 is also based on the current corresponding to the first bias difference at the output of the digital counter. Since the negative output of the D-type flip-flop 212 is at a low level, the switching element SW1 is turned off, and the current of the first current source χι passes through a diode D1 鲥 _ _ The slope generator 221 of the present invention can be a digital counter, and the pulse of the third clock CLK3 is inverted and the pulse wave is output, so that the first surface loop and the second compensation loop form a step. a rising or falling compensation current, and the slope generator 221 can also be Including at least - capacitance =, discharge circuit, and the light H charge and discharge coffee light change (four) scale - job loop flow output size; the present invention has a frequency reading read command power supply material _ 勉 heavy load is different The frequency operation 'is further set the frequency dividing unit 23 to divide the first clock signal by an integer (such as 2 or 3 or 4, etc.), thereby generating the frequency of the second clock signal CLK2 to reduce the working secret. Hongna money or 贞 compensation for the age of the tester = the transient state of the pattern has the average slope of the mosquito to bribe the normal state, and in the transient ^ j back to the regular secret _ shape buffer time, the power supply The output voltage fluctuation of the enchantment is minimized, and the effect of the compensation and the stable output is achieved at the frequency of the service, and the present invention uses the =$ mode to change the system. The first-time 峨(10) is subjected to the division operation to generate a lower frequency.帛2 clock _ CLK2 ' makes the _ shape fresh can still be synchronized with the county, so that it has the advantage of being integrated with other circuits into an integrated circuit. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any of the spirit and scope of the present invention, the slight change and refinement of the present invention, should be encompassed by the present invention. Therefore, the definition of this road and scope shall prevail. The scope of protection of the present invention is subject to the patents attached to it, and should be fully in line with the novelty. Please refer to this section for the approval of this article. The more innovative legal patents of the present invention to enhance the above-mentioned efficacy and progress, Applying for a patent application in accordance with the law, in order to encourage creation, to the sense of virtue. 11 200906037 [Simple description of the diagram] Figure 1 is a diagram of a conventional circuit architecture. Figure 2 is a diagram of a conventional circuit waveform. Figure 3 is a diagram showing the application circuit architecture of the present invention. Figure 4 is a block diagram of the frequency conversion circuit architecture of the present invention. Fig. 5 is a circuit diagram showing the implementation of the present invention. Figure 6 is a diagram showing the node waveforms of the circuit of the present invention. [Explanation of main component symbols] 11 ........ Secondary side rectification unit 12 .... Transformer 13 .... Switch unit 14 ......... feedback unit 141 . . current feedback unit 142 . . . voltage feedback unit 15 ... pulse wave modulation unit 2 ... ... frequency conversion circuit with compensation mechanism 21 .......load judgment unit
211 .......比較器A 212 .......D型正反器 213 .......切換開關 214 .......第一定電壓源 215 .......第二定電壓源 22 .......位準調變單元 221 .......斜率產生器 222 .......補償單元 23 .......除頻單元 231.......T型正反器 12211 ....... Comparator A 212 .... D type flip-flop 213 .... switch 214 .... first constant voltage source 215 .. ..... second constant voltage source 22 .... level modulation unit 221 ... ... slope generator 222 ... ... compensation unit 23 ..... .. frequency dividing unit 231.......T type flip-flop 12