200820364 九、發明說明 【發明所屬之技術領域】 緣檢 且徹 做了 和效 能半 查系 圓通 供各 -施-如--半導 之液 晶圓 得晶 半導 阻劑 單元 本發明關於一種檢查和量測，特別是關於一種 查和量測。 【先前技術】 過去數十年來，驅動半導體的技術已突飛猛進’ 底改革了我們的社會。半導體的製造者已在生產方頂 巨大的改善，此導致改善了末端產品的品質、速率、 能。然而，仍然持續有對更快、更可信賴、和更高僧 導體的需求。爲了幫助滿足此需求，渴望有較佳的楨 統和方法。200820364 IX. Description of the invention [Technical field to which the invention pertains] The invention relates to a checksum and a semi-conducting liquid crystal semi-conductive resistive unit Measurement, especially with regard to a type of investigation and measurement. [Prior Art] Over the past few decades, the technology that drives semiconductors has advanced by leaps and bounds. Semiconductor manufacturers have made tremendous improvements in production, which has led to improved quality, speed and performance of end products. However, there continues to be a need for faster, more reliable, and higher 导体 conductors. In order to help meet this need, we are eager to have better systems and methods.
半導體常常製造成晶圓形式。作爲參考之用’晶 常製造成多層，且包括被製造在晶圓邊緣上的缺口’ 一製-造-階-段-對-齊-晶· -圓-之-用--° -在-生-產-半.導-體.晶B的-期-間--遮罩層或阻劑層至晶圓，使得能夠依據後續的程序將 體晶圓圖案化。通常在晶圓旋轉期間，施加期望數量 體阻劑至晶圓的上表面。當旋轉晶圓時，阻劑材料從 的中心向外徑向地深展，且向半導體的邊緣展開，使 圓被一層阻劑實質地塗覆。過量的阻劑會堆積，且在 體晶圓的外部邊緣上形成阻劑小丘或小珠。爲了消險 的「邊緣小珠」，可使用稱爲邊緣小珠移除（EBR ) 的習知塗覆系統。 化學的邊緣小珠移除（EBR )單元包括噴嘴，該噴嘴 200820364 分配一種稱爲邊緣小珠移除流體至半導體晶圓的阻劑上。 該溶劑溶解或分解阻劑，且允許從半導體晶圓的邊緣輕易 地移除阻劑。在光學的邊緣小珠移除單元中，在半導體晶 圓邊緣處或附近的阻劑暴露於光線。在隨後的顯影製程期 間，移除已曝光的阻劑。如果在邊緣小珠移除期間，晶圓 沒有對準中心，則其餘的阻劑層相對於晶圓不能對準中心 。此外，被移除阻劑量的變化會影響阻劑邊緣離晶圓邊緣 之距離的變化。 不同的邊緣小珠移除單元和/或多個邊緣小珠移除製 程，（例如）會導致半導體晶圓之邊緣處或附近處基板層 的不均勻疊積。無論如何，因爲晶圓之阻劑層偏移，所以 會產生多個不想要的效果。例如隨機或不均勻的疊積基板 層會隆起，且不利地再沉積在半導體晶圓上。再沉積的基 板材料會污染半導體晶圓，並造成形成在晶圓上之積體電 ——°— - —------------- - — —"— ------------— ---------------------- —* 【發明內容】 本發明關於一種檢查和量測，特別是關於一種邊緣檢 查和量測。 【實施方式】 有很多理由可證明晶圓邊緣檢查和量測是重要的。例 如製程工程師需要能夠量測邊緣小珠移除線，亦確保其製 程正確地進丫了。例如邊緣移除線被整個晶圓表面的流動阻 -5- 200820364 劑所創造。在整個邊緣排斥區中，一除了由阻劑在晶圓邊 緣所形成的小珠。在圖案化和腐飩之後，依據所進行的製 程，移除阻劑且留下邊緣小珠移除線。藉由量測這些線相 對於晶圓和晶圓邊緣的幾何關係，例如此等製程工程師可 確保，他們的生產製程適當地操作。 因此以一般的用辭，依據本發明原理之邊緣構造特徵 量測系統和方法，被用於將趨近晶圓邊緣之外部邊緣的阻 劑層特徵化，且將趨近晶圓邊緣的其他晶圓構造特徵如所 希望地特徵化。一些實施例包括尋找從半導體晶圓邊緣至 阻劑層邊緣的相對距離，例如在繞著晶圓圓周移除阻劑之 處。做爲參考之用，雖然應暸解本發明的原理應用至藉由 各種晶圓生產製程所形成的阻劑邊緣（包括邊緣小珠移除 製程，但不限於此），但是本文所謂阻劑邊緣係指「邊緣 小珠移除線」。在一些實施例中，設有多個邊緣構造特徵 —’例—姐—晶邊-緣--、-晶圓-缺-Ξ或-平-邊-和-或~更多-邊-緣小—珠-移除線。方法也包括尋找晶圓的中心、和/或一或更多阻 劑層的中心、和（如果想要的話）晶圓中心一或更多阻劑 層中心之間的相對偏移。 當作幫助瞭解下文的討論，應注意的是一些實施例邊 緣構造特徵量測系統和方法，包括例如以設在徑向偏移旋 轉台中新的數位檢查相機，獲得晶圓邊緣的一系列數位影 像。在一些實施例中，以連續和/或步進方式，將晶圓的 整個外部圓周成像。選擇性地從此影像資料擷取晶圓缺口 位置、晶圓中心、阻劑層中心、邊緣小珠移除線位置、晶 -6 - 200820364 圓邊緣位置、和其他構造特徵。 例如選擇性地決定晶圓中心、阻劑層中心、檢查相機 座標系統、和/或晶圓缺口的位置。如下文將更詳細描述 者，晶圓邊緣的影像被累計地壓縮和評估，以較佳地評估 各種構造特徵。在一些實施例中，繞著使用此壓縮之晶圓 的整個圓周，評估從晶圓邊緣至阻劑已被移除處之邊緣小 珠移除線的距離。如上所暗示，晶圓上可呈現任何數目的 Φ 阻劑層，每一阻劑層有已移除小珠的邊緣，且界定邊緣小 珠移除線。因此在一些實施例中，在可應用之處，辨識或 • 追蹤有興趣的複數邊緣小珠移除線。 此外，要說明的是，藉由將晶圓成像所獲得的資訊（ 例如經運算之晶圓中心位置），可被用在相關的檢查製程 和系統中。例如晶圓中心位置可被用於報告和分析晶圓瑕 疵，或用於允許檢查相。設置該相機用於將晶圓邊緣（正 .....- 常-邊-緣―)·的-輪-廊或-側-邊-成-像-’以追-縱-正_常-邊緣’甚-先§午-相 • 機維持離晶圓之正常邊緣的焦距。因此在一些實施例中， 以邊緣小珠移除檢查系統和方法蒐集的資訊，被用做較大 且更詳細晶圓特徵系統或檢查量測的一部分。 ， 參考圖式，圖1例示半導體晶圓5 0的上視圖。晶圓 5〇界定邊緣區域1〇〇，且包括晶圓邊緣1〇2、晶圓中心 1 04、晶圓缺口 1 06、一層阻劑1 08、已移除阻劑的晶圓區 域1 1 0、阻劑中心1 1 2、阻劑邊緣1 1 4、晶圓邊緣1 02和阻 劑邊緣1 1 4之間的距離1 1 6、應有阻劑存再但已被移除的 晶圓區域1 1 8、和應已被移除但卻有阻劑存在的晶圓區域 200820364 120 ° 圖1例示阻劑中心1 1 2自晶圓中心1 04偏移。此不一 致常常是因爲在形成阻劑1 08期間、和/或在移除部份阻 劑1 08期間，操作者或機械誤差所造成。如先前所暗示者 ，晶圓50在製造期間之旋轉中心的位置，影響阻劑相對 於晶圓中心1 〇4的位置。例如在一些實施例中，在各種自 動製造步驟期間’晶圚5 0被固定在夾頭（未示）上。但 是由於自動化或其他誤差，旋轉中心有時候和晶圓中心沒 對齊。當旋轉中心和晶圓中心1 04沒對齊時，阻劑層（例 如阻劑層1 〇 8 )相對於晶圓5 0偏心地設置。 圖1例示阻劑中心1 1 2被誇大地從晶圓中心1 04偏移 ，使得兩中心1 〇4、1 1 2之間的不對齊可容易地辨別。但 是應注意的是，兩中心104、112之間的不對齊，實務上 常常是難以人類肉眼觀察。有此瞭解之後，也應注意晶圓 邊·緣…1-0 2-和-阻-劑-邊緣-14 4 .之間-的――距――酿-’-繞^ 周並不一致。此外也要注意，在晶圓製造期間，也可能產 生例如晶圓區域1 1 8 (其應包括阻劑但卻未包括）的瑕疵 區域。例如在一些製造製程中，由於很多原因而移除晶圓 區域118的阻劑108，該等原因包括各種製造或處理的不 一致性。在一些實施例中，在邊緣檢查製程期間，也辨識 瑕疵區域或潛在的瑕疵區域（例如晶圓區域120)。同樣 地，也選擇性地辨識例如晶圓區域1 20的區域，該等區域 不應有阻劑但卻有阻劑。供參考之用，晶圓區域1 20也可 例如因爲製造誤差或處理不一致而產生。 -8- 200820364 圖2是沿著圖1所示線2-2之邊緣區域100的放大視 圖。邊緣區域1 0 0包括阻劑邊緣i丨4、實質上無阻劑1 〇 8 之暴露的頂部區域1 3 0、晶圓邊緣1 〇 2、和也是選擇性地 實質無阻劑層（例如阻劑1 〇 8 )的晶圓底部區域1 3 4。晶 圓邊緣102界定頂部斜面136、晶圓邊緣標準（normal ) 138、和底部斜面140。 圖3是與本發明之原理一致的邊緣檢查系統150的 示意圖。邊緣檢查系統150包括頂部邊緣感應器152、底 部邊緣感應器1 5 4、標準邊緣感應器156、控制器158、底 座160、和工作台組合體162。頂部邊緣感應器152包括 相機164，標準邊緣感應器156包括相機166，而底部邊 緣感應器154包括相機168。工作台組合體162包括馬達 170、編碼器172、和支撐板174。馬達170耦合至編碼器 172和支撐板174，所以馬達170適於轉動支撐板174。編 碼-器—1-7-2 -提-供-g十-數用-於-控-制-馬-達-的-位-置-。…在-·晶-隱-5 0--旋-轉和成像期間，支撐板1 74支撐晶圓5 0。控制器1 5 8經由 通信鏈176電性地耦合至頂部邊緣感應器152、經由通信 鏈1 7 8電性地耦合至標準邊緣感應器1 5 6、經由通信鏈 1 80電性地耦合至底部邊緣感應器1 54、和經由通信鏈1 82 電性地耦合至工作台162。控制器158經由通信鏈176、 178、180、182控制頂部邊緣感應器152、標準邊緣感應 器156、底部邊緣感應器154、和工作台組合體162，以檢 查邊緣區域1〇〇。 在一些實施例中，以邊緣檢查系統1 5 0從頂部、標準 -9- 200820364 、和底部方向檢查邊緣區域100，雖然也可考慮其他方向 和角度的檢查。一般而言，邊緣檢查系統1 5 0藉由頂部邊 緣感應器152執行邊緣區域100 (圖2 )的頂部檢查、藉 由底部邊緣感應器1 5 4執行晶圓5 0之邊緣區域1 0 0的底 部檢查、和藉由標準邊緣感應器1 5 6執行邊緣區域1 00的 標準檢查。邊緣檢查系統150沿著晶圓50之邊緣區域100 檢查和/或量測，包括阻劑邊緣1 1 4、暴露的頂部區域1 3 0 、和晶圓區域1 〇 2。在一些實施例中，邊緣檢查系統也檢 查和/或量測晶圓邊緣1 02的頂部斜面1 3 6、晶圓邊緣標準 138、和底部斜面140。 參考圖2，頂部邊緣感應器152具有檢查區域184、 標準邊緣感應器156具有檢查區域186、和底部邊緣感應 器154具有檢查區域188。因此，在一些實施例中，邊緣 檢查系統150沿著晶圓50之邊緣區域100如所希望地檢 ——…查—和—/或看―測—1包括—阻_獨一4—〇—8—、—阻—劑緣——、—.暴—獯—的—頂；— 區域1 3 0、頂部斜面1 3 6、邊緣標準1 3 8、底部斜面1 40、 和晶圓底部區域1 34。在一些實施例中，利用黑暗區和明 亮區照明以檢查晶圓特徵，例如用於評估阻劑1 1 4繞著晶 圓5 0之圓周的位置。 參考圖4-1 9，依據本發明原理之邊緣檢查的一些實施 例，包括獲得繞著晶圓邊緣區域1 00的複數影像，且每一 影像爲具有第一維X和第二維γ的像素（pixel )陣列190 ，壓縮在第一維X的每一像素陣列1 9 0，將被壓縮的像素 陣列190連綴（stitch)成邊緣圖像（map)，且分析邊緣 -10- 200820364 圖像以辨識一或更多邊緣特徵，例如阻劑邊緣1 1 4和晶圓 邊緣102。 圖4例示以晶圓檢查系統150繞著邊緣區域100獲得 影像期間之晶圓5 0的一部分，特別是頂部邊緣感應器1 5 2 在晶圓5 0轉動（例如在旋轉方向r )時，繞著邊緣區域 1 〇 〇量測’以獲得邊緣區域1 0 0附近的影像。在一些實施 例中，繞著整個邊緣區域1 00取得影像。如果希望的話， 重疊地取得影像，以幫助確保含蓋完整的邊緣區域1 〇〇， 或增加所獲得之影像資訊量以得到較佳的解析度（如下文 將詳細描述者），雖然沒重疊的影像、分離的影像、和其 組合等也都爲本發明所想要的。 在一個實施例中，就2 0 0毫米放大機構而言，獲得 128個數位影像以確保含蓋晶圓50的3 60度影像。但是頂 部邊緣檢查相機1 52如所希望地選擇性地獲得更多數或更 …少數-的畫-面--，-视-如-上-違·—3 -6-0-畫-面-或-更-多以―獲得—被—檢―查― 之晶圓5 0整個圓周的影像，或較高解析度的邊緣圖像。 在一些實施例中，頂部邊緣檢查相機152具有上達7微米 的解析度。要注意的是較大倍率的放大要求額外的影像， 而較小倍率的放大要求較少的影像，以將邊緣區域1 0完 全地成像。因此，放大倍率和影像數目的其他組合，也都 爲本發明所想要的。 圖5是頂部邊緣感應器1 52所取檢查區域1 84之影像 資料所對應的像素陣列1 9 0的大致代表。在一些實施例中 ，使用底部邊緣感應器156進行類似的資料/製程，以將 -11 - 200820364 晶圓5 G底邰成像或特徵化。儘管如此，像素陣列1 9 〇選 擇性地包括例如晶圓邊緣1 02、頂部斜面1 3 6、和阻劑邊 緣1 1 4等相關位置的亮度資料。像素陣列丨9 〇界定第一次 元（dimension) X和第二次元γ。如圖所示，X次元和晶 圓50 (特別是晶圓邊緣1〇2)實質地相切，且γ次元實質 地和晶圓5 0徑向地對齊，雖然像素的其他方位也都爲本 發明所想要的。像素1 90包括灰階亮度資訊，雖然在其他 實施例也想要其他類型的資訊（例如彩色資料）。在取得 影像期間，獲得許多像素陣列1 9 0，且像素陣列1 9 0的每 一像素具有亮度値。如下文所述，在壓縮之前或壓縮之後 ，每一像素陣列依序連綴在一起，以適當地對齊複數像素 陣列，而形成邊緣區域100的影像圖像。 在其他實施例中，每一數位影像對應於一像素陣列（ 也稱爲影像圖像），其具有橫越第一次元X的1 6 0 0個水 --平-像-素--、-~和-橫-越-第-三-次-带年的--1-2 0夺偃-直-奋]象-素一--雖-然其-他像素陣列也爲本發明所想要，例如像素陣列選擇地爲橫 越第一次兀X的 1920個像素、和橫越第二次元 Y的 1 〇 7 8個像素。在一些實施例中，1 6 0 〇 X 1 2 0 0陣列對應 於200毫米影像放大結構。但是應瞭解如果使用較大的放 大倍率（例如3 00毫米結構），則需要較大數目的數位影 像，以將邊緣區域1 00沿著晶圓5 0的圓周完全地成像。 類似地，如果使用較小的放大倍率，（例如1 00毫米）， 則需要較小數目的數位影像，以將邊緣區域1 〇〇沿著晶圓 50的圓周完全地成像。 -12- 200820364 在一些實施例中，完成環繞晶圓5 0圓周的一或二次 完全通過，且以實質地連續和/或步進的方式蒐集資料。 在具有二次通過的一些實施例中，第一次通過是明亮區資 料，而第二次通過是黑暗區資料。如果想要的話，晶圓50 旋轉超過一圈（迴轉）或超過二圈，例如1.1圈、2.1圈 、或如所欲的其他圈數，以幫助確保在取得影像之起點和 終點處的一些重疊、和/或獲得所欲數量的影像資訊。 圖6是藉由壓縮橫越第一次元X之像素陣列1 90而產 生的已壓縮影像192，在一些實施例中，只在第一次元X 獲得壓縮，而第二次元Y沒被壓縮。藉由各種方法完成橫 越第一次元X的壓縮。在一些實施例中，像素陣列1 90被 對應於橫越第一次元X之像素陣列1 90的平均亮度値所壓 縮，以在第二次元Y產生單一行的像素亮度値；雖然在一 些實施例中，希望像素陣列1 90被壓縮成更多行的像素。 儘-管如-此藉--由-橫-越-第^^ -次-7E—X-的壓縮一’―哥~減--少-在量-度-的-像差、在亮度的隨機變化、藉由晶圓圖案化所誘導的亮度 變化、和其他不想要的影像資料效果。 因此在一些實施例中，每一影像被平均像素列（換言 之，橫越第一次元X)所壓縮，且導致許多影像在第二次 元Y是全部深度，但在第一次元X只有一個像素寬。以 此方式，可減少橫越第一次元的變化（例如隨機影像變化 或晶圓圖案化），以強調沿著第一次元X實質地延伸的正 規特徵。因此，沿著第一次元X的影像壓縮，例如被用於 執行雜訊和/或不想要的邊緣抑制。 •13- 200820364 符合本發明原理之影像壓縮的各種額外特徵和晶圓邊 緣量測/檢查，在圖7-16被圖解和描述。一般而言，影像 壓縮幫助移除或減少晶圓元圖案化、影像資料的隨機變化 、或其他不想要之影像資訊所關聯的應向資訊。此等圖案 和其他隨機變化會造成發現阻劑邊緣1 1 4、其他邊緣小珠 移除線、和其他邊緣特徵的困難。在一些實施例中，在影 像擺取和壓縮之後，該等影像被連結（concatenate)(例 如藉由連綴作業）成單一複合影像，也稱爲已壓縮影像的 影像圖像、邊緣圖像、邊緣小珠移除圖像。 參考圖7、8，在一些實施例中，晶圓邊緣1 02和頂部 邊緣斜面136位在複合影像內，且以被發現的晶圓邊緣 1 02爲基準，將複合影像標準化，使得複合影像之被發現 的晶圓邊緣1 02可被顯示成一直線。如果需要的話，當影 像是圓形且連續的物體（即晶圓50)時，藉由將邊緣移位 -至複-合-影像-的一俏f或-另一可-將些實―施—膝之—複-合――影—像 中顯現爲不連續之晶圓缺口 106或平邊呈現在中央。 在一些實施例中，執行邊緣發現演算法（algorithm ) /方法，以決定邊緣小珠移除線。在一些實施例中，應用 Canny邊緣偵測器和Sob el邊緣偵測器。基於開始的像素 特徵和邊緣臨界條件（對照一些例子），如果滿足選定的 邊緣臨界條件，線段藉由增加像素而成長爲線段組。在一 些實施例中，允許使用者調整上和下邊緣梯度臨界値、邊 緣強度（例如平均線段梯度）臨界値、和/或線段尺寸臨 界値，以捨棄或強調特別的線段組。因此在一些實施例中 -14- 200820364 ，只有特別尺寸/邊緣強度/梯度在後續步驟被處理。 在一些實施例中，分析整個區段的線段強度以決定線 段的輪廓，其能指示邊緣小珠移除線和/或雜訊，且允許 在邊緣擬合（配適fitting )期間或之前捨棄壞的線段。選 定第一線段，且以曲線擬合該線段。在一些實施例中，邊 緣小珠移除線呈良好的正弦曲線。因此選定正弦曲線擬合 該等線段。但是可選擇其他類型的曲線或線供此擬合步驟 〇 在一些實施例中，辨識後續的線段，且計算第一曲線 擬合線段的距離（平均、中間、或和/或絕對），以看看 他們和第一擬合曲線是否爲良好的擬合。在後續線段是良 好擬合之情況，該線段連結於第一線段，且後續曲線被擬 合。此製程持續反覆，直到邊緣小珠移除線被特徵化。在 線段離所形成之邊緣小珠移除線太遠的情況（如另一臨界 位-準-所-決—定—者4 —，-新曲-線可-擬-合選定的屬-段— 續直到所欲數目之線段或影像畫面呈現，例如實質地所有 影像畫面，被包括在已擬合的曲線中。 圖7 A、7 B顯示影像擷取和壓縮、擬合影像、和複合 影像的例子。圖7A代表在上述參考圖4、5描述之影像擷 取期間，所獲得一部分晶圓和其影像的例子。圖7A顯示 晶圓400和邊緣402的示意圖，其指示對應於晶圓邊緣 4〇2之各位置的複數被擷取影像404。圖7A也顯示了取自 晶圓邊緣402之單一非壓縮影像406的例子。圖7B代表 在處理複數被擷取影像404之後，被壓縮且擬合之晶圓邊 -15- 200820364 緣402的例子。更特別地，圖7B示意地顯 晶圓400的邊緣402，其被呈現爲由一系列 取影像404組成的一條線408。取自線408 404的線段410，被顯示成被擬合壓縮影像 所示的線段可包括任何數目的已壓縮影像， 未包覆（unwrapped)」的晶圓邊緣408。 已壓縮影像4 1 2的例子可以各種方法由 像編輯而得。例如單一影像406可先被壓縮 已壓縮影像4 1 2。此外，單一影像可先被擬 縮成已壓縮影像4 1 2。 被壓縮且被連綴在一起的影像412，允 生在晶圓位準，而非僅考慮一個畫面一個畫 經由整個晶圓追蹤邊緣小珠移除線，而非經 面。可使用演算法計算晶圓邊緣的準確位置 心-的孺书-，-且寻計-蒉-全都-邊-緣-小-珠-备除-線離-離。 圖8顯示當晶圓400的中心位於晶圓軸 軸線沒有位在旋轉夾頭中心時，所獲得影像 。兩軸線4 1 4、4 1 6之間的偏移造成邊緣小 偏離晶圓邊緣402的同心圓，且邊緣小珠移 心示意地位在阻劑軸線上。整個邊緣圓周之 結的影像，顯示成影像4 1 5而爲邊緣小珠移 有在夾頭中心上之晶圓的邊緣小珠移除線呈 例子中，晶圓4 0 2的邊緣也未呈直線。此例 示大致圓形之 之被擬合被擷 之被擬合影像 4 1 2的例子。 其包括整個^ 單一非壓縮影 ，然後擬合成 合，然後被壓 許檢查晶圓發 面地變化。可 由每一個別畫 和其與晶圓中 -晶-圓-邊·-緣-的-距- 線4 1 4且阻劑 例子的示意圖 珠移除線4 1 8 除線4 1 8的中 已壓縮且已連 除線圖像。沒 正弦線。在此 子可使用演算 -16- 200820364 法將晶圓邊緣4 02變直，使其成如影像419中所示地晶圓 位在夾頭中心上’而呈整個邊緣4 02圓周之已壓縮、已連 結、和已變直的影像。影像4 1 9可呈現邊緣小珠移除線 418離晶圓邊緣402的距離。在影像419中，晶圓邊緣 4 02在邊緣小珠移除圖像上已變直，且阻劑偏移晶圓的中 心。當邊緣小珠移除線逐漸正弦，則偏移隨之變大。 圖9A、9B記載具有單一邊緣小珠移除線之未圖案化 晶圓的影像例子的示意圖。圖9A顯示中心位在晶圓軸線 414上之另一例子的晶圓400，且阻劑軸線416未位在旋 轉夾頭的中心上。圖9B顯示其對應之整個邊緣402圓周 的已壓縮、已連結、和已變直的影像420，其具有已呈現 的邊緣小珠移除線422和額外的特徵。已呈現的邊緣小珠 移除線422是在已變直之晶圓邊緣上的已壓縮已連結的線 ，其對應實際的邊緣小珠移除線418。影像420也呈現有 --------內-公—線—4~2~4—和-外-公差：~^泉——4 2-6 &內-公^.差·線r - 4 2 4--界-定—較佳-邊- 緣小珠移除線離晶圓中心的最小距離，外公差線426界定 較佳邊緣小珠移除線離晶圓中心的最大距離。在此兩公差 之間的邊緣小珠移除線包括了在製造規格內的區段。 此例子也顯示滑動放大感43 2的特徵。此例子中的滑 動放大桿432包括刻度尺434，其能指示離晶圓中心的距 離（例如以毫米計），但是應瞭解也可使用任何適合的量 測刻度尺。滑動放大桿432也可包括示窗436，其將大略 對應於滑動放大桿432重疊之邊緣小珠移除線422處的晶 圓400邊緣402附近的原始資料放大。在另一例子中，滑 -17- 200820364 動放大桿沒有重疊影像4 2 0 ’而是以分離的視窗顯示。 此例子提供能從影像得知之計量資料的清單。內部和 外部公差424、426可由使用者定義，且可由各種指標（ 例如不同顏色、陰影、或類似者）來呈現。最好的圓圈擬 合可應用於在圓形晶圓呈現之已壓縮影像的資料。在另一 實施例中’圓形的呈現可由應用至已連結邊緣圖像或邊緣 小珠資料圖像之最佳擬合正弦來形成。在圖9 A中，在規 格外側之邊緣小珠移除線418的部分顯示成部分428，且 在規格以內之邊緣小珠移除線的部分顯示成部分4 3 0。也 可獲得或顯示中心偏移、或軸線4 1 4和4 1 6之間的位移。 此例子提供能從影像得知之計量資料的清單。內部和 外部公差424、426可由使用者定義，且可代表離晶圓中 心的毫米。此外，邊緣斜面寬度4 3 8也可以毫米量測，且 可量測邊緣小珠移除銳利因子、標準偏差、或兩者。可由 嚴-屯—心i —414_ __之—x—座—標―或—X座-標—毫盘値」—來量測.軸j泉j 4 1 6之間的偏移。或可以半徑距離毫米値和角度做徑向量 測。其他的邊緣小珠移除統計可用於將影像量化，例如平 均、中間、多模式資料（例如紅、綠、藍資料）、和包括 游離者之最小和最大値的標準偏差。 系統的其他特徵可被成像。在例子中，可用標準偏差 來決定邊緣小珠移除線的粗糙度。如果邊緣小珠移除線不 完全，則可以最佳正弦擬合或最佳圓形擬何來使該線完全 。可使用影像壓縮或過濾技術來量測邊緣小珠移除線的凹 陷（undercutting )。可基於明亮區和黑暗區影像來分析 -18- 200820364 邊緣小珠移除線。邊緣小珠移除線圖像可以彩色影像（例 如紅色、綠色、和藍色頻道）爲基礎。可以許多格式來輸 出結果，該等結果可被格式化以相容成爲較大且更完全之 晶圓特徵化系統的一部分，其例子包括具有影像的和諧 ASR、純文字（text) 、Excel、和 KLARF。 圖1 0顯示具有多重邊緣小珠移除線之未圖案化晶圓 之影像例子的示意圖。在所示的例子中，多重邊緣小珠移 除線423、425彼此沒有相交，或者其中一條423比另一 條42 5在環繞晶圓之所有點總是更靠近中心。使用者界定 的邊緣小珠移除線427可被決定，且使用者可選擇所希望 的邊緣小珠移除線，以從各種潛在的已擬合線追蹤或辨識 。在各邊緣小珠移除線相交的情況，會基於相交的點數和 相關的資料呈現警示（例如以影像）。 圖1 1也顯示具有邊緣小珠移除線之未圖案化晶圓之 氣像_掘„王_的_兀_寬_胤_ L先前各_观_子虫_已量麗的邊緣_也.移__餘_ 線，可沿著已呈現的邊緣小珠移除線提供多個點43 8做樣 本。消除統計上的游離者440，且使用最佳正弦擬合或最 佳圓形擬何來提供虛擬的邊緣小珠移除線。最佳圓形擬合 可由先前應用的最佳正弦擬合衍生而得。可由此虛擬線推 導出定性和定量的資料。在阻劑完美地位在中心且晶圓邊 緣被變直的情況，阻劑也會是直的，且擬合會包括振幅爲 零的正弦。 圖1 2顯示以本發明之例子所獲得之實際影像的代表 呈現。影像450是含有圖案451之已圖案化晶圓的放大視 -19- 200820364 圖，其包括第一邊緣小珠移除線452、第二邊緣小珠移除 線454、晶圓斜面456、和開放空間45 8。影像460顯示依 據本發明原理之影像的被壓縮視圖，其顯示對應的邊緣小 珠移除線452、454、晶圓斜面456、和開放空間45 8。影 像450的晶圓圖案451被修飾如影像460內的圖案464， 因爲其因切線方向的影像壓縮而被減少。影像462是影像 4 60的擬合和變直版本，其顯示相關於已變直之晶圓斜面 456的重新組構的邊緣小珠移除線452、454。 圖1 3至1 5顯示已圖案化晶圓之非壓縮影像470和已 壓縮影像472，以指示本發明的優點。圖13顯示具有已隱 藏圖案4 7 1之已圖案化晶圓的實際影像4 7 0的代表呈現， 而且也顯示本發明的影像例子4 7 2。圖1 4顯示具有許多已 隱藏圖案47 1之已圖案化晶圓和邊緣附近已圖案化之晶圓 的實際影像4 7 0的代表呈現，而且也顯示本發明的影像例 壬—4.12」——1—1—4 一展.孟—邊一緣—服近—圖—案一的^ 4 72之間（特別在點474 )的影像壓縮所降低。圖15顯示 具有已隱藏圖案471之已圖案化晶圓和已圖案化至邊緣之 晶圓的實際影像470的代表呈現。晶圓圖案非常容易看到 ，且和在非壓縮影像470中的影像分析相衝突，所以稍後 會使用在切線方向的壓縮將其過濾掉，以強調邊緣特徵（ 例如邊緣小珠移除線475 )。 參考圖1 6，呈現相交的二邊緣小珠移除線。在一些實 施例中，辨識六個線段A-F。線段A-C融合，且線段D-F 融合，以依據六個線段A-F產生二最佳正弦擬合。在例如 -20- 200820364 圖1 6所示相交的情況，在一些實施例中評估、量測、或 特徵化阻劑「覆蓋（overhang )」。 在一些實施例中，有剩餘的線段可或不可被倂入已產 生之邊緣小珠移除線其中之一。一旦一或更多曲線已被擬 合，則檢查未擬合者、邊界線、和/或已擬合的線段，且 依所希望地將其倂入一或更多已擬合的曲線，例如藉由依 據更寬大之長度或邊緣強度要件重新評估線段，例如依據 和使用者所選之曲線擬合的接近度、特別的強度、關聯性 、最充分地特徵化、或其他選擇。 一旦邊緣小珠移除線已被產生，則需計算已被檢查之 晶圓的各種計量/特徵。例如此計量/特徵包括由邊緣小珠 移除線所形成之周圍的形狀、由邊緣小珠移除線所界定形 狀的中心/質心對晶圓之中心/質心的偏移（R，Θ座標和/或 DELTAX，DELTAY座標）、邊緣小珠移除線的位置是否在 —-特-定或-其_他_公_差_西二_例_姐從阻劑_質」k褒從.邊緣 所界定之已圖案區域的質心至所討論之邊緣小珠移除線等 的周圍資訊、代表所產生之邊緣小珠移除線鋸齒狀或平滑 程度的粗糙度量測或標準偏差値、能決定隻周圍邊緣小珠 移除線的基本形狀（例如圓形、橢圓形等）、多條邊緣小 珠移除線的十字形交叉或相交、平均斜面寬度、斜面寬度 標準偏差、和其他。 在一些實施例中，由已壓縮的邊緣小珠移除線影像創 造「黃金邊緣小珠移除線」影像模型。在檢查過晶圓在統 計上的重要數値且壓縮其影像之後，各已壓縮的影像組合 -21 - 200820364 成統計模型。基於此模型來分析爾後的已壓縮影像。進行 影像減法，並分析「黃金邊緣小珠移除線」影像和檢查影 像之間所餘留的差（例如差影像（d i f f e r e n c e i m a g e ))。 接下來選擇性地進行通過/失敗分析或進行邊緣發現演算 法，以獲得上述的邊緣小珠移除資訊。例如分析（例如經 由差影像）和「黃金邊緣小珠移除線」影像標準有足夠不 同的瑕疵邊緣小珠移除線或其他特徵的差値。 參考圖20-25，其描述辨識、量測、或將邊緣與晶圓 特徵特徵化的相關方法。應瞭解的是，那些實施例和前述 實施例累積在一起閱讀，且各實施例間的特徵可適當地互 換或增加。 將上述謹記在心裡，圖1 7是例示邊緣小珠移除量測 方法200的流程圖。在202，決定一系列已獲得數位影像 中每一者之晶圓50的晶圓邊緣1〇2。在204，決定晶圓邊 .歡—丄0_2_ _上的嚴—0_」_〇丄、在—2立6—l決—定—_晶亂虫A 。在208，決定環繞晶圓50之圓周從晶圓邊緣102至阻劑 邊緣H4的邊緣小珠移除線距離116。方法步驟202-208 中每一者會參考圖18-21進一步描述。 圖18是例示圖17之步驟202的流程圖’其中決定一 系列已獲得數位影像中每一者之晶圓5 0的晶圓邊緣1 02。 在2 2 0，從被檢查的晶圓區域1 0 0獲得一組數位影像。利 用頂部邊緣檢查感應器1 52 ’以獲得邊緣區域環繞整個晶 圓5 0圓周的影像資料。在一些實施例中’頂部邊緣檢查 感應器152具有上達7微米的解析度。頂部邊緣檢查感應 -22- 200820364 器1 5 2獲得很多畫面（例如上達3 6 〇個畫面或更多），以 獲得關於邊緣區域100之整個晶圓圓周的影像。 在222，在第一數位影像或畫面上，擷取直立的投影 。利用一陣列1 6 0 0水平像素和i 2 〇 〇直立像素，產生具有 1 600元件的陣列。來自全部1 600元件的資訊被加在一起 且決定平均投影，藉此產生直立的投影。在224，使用 C anny型的邊緣檢測或其他可接受的邊緣檢測例行程式（ routine )/過濾器（例如LOG例行程式），以發現在直立 影像投影內的最大影像梯度。在226，一旦從邊緣檢測過 濾器之輸出的峰値檢測發現最大影像梯度的位置，則建構 晶圓邊緣追蹤例行程式。 在228，晶圓邊緣追蹤例行程式辨識或群集（cluster )在被處理成副組（subset )之每一列影像上在已發現峰 値後面之給定數目的像素和在峰値前面之給定數目的像素 上—在—2_3_ 0丄該、_副—組—的—|屬—從_紅_扁_色__影_像JI換—至―綠色色彩麗 處理。在232，使用Canny型的邊緣檢測或其他可接受的 邊緣檢測例行程式（routine )/過濾器，以發現在像素的 有興趣線區域內最大梯度。在234，在所蒐集之每一數位 影像或畫面的每一列像素持續追蹤製程。在23 6，所發現 最後的晶圓邊緣位置，用於在新處理有興趣線區域的中心 位置。 發現晶圓缺口的製程（圖20的步驟204 )，較詳細地 例示在圖1 9中。如圖19所示，在240，在每一像素位置 量測梯度向量的方向。在242，辨識在兩預先界定範圍其 -23 - 200820364 中之一具有梯度向量之像素的數位影像。在244，就二預 先界定區域中的每一者，像素位置（X，y)被擬合至直線 方程式y二m X + b。使用遞迴例行方程式消除或剔除不適 當地偏離直線方程式的雜訊或不一致性。在246，就兩已 界定區域的每一者，從線擬合方程式剔除高雜訊的點。在 248’發現兩條線相父 > 其爲晶圓缺口的位置。 決定晶圓中心位置的製程（圖17的步驟206 )，較詳 細地例示在圖2 0中。在2 6 0，決定邊緣位置取樣點。在 2 62，藉由快速傅立葉（Fourier )轉換例行程式，來分析 邊緣位置取樣點。在步驟264，分析快速傅立葉（Fourier )轉換例行程式之諧波（h a r m ο n i c s )的大小和相位角，藉 此決定晶圓中心的位置。 一旦辨識了晶圓邊緣、晶圓缺口、和晶圓中心，則決 定阻劑線、邊緣小珠移除線、或量測（圖1 7的步驟208 ) 此—決—定—較—詳—舰—派倒―敢在麗—2Λ—。就—邊—I小—珠—良 而言，在270，藉由使用晶圓邊緣和目標邊緣小珠移除線 連同邊緣小珠移除尋找公差而界定有興趣的處理區域。在 2 72繼續線邊緣小珠移除線的方法，其中，在每一已蒐集 數位影像或畫面中的處理區域，從紅棕色影像轉換成綠色 色彩供處理。在274，在有興趣的處理區域中擷取直立的 影像投影，類似於參考步驟222所討論的直立影像。在 2 76 ’ Canny型或其他可接受的邊緣檢測例行程式/過濾器 在直立投影上操作。在278，在特定範圍內之過濾器輸出 的峰値位置，被儲存在用於數位影像或畫面的邊緣柱狀圖 -24- 200820364 。一般而言，邊緣柱狀圖是計數器，其辨識相對於預先決 定之臨界値的邊緣位置。柱狀圖的真實邊緣是具有最大數 目計數的位置。在280，在處理所有的影像或畫面以後’ 藉由將每一影像或畫面邊緣柱狀圖加起來，每一畫面的邊 緣柱狀圖被用於創造完整的晶圓邊緣柱狀圖。在282，過 濾晶圓邊緣柱狀圖，且控制迴路決定最接近所選擇給定臨 界値以上之目標邊緣小珠移除位置，以做爲供次一個數位 影像或畫面上第一邊緣小珠移除線用的目標位置。換言之 ，數位影像上最後辨識的邊緣位置和次一個數位影像上第 一邊緣之間的差分離或減半，藉此使真實邊緣位置變窄。 在284，目標邊緣小珠移除値和每一影像或畫面邊緣小珠 移除邊緣柱狀圖相比較。在286，在影像或畫面邊緣小珠 移除邊圓柱狀圖中最接近的値，被選做爲該畫面的邊緣小 珠移除邊緣位置。在2 8 8，目標邊緣小珠移除邊緣位置和 在2 90，被乘後的差値被加到舊的目標邊緣小珠移除邊緣 位置’此產生次一個影像或畫面之新目標邊緣小珠移除邊 緣位置，此係藉由只具有增益的簡單伺服控制迴路來進行 。在292，重複上述的製程，直到所有的數位影像或畫面 被處理。 在2 94 ’在發現數位影像或畫面邊緣小珠移除邊緣位 置以後’可進行精鍊步驟，即從影像或畫面邊緣小珠移除 値量測每一邊緣小珠移除線的粗糖度。 上述程序的一種變化是，以Canny型邊緣檢測器或其 -25- 200820364 他可接受邊緣檢測例行程式/過濾器來過濾綠色緩衝區資 料。檢測器/過濾器的輸出是臨界値。然後可利用臨界資 料的投影。此允許計算邊緣小珠移除線中邊緣像素的數目 ，以觀察邊緣小珠移除線是否有效。 一旦完成上述的製程，然後將邊緣小珠移除位置資料 和已知的製程公差相比較，以做晶圓通過/失敗的決定。 失敗的晶圓可被剝除並再運作，以節省製造室的製造成本 〇 圖22是具有多層阻劑之晶圓300的上視圖。晶圓300 包括晶圓邊緣301、晶圓缺口 304、阻劑層306、307、已 移除阻劑的晶圓區域3 0 8、層3 06的阻劑邊緣3 09、阻劑 層3 07的阻劑邊緣31 1、阻劑層3 06的邊緣小珠移除距離 3 12、和阻劑層3 07的邊緣小珠移除距離3 13。在晶圓300 的製造期間，多層阻劑可在晶圓3 00上曝光。在此等情況 _主丄定_ I蓋—晶—圚1圓—|的ji—多麗緣^瓜 候是重要的，每一邊緣小珠移除線和特定的阻劑層相關。 可利用已顯示和描述之處理步驟的方法，以蒐集有興趣之 每一邊緣小珠移除線的相關個別資訊。因此儘管阻劑層造 成瑕疵但仍可辨識所有的瑕疵和不想要之規格偏差，例如 阻劑應呈現但卻被移除的晶圓區域8、或阻劑應被移除 但卻呈現的晶圓區域1 2 0。藉由重複所顯示和描述的製程 或方法步驟，分離和區別的邊緣小珠移除線可累積於單一 晶圓。 在前述的描述中，爲了簡潔、清楚、和瞭解而使用某 -26- 200820364 些語辭，但並不意涵其有超過習知技藝所要求之不必要的 限制，因爲此等語辭的目的是用於描述，且意欲做寬廣的 解釋。 再者，本發明的描述和圖解使以例子方式，且本發明 的範圍不限於所顯示和描述的精確細節。 現在已描述本發明的特色、發現、和原理、建構和使 用的方式、結構的特徵、和所獲得有利新穎有用的結果； 新穎有用的構造、裝置、元件、設備、零件、和其組合則 記載在所附的申請專利範圍。 【圖式簡單說明】 圖1是依據本發明原理之一實施例半導體晶圓的示意 上視圖，其邊緣小珠已被移除； 圖2是沿著圖1之線2-2的示意剖視圖、和依據本發 __明__原_理_之二_皇_施麗_邊_緣_檢„查_系.統__的_部_分_示_意_圖_丄______________________ 圖3是例示依據本發明原理之一實施例邊緣檢查系統 的上視示意圖； 圖4是圖1之晶圓的部分示意上視圖； 圖5是依據本發明原理之晶圓影像的一般化示意圖； 圖6是依據本發明原理之圖5晶圓影像在影像壓縮以 後的一般化示意圖； 圖7-1 6例示和描述依據本發明原理之影像壓縮和晶 圓邊緣量測/檢查之實施例特徵； 圖1 7是例示一實施例邊緣小珠移除量測方法的流程 -27- 200820364 圖； 圖1 8是例示一實施例決定晶圓邊緣位置的流程圖； 圖1 9是例示一實施例決定晶圓邊緣上缺口位置之方 法的流程圖； 圖20是例示一實施例決定晶圓中心位置之方法的流 程圖； 圖2 1是例示一實施例環繞晶圓圓周決定晶圓邊緣至 邊緣小珠移除位置之距離的方法的流程圖；和 圖22是具有多層阻繼之晶圓的上視圖。 【主要元件符號說明】 5 0 :半導體晶圓 1 00 :邊緣區域 102 :晶圓邊緣 _————LM丄益圓—________________________—__________________________ ______________________________________ — 1 0 6 :晶圓缺口 1 0 8 :阻劑（層） 1 1 〇 :(已移除阻劑的）晶圓區域 1 1 2 :阻劑中心 1 1 4 :阻劑邊緣 1 16 :距離 118:(應有阻劑存在但已被移除的）晶圓區域 1 20 :(應已被移除但卻有阻劑存在的）晶圓區域 130:暴露的頂部區域 -28- 200820364 134 ： 136 ： 138 : 140 ： 150 ： 152 ： 154 ：Semiconductors are often fabricated in wafer form. For reference, 'crystals are often fabricated into multiple layers, and include the notches that are fabricated on the edge of the wafer. ' Manufacture - Build - Order - Segment - Pair - Align - Crystal · - Circle - Use - ° - In - Health-production-half. conductor. The phase-interval-interstitial layer of the crystal B or the resist layer to the wafer enables patterning of the bulk wafer in accordance with subsequent procedures. Typically, a desired amount of bulk resist is applied to the upper surface of the wafer during wafer rotation. When the wafer is rotated, the resist material extends radially outward from the center and spreads toward the edges of the semiconductor, causing the circle to be substantially coated with a layer of resist. Excessive resist will build up and form a resist hillock or bead on the outer edge of the bulk wafer. For the "edge bead" of the consumer, a conventional coating system called edge bead removal (EBR) can be used. The chemical edge bead removal (EBR) unit includes a nozzle that dispenses a resist called edge beads to remove fluid from the semiconductor wafer. The solvent dissolves or decomposes the resist and allows the resist to be easily removed from the edge of the semiconductor wafer. In the optical edge bead removal unit, the resist at or near the edge of the semiconductor crystal is exposed to light. The exposed resist is removed during the subsequent development process. If the wafer is not centered during edge bead removal, the remaining resist layer cannot be centered relative to the wafer. In addition, changes in the removed resistive dose can affect the change in the distance of the resist edge from the edge of the wafer. Different edge bead removal units and/or multiple edge bead removal processes, for example, can result in uneven stacking of substrate layers at or near the edges of the semiconductor wafer. In any case, because the resist layer of the wafer is offset, a number of unwanted effects are produced. For example, a random or uneven stack of substrate layers can bulge and be undesirably redeposited on the semiconductor wafer. The re-deposited substrate material can contaminate the semiconductor wafer and cause the integrated electricity formed on the wafer - ° - - - - - - - - - " - ---------— ----------------------—* [Invention] The present invention relates to an inspection and measurement, in particular An edge check and measurement. [Embodiment] There are many reasons to prove that wafer edge inspection and measurement are important. For example, a process engineer needs to be able to measure the edge bead removal line and ensure that the process is properly advanced. For example, the edge removal line is created by the flow resistance of the entire wafer surface. In the entire edge exclusion zone, a bead is formed on the edge of the wafer by the resist. After patterning and rot, the resist is removed and the edge bead removal line is left depending on the process being performed. By measuring the geometry of these lines relative to the wafer and wafer edges, for example, these process engineers can ensure that their production processes operate properly. Thus, in general terms, edge construction feature measurement systems and methods in accordance with the principles of the present invention are used to characterize a resist layer that approaches the outer edge of the wafer edge and that will approach other wafer edges. The circular construction features are characterized as desired. Some embodiments include finding the relative distance from the edge of the semiconductor wafer to the edge of the resist layer, such as where the resist is removed around the circumference of the wafer. For reference, although it should be understood that the principles of the present invention are applied to the resist edge formed by various wafer manufacturing processes (including the edge bead removal process, but are not limited thereto), but the so-called resist edge system Refers to the "edge bead removal line". In some embodiments, a plurality of edge construction features are provided - 'example - sister - crystal edge - edge -, - wafer - missing - Ξ or - flat - edge - and - or ~ more - edge - edge small - Beads - remove the line. The method also includes finding the center of the wafer, and/or the center of one or more resistive layers, and, if desired, the relative offset between the centers of the one or more resistive layers of the wafer center. As a aid to understanding the discussion below, it should be noted that some embodiments of the edge construction feature measurement system and method include, for example, obtaining a series of digital images of the wafer edge with a new digital inspection camera located in a radially offset rotary table. . In some embodiments, the entire outer circumference of the wafer is imaged in a continuous and/or stepwise manner. The wafer notch location, wafer center, resistive layer center, edge bead removal line location, crystal -6 - 200820364 round edge location, and other structural features are selectively extracted from this image data. For example, the center of the wafer, the center of the resist layer, the position of the camera coordinate system, and/or the location of the wafer notch are selectively determined. As will be described in more detail below, images of the wafer edges are cumulatively compressed and evaluated to better evaluate various structural features. In some embodiments, the distance from the edge of the wafer to the edge bead removal line where the resist has been removed is evaluated around the entire circumference of the wafer being compressed. As implied above, any number of Φ resist layers can be present on the wafer, each resist layer having edges of the removed beads and defining edge bead removal lines. Thus, in some embodiments, where applicable, the complex edge bead removal lines of interest are identified or tracked. In addition, it is to be noted that the information obtained by imaging the wafer (e.g., the center position of the wafer being processed) can be used in related inspection processes and systems. For example, the wafer center position can be used to report and analyze wafer defects, or to allow inspection of phases. Set the camera to use the edge of the wafer (positive. . . . . - often - edge - edge -) - wheel - gallery or - side - edge - into - like - 'to chase - vertical - positive _ often - edge' very - first § noon - phase • machine maintenance from the wafer The focal length of the normal edge. Thus, in some embodiments, the information gathered by the edge bead removal inspection system and method is used as part of a larger and more detailed wafer feature system or inspection measurement. Referring to the drawings, FIG. 1 illustrates a top view of a semiconductor wafer 50. The wafer 5 〇 defines the edge region 1 〇〇 and includes the wafer edge 1 晶圆 2, the wafer center 104, the wafer gap 106, a layer of resist 108, the wafer region with the resist removed 1 1 0 , Resistor Center 1 1 2, Resistor Edge 1 1 4, Wafer Edge 102 and Resistor Edge 1 1 4 Distance 1 1 6 , Wafer Area with Resistive Retention but Removed 1 18 8. Wafer area that should have been removed but has a resist present 200820364 120 ° Figure 1 illustrates that the resist center 1 1 2 is offset from the wafer center 104. This inconsistency is often caused by operator or mechanical errors during the formation of the resist 108, and/or during the removal of a portion of the resist 108. As previously suggested, the position of the wafer 50 at the center of rotation during manufacture affects the position of the resist relative to the center of the wafer 1 〇4. For example, in some embodiments, the wafer 50 is secured to a collet (not shown) during various automated fabrication steps. However, due to automation or other errors, the center of rotation is sometimes not aligned with the center of the wafer. When the center of rotation and wafer center 104 are not aligned, a resist layer (e.g., resist layer 1 〇 8 ) is eccentrically disposed relative to wafer 50. Figure 1 illustrates that the resist center 112 is exaggerated from the wafer center 104 so that misalignment between the two centers 1 〇 4, 1 1 2 can be easily discerned. However, it should be noted that the misalignment between the two centers 104, 112 is often difficult for humans to observe with the naked eye. After this understanding, you should also pay attention to the wafer edge and edge...1-0 2- and -resistance-agent-edge-14 4 . The ----------weeks are not consistent. It is also noted that during wafer fabrication, it is also possible to create regions such as wafer regions 1 18 (which should include resist but not included). For example, in some manufacturing processes, the resist 108 of the wafer region 118 is removed for a number of reasons, including various manufacturing or processing inconsistencies. In some embodiments, a germanium region or a potential germanium region (e.g., wafer region 120) is also identified during the edge inspection process. Similarly, regions such as wafer regions 126 are also selectively identified, which should have no resist but have a resist. For reference, wafer area 1 20 can also be generated, for example, due to manufacturing tolerances or process inconsistencies. -8- 200820364 Figure 2 is an enlarged view of the edge region 100 along line 2-2 of Figure 1. The edge region 100 includes a resist edge i丨4, an exposed top region 1 3 0 of substantially no resist 1 〇8, a wafer edge 1 〇2, and also a substantially substantially resistive layer (eg, resist 1) 〇8) The bottom area of the wafer is 1 3 4 . The wafer edge 102 defines a top bevel 136, a wafer edge normal 138, and a bottom bevel 140. 3 is a schematic illustration of an edge inspection system 150 consistent with the principles of the present invention. The edge inspection system 150 includes a top edge sensor 152, a bottom edge sensor 154, a standard edge sensor 156, a controller 158, a base 160, and a table assembly 162. The top edge sensor 152 includes a camera 164, the standard edge sensor 156 includes a camera 166, and the bottom edge sensor 154 includes a camera 168. The table assembly 162 includes a motor 170, an encoder 172, and a support plate 174. Motor 170 is coupled to encoder 172 and support plate 174 so motor 170 is adapted to rotate support plate 174. Code - device - 1-7-2 - mention - supply - g ten - number use - in - control - system - horse - up - - bit - set -. The support plate 1 74 supports the wafer 50 during the - crystal-hidden-5 0--rotation-rotation and imaging. Controller 158 is electrically coupled to top edge sensor 152 via communication link 176, electrically coupled to standard edge sensor 156 via communication chain 178, and electrically coupled to the bottom via communication chain 1800 An edge sensor 1 54 is electrically coupled to the table 162 via the communication link 1 82. Controller 158 controls top edge sensor 152, standard edge sensor 156, bottom edge sensor 154, and table assembly 162 via communication chains 176, 178, 180, 182 to inspect edge regions 1 〇〇. In some embodiments, the edge region 100 is inspected from the top, the standard -9-200820364, and the bottom direction with the edge inspection system 150, although other orientations and angles are also contemplated. In general, the edge inspection system 150 performs a top inspection of the edge region 100 (FIG. 2) by the top edge sensor 152, and performs an edge region 100 of the wafer 50 by the bottom edge sensor 154. The bottom check, and the standard inspection of the edge area 100 is performed by the standard edge sensor 156. The edge inspection system 150 is inspected and/or measured along the edge region 100 of the wafer 50, including the resist edge 144, the exposed top region 1300, and the wafer region 〇2. In some embodiments, the edge inspection system also inspects and/or measures the top bevel 136 of the wafer edge 102, the wafer edge standard 138, and the bottom slope 140. Referring to Figure 2, the top edge sensor 152 has an inspection area 184, the standard edge sensor 156 has an inspection area 186, and the bottom edge sensor 154 has an inspection area 188. Thus, in some embodiments, the edge inspection system 150 along the edge region 100 of the wafer 50 as desired to check - and / or look - test - 1 includes - resistance - unique 4 - 〇 - 8—,—resistance—agent edge—,—. 暴—獯——top;—area 1 3 0, top bevel 1 3 6 , edge standard 1 3 8 , bottom bevel 1 40, and wafer bottom area 1 34. In some embodiments, dark areas and bright areas are illuminated to inspect wafer features, such as to assess the location of the resist 1 14 around the circumference of the crystal 50. Referring to Figures 4-1, some embodiments of edge inspection in accordance with the principles of the present invention include obtaining a plurality of images around a wafer edge region 100, and each image being a pixel having a first dimension X and a second dimension y (pixel) array 190, compressing each pixel array 1 90 in the first dimension X, stitching the compressed pixel array 190 into an edge image, and analyzing the edge -10- 200820364 image to One or more edge features are identified, such as resist edge 1 14 and wafer edge 102. 4 illustrates a portion of the wafer 50 during wafer acquisition of the image by the wafer inspection system 150, particularly when the top edge sensor 1 5 2 is rotated (eg, in the direction of rotation r). The edge area 1 〇〇 Measure 'to obtain an image near the edge area 1 0 0. In some embodiments, an image is taken around the entire edge region 100. If desired, overlay images to help ensure that the entire edge area is covered, or increase the amount of image information obtained for better resolution (as described in more detail below), although not overlapping Images, separate images, combinations thereof, and the like are also contemplated by the present invention. In one embodiment, for a 200 mm magnification mechanism, 128 digital images are obtained to ensure a 3 60 degree image of the covered wafer 50. However, the top edge inspection camera 1 52 selectively obtains more numbers or more... a few - of the picture - face, as desired - a view - like - up - violation - 3 -6-0 - draw - face - Or - more - an image of the entire circumference of the wafer 50, or a higher resolution edge image. In some embodiments, the top edge inspection camera 152 has a resolution of up to 7 microns. It is to be noted that amplification of larger magnifications requires additional images, while magnification of smaller magnifications requires less imagery to fully image the edge region 10 . Therefore, other combinations of magnification and number of images are also desirable for the present invention. 5 is a rough representation of the pixel array 190 corresponding to the image data of the inspection region 184 taken by the top edge sensor 152. In some embodiments, a bottom edge sensor 156 is used to perform a similar data/process to image or characterize the -11 - 200820364 wafer 5 G bottom. Nonetheless, the pixel array 192 selectively includes luminance data for associated locations such as wafer edge 102, top bevel 136, and resist edge 144. The pixel array 丨9 〇 defines a first dimension X and a second dimension γ. As shown, the X-dimensional and wafer 50 (especially the wafer edge 1〇2) are substantially tangent, and the gamma dimension is substantially radially aligned with the wafer 50, although the other orientations of the pixel are also What the invention wants. Pixel 1 90 includes grayscale luminance information, although other types of information (e.g., color data) are desired in other embodiments. During the acquisition of the image, a number of pixel arrays 190 are obtained, and each pixel of the pixel array 190 has a luminance 値. As described below, each pixel array is sequentially spliced together before or after compression to properly align the complex pixel array to form an image image of the edge region 100. In other embodiments, each digital image corresponds to a pixel array (also referred to as an image image) having 160 water-level-image-primimeter-crossing the first dimension X, -~ and - 横-越-第-三-次-带年-- 1-2 0 偃 直 - straight - Fen] 象-素一-- although - it - his pixel array is also thought of the present invention For example, the pixel array is selectively 1920 pixels traversing the first 兀X and 1 〇78 8 traversing the second dimension Y. In some embodiments, the 1 60 〇 X 1 2 0 0 array corresponds to a 200 mm image magnification structure. However, it should be understood that if a larger magnification (e.g., 300 mm structure) is used, a larger number of digital images are required to completely image the edge region 100 along the circumference of the wafer 50. Similarly, if a smaller magnification (e.g., 100 mm) is used, a smaller number of digital images are needed to completely image the edge region 1 〇〇 along the circumference of the wafer 50. -12- 200820364 In some embodiments, one or two passes through the circumference of the wafer 50 are completed and data is collected in a substantially continuous and/or stepwise manner. In some embodiments with secondary pass, the first pass is a bright zone data and the second pass is a dark zone profile. If desired, wafer 50 is rotated more than one turn (turn) or more than two turns, such as 1. 1 lap, 2. One lap, or other laps as desired, to help ensure some overlap at the start and end of the image, and/or to obtain the desired amount of image information. 6 is a compressed image 192 produced by compressing a pixel array 1 90 that traverses a first dimension X. In some embodiments, compression is only obtained in the first dimension X, and the second dimension Y is not compressed. . The compression across the first dimension X is accomplished by various methods. In some embodiments, pixel array 1 90 is compressed by an average brightness 对应 corresponding to pixel array 1 90 across first dimension X to produce a single line of pixel luminance 第二 in second dimension Y; although in some implementations In an example, it is desirable for pixel array 1 90 to be compressed into more rows of pixels. End-tube--this borrow--by-cross-over-the first ^^-time-7E-X-compression one------------------ Random variations, changes in brightness induced by wafer patterning, and other unwanted image data effects. Thus in some embodiments, each image is compressed by the average pixel column (in other words, across the first dimension X) and results in many images being full depth in the second dimension Y, but only one in the first dimension X The pixel is wide. In this manner, variations across the first dimension (e.g., random image changes or wafer patterning) can be reduced to emphasize the regular features that extend substantially along the first dimension X. Thus, image compression along the first dimension X is used, for example, to perform noise and/or unwanted edge suppression. • 13-200820364 Various additional features of image compression and wafer edge measurement/inspection consistent with the principles of the present invention are illustrated and described in Figures 7-16. In general, image compression helps remove or reduce wafer element patterning, random variations in image data, or other targeted information associated with unwanted image information. These patterns and other random variations can cause difficulties in finding resist edge 1 14 , other edge bead removal lines, and other edge features. In some embodiments, after image capture and compression, the images are concatenated (eg, by a splicing operation) into a single composite image, also referred to as an image image, edge image, edge of the compressed image. Beads remove the image. Referring to FIGS. 7 and 8, in some embodiments, the wafer edge 102 and the top edge bevel 136 are located within the composite image, and the composite image is normalized based on the discovered wafer edge 102, such that the composite image is The discovered wafer edge 102 can be displayed in a straight line. If necessary, when the image is a circular and continuous object (ie, wafer 50), by shifting the edge-to-complex-image--a pretty or another - Knee - Complex - Heap - Shadow - The wafer notch 106 or flat edge appears to be discontinuous in the center. In some embodiments, an edge discovery algorithm/method is performed to determine the edge bead removal line. In some embodiments, a Canny edge detector and a Sob el edge detector are applied. Based on the starting pixel characteristics and edge critical conditions (cf. some examples), if the selected edge critical condition is met, the line segment grows into a line segment group by adding pixels. In some embodiments, the user is allowed to adjust the upper and lower edge gradient thresholds, the edge strength (e.g., average line segment gradient) thresholds, and/or the line segment thresholds to discard or emphasize particular line segments. Thus in some embodiments -14-200820364, only the special size/edge strength/gradient is processed in subsequent steps. In some embodiments, the line segment strength of the entire segment is analyzed to determine the contour of the line segment, which can indicate edge bead removal lines and/or noise, and allow for discarding during or before edge fitting (fitting) Line segment. The first line segment is selected and the line segment is fitted with a curve. In some embodiments, the edge bead removal line exhibits a good sinusoid. So select the sinusoid to fit the segments. However, other types of curves or lines may be selected for this fitting step. In some embodiments, subsequent segments are identified and the distance (average, intermediate, or and/or absolute) of the first curve-fitted line segment is calculated to see See if they and the first fit curve are a good fit. In the case where the subsequent line segment is a good fit, the line segment is joined to the first line segment and the subsequent curve is fitted. This process continues until the edge bead removal line is characterized. The case where the line segment is too far away from the formed edge bead removal line (such as another critical position - quasi-decision - definite - 4 -, - new music - line can - pseudo-select selected genus - segment - Continue until the desired number of line segments or image frames, such as substantially all image frames, are included in the fitted curve. Figure 7 A, 7 B shows image capture and compression, fit image, and composite image Example Figure 7A represents an example of a portion of the wafer and its image obtained during image capture described above with reference to Figures 4 and 5. Figure 7A shows a schematic of wafer 400 and edge 402, indicated corresponding to wafer edge 4 The plurality of locations of 〇2 are captured image 404. Figure 7A also shows an example of a single uncompressed image 406 taken from wafer edge 402. Figure 7B represents the compressed and simulated after processing the complex captured image 404 The wafer edge -15-200820364 is an example of the edge 402. More specifically, Figure 7B schematically shows the edge 402 of the wafer 400, which is presented as a line 408 consisting of a series of images 404. taken from line 408 Line 404 of 404, shown as being fitted to the compressed image The line segment can include any number of compressed images, unwrapped wafer edges 408. Examples of compressed images 4 1 2 can be edited by various methods. For example, a single image 406 can be compressed first and compressed. Image 4 1 2. In addition, a single image can be first reduced to a compressed image 4 1 2 . The image 412 that is compressed and spliced together allows for wafer level alignment, rather than just considering one image and one painting. The entire wafer tracks the edge bead removal line, not the warp surface. The algorithm can be used to calculate the exact position of the edge of the wafer - the 孺 - - - 寻 - 蒉 - all - edge - edge - small - beads - Alternate - Line Off - Off. Figure 8 shows the image obtained when the center of the wafer 400 is not centered on the axis of the wafer. The offset between the two axes 4 1 4, 4 1 6 A concentric circle with a small edge offset from the edge 402 of the wafer is caused, and the edge bead is centered on the resist axis. The image of the junction of the entire edge is displayed as an image 4 1 5 and the edge bead is moved in the chuck The edge of the wafer on the center of the bead removal line is shown in the example, wafer 4 0 2 The edge is also not in a straight line. This example shows a roughly circular example of a fitted image 4 1 2 that is fitted to it. It consists of a single uncompressed shadow, then fits into a joint, and is then pressed to examine the crystal. The round face changes. It can be divided by each individual drawing and its wafer-crystal-circle-edge--edge-to-line 4 1 4 and the resistive example of the resist removal line 4 1 8 4 1 8 has been compressed and has been stripped of the line image. There is no sinusoid. Here, the wafer edge 4 02 can be straightened using the calculation -16-200820364 method to make the crystal as shown in image 419. The circular position is on the center of the collet' and the compressed, joined, and straightened image of the entire edge of the edge 042. Image 4 1 9 may present the distance of edge bead removal line 418 from wafer edge 402. In image 419, wafer edge 420 has been straightened on the edge bead removal image and the resist is offset from the center of the wafer. When the edge bead removal line is gradually sinusoidal, the offset becomes larger. 9A, 9B are schematic illustrations of examples of images of unpatterned wafers having a single edge bead removal line. Figure 9A shows another example wafer 400 centered on wafer axis 414, and resist axis 416 is not centered on the rotating chuck. Figure 9B shows a compressed, joined, and straightened image 420 corresponding to the circumference of the entire edge 402 with the presented edge bead removal line 422 and additional features. The edge bead removal line 422 that has been presented is a compressed, joined line on the edge of the wafer that has been straightened, which corresponds to the actual edge bead removal line 418. The image 420 is also presented with -------- inner-public-line--4~2~4- and -outer-tolerance: ~^泉——4 2-6 & inner-male ^. Difference line r - 4 2 4--boundary-fixed-better-edge-edge bead removes the minimum distance from the center of the wafer, outer tolerance line 426 defines the preferred edge bead removal line from the center of the wafer The maximum distance. The edge bead removal line between these two tolerances includes the sections within the manufacturing specifications. This example also shows the characteristics of the sliding magnification 43 2 . Sliding magnifying rod 432 in this example includes a scale 434 that indicates the distance from the center of the wafer (e.g., in millimeters), although it should be understood that any suitable measuring scale can be used. The slide-up zoom lever 432 can also include a window 436 that magnifies the original material near the edge 402 of the wafer 400 at the edge bead removal line 422 that substantially corresponds to the overlap of the slide-amplifier rod 432. In another example, the slide -17-200820364 dynamic zoom bar does not overlap the image 4 2 0 ' but is displayed in a separate window. This example provides a list of measurement data that can be learned from the image. Internal and external tolerances 424, 426 can be defined by the user and can be presented by various indicators, such as different colors, shading, or the like. The best circle fits can be applied to the data of the compressed image presented on a circular wafer. In another embodiment, the presentation of a circle may be formed by a best fit sinus applied to the image of the joined edge image or the edge bead data. In Fig. 9A, the portion of the edge bead removal line 418 outside the gauge is shown as portion 428, and the portion of the edge bead removal line within the gauge is shown as portion 430. The center offset, or the displacement between the axes 4 1 4 and 4 16 , can also be obtained or displayed. This example provides a list of measurement data that can be learned from the image. Internal and external tolerances 424, 426 can be defined by the user and can represent millimeters from the center of the wafer. In addition, the edge bevel width 4 3 8 can also be measured in millimeters, and the edge beads can be measured to remove sharpness factors, standard deviations, or both. It can be measured by Yan-屯—心i—414_ __—x—seat—label——X------------------------ The offset between the axis j springs j 4 1 6 . Or radial measurements can be made with a radius of millimeters 値 and angle. Other edge bead removal statistics can be used to quantify the image, such as average, intermediate, multimodal data (e.g., red, green, and blue data), and the standard deviation of the minimum and maximum chirps including the free. Other features of the system can be imaged. In the example, the standard deviation can be used to determine the roughness of the edge bead removal line. If the edge bead removal line is not complete, then the best sinusoidal fit or best round can be used to complete the line. Image compression or filtering techniques can be used to measure the undercutting of the edge bead removal line. The -18-200820364 edge bead removal line can be analyzed based on the image of the bright and dark areas. The edge bead removal line image can be based on color images such as red, green, and blue channels. Results can be output in a number of formats that can be formatted to be compatible as part of a larger and more complete wafer characterization system, examples of which include harmonious ASR with images, text, Excel, and KLARF. Figure 10 shows a schematic diagram of an image example of an unpatterned wafer with multiple edge bead removal lines. In the illustrated example, the multiple edge bead removal lines 423, 425 do not intersect each other, or one of the 423 is always closer to the center than the other 42 5 at all points around the wafer. The user defined edge bead removal line 427 can be determined and the user can select the desired edge bead removal line to track or identify from various potential fitted lines. In the case where the edge bead removal lines intersect, an alert (eg, as an image) is presented based on the number of intersecting points and associated data. Figure 11 also shows the air image of the unpatterned wafer with the edge bead removal line _ _ _ _ _ _ _ _ _ _ _ L _ _ _ _ _ _ _ _ _ _ _ _ _ . Move the __ remaining_ line to provide multiple points 43 8 along the presented edge bead removal line. The statistical freezer 440 is eliminated and the virtual edge bead removal line is provided using the best sinusoidal fit or best rounded fit. The best circular fit can be derived from the best sinusoidal fit of the previous application. Qualitative and quantitative data can be derived from this virtual line. In the case where the resist is perfectly centered and the edge of the wafer is straightened, the resist will also be straight and the fit will include a sinusoid with zero amplitude. Figure 12 shows a representative representation of the actual image obtained with an example of the present invention. Image 450 is an enlarged view of a patterned wafer containing pattern 451 - 200820364, including first edge bead removal line 452, second edge bead removal line 454, wafer bevel 456, and open Space 45 8. Image 460 shows a compressed view of an image in accordance with the principles of the present invention showing corresponding edge bead removal lines 452, 454, wafer bevel 456, and open space 45 8 . The wafer pattern 451 of the image 450 is modified as the pattern 464 in the image 460 because it is reduced by image compression in the tangential direction. Image 462 is a fitted and straightened version of image 460 that displays the reconstituted edge bead removal lines 452, 454 associated with the straightened wafer bevel 456. Figures 13 through 1-5 show the uncompressed image 470 and the compressed image 472 of the patterned wafer to illustrate the advantages of the present invention. Figure 13 shows a representative representation of an actual image 410 of a patterned wafer having a hidden pattern 471, and also shows an image example 742 of the present invention. Figure 14 shows a representative representation of an actual image of a patterned wafer having a plurality of hidden patterns 47 1 and a patterned wafer near the edges, and also shows an image example of the present invention. 12"——1—1—4 Exhibition. The image compression between Meng-Bian-Yi-Yi-Yi---------------------------------------------------------- Figure 15 shows a representative representation of an actual image 470 of a patterned wafer having a hidden pattern 471 and a wafer patterned to the edge. The wafer pattern is very easy to see and conflicts with image analysis in uncompressed image 470, so it will be filtered out later using compression in the tangential direction to emphasize edge features (eg edge bead removal line 475) ). Referring to Figure 1-6, the intersecting two edge bead removal lines are presented. In some embodiments, six line segments A-F are identified. The line segments A-C merge and the line segments D-F merge to produce a two-optimal sinusoidal fit from the six line segments A-F. In the case of, for example, -20-200820364 shown in Fig. 16. In some embodiments, the resist "overhang" is evaluated, measured, or characterized. In some embodiments, the remaining line segments may or may not be broken into one of the edge bead removal lines that have been created. Once one or more curves have been fitted, the unfit, boundary, and/or fitted line segments are checked and desirably broken into one or more fitted curves, such as The line segment is re-evaluated by a wider length or edge strength requirement, such as proximity, special intensity, relevance, most adequate characterization, or other selection based on the curve selected with the user. Once the edge bead removal line has been generated, the various meters/features of the wafer that has been inspected need to be calculated. For example, the metering/feature includes the shape of the perimeter formed by the edge bead removal line, the center/centroid of the shape defined by the edge bead removal line versus the center/centroid of the wafer (R, Θ Coordinate and / or DELTAX, DELTAY coordinates), the position of the edge bead removal line is - special - or - its _ he _ public _ poor _ West two _ example _ sister from the resistance _ quality" k褒 from . The surrounding information of the center of the patterned area defined by the edge to the edge of the edge of the bead removal line in question, the roughness measurement or standard deviation of the edge of the resulting bead removal line or the degree of smoothness, It is possible to determine the basic shape of only the peripheral edge bead removal line (eg, circular, elliptical, etc.), the cross-shaped intersection or intersection of multiple edge bead removal lines, the average bevel width, the standard deviation of the bevel width, and others. In some embodiments, the "golden edge bead removal line" image model is created by removing the line image from the compressed edge bead. After examining the important statistics of the wafer and compressing its image, each compressed image combination -21 - 200820364 is a statistical model. Based on this model, the compressed image is analyzed. Perform image subtraction and analyze the remaining difference between the "Golden Edge Bead Removal Line" image and the inspection image (for example, the difference image (d i f f e r e n c e i m a g e )). Next, a pass/fail analysis or an edge finding algorithm is selectively performed to obtain the edge bead removal information described above. For example, analysis (e.g., by poor image) and "golden edge bead removal line" image standards have sufficiently different margins for edge bead removal lines or other features. Referring to Figures 20-25, a method of identifying, measuring, or characterizing edge and wafer features is described. It will be appreciated that those embodiments and the foregoing embodiments are cumulatively read together, and features between the various embodiments may be interchanged or added as appropriate. Keeping the above in mind, Figure 17 is a flow chart illustrating an edge bead removal measurement method 200. At 202, a series of wafer edges 1 〇 2 of wafer 50 for each of the digital images has been determined. At 204, the wafer edge is determined. Huan-丄0_2_ _ on the strict -0_" _ 〇丄, in the -2 standing 6-l decided - set - _ crystal worm A. At 208, it is determined that the edge bead removal line distance 116 from the wafer edge 102 to the resist edge H4 around the circumference of the wafer 50. Each of method steps 202-208 will be further described with reference to Figures 18-21. Figure 18 is a flow chart illustrating the step 202 of Figure 17 in which a wafer edge 102 of a wafer 50 of each of a series of digital images has been determined. At 2 2 0, a set of digital images is obtained from the wafer area 100 to be inspected. The top edge inspection sensor 1 52 ' is used to obtain image data of the edge region surrounding the circumference of the entire circle 50. In some embodiments the 'top edge inspection sensor 152 has a resolution of up to 7 microns. Top Edge Inspection Sensing -22- 200820364 1 1 2 Obtain a lot of pictures (for example, up to 3 6 pictures or more) to get an image of the entire wafer circumference of the edge area 100. At 222, an upright projection is captured on the first digital image or image. An array of 1 600 elements is produced using an array of 1 600 horizontal pixels and i 2 〇 〇 upright pixels. Information from all 1 600 components is added together and the average projection is determined, thereby producing an upright projection. At 224, a C anny type edge detection or other acceptable edge detection routine/filter (e.g., LOG example stroke) is used to find the maximum image gradient within the upright image projection. At 226, once the peak of the output of the edge detection filter detects the location of the largest image gradient, the wafer edge tracking routine is constructed. At 228, the wafer edge tracking routine is identified or clustered on a column of each of the subsets that are processed into a subset, a given number of pixels after the peak has been found and given in front of the peak The number of pixels - in the -2_3_ 0 丄, _ sub-group - - | genus - from _ red _ flat _ color _ _ shadow _ like JI change - to "green color processing. At 232, a Canny-type edge detection or other acceptable edge detection routine/filter is used to find the largest gradient in the region of interest of the pixel. At 234, the process is continuously tracked for each column of pixels or images of each of the collected pixels. At 23, 6, the last wafer edge location was found to be used at the center of the newly processed area of interest. The process of finding the wafer notch (step 204 of Fig. 20) is illustrated in more detail in Fig. 19. As shown in Figure 19, at 240, the direction of the gradient vector is measured at each pixel location. At 242, a digital image of a pixel having a gradient vector in one of two predefined ranges -23 - 200820364 is identified. At 244, for each of the two pre-defined regions, the pixel position (X, y) is fitted to the line equation y two m X + b. Use the recursive routine to eliminate or eliminate noise or inconsistencies that do not properly deviate from the linear equation. At 246, for each of the two defined regions, the point of the high noise is removed from the line fitting equation. At 248', the two line fathers > are found to be the locations of the wafer gaps. The process of determining the center position of the wafer (step 206 of Fig. 17) is illustrated in more detail in Fig. 20. At 2 60, the edge position sampling point is determined. At 2 62, the edge position sampling points are analyzed by a fast Fourier transform routine. At step 264, the magnitude and phase angle of the harmonics of the Fourier transform routine (h a r m ο n i c s ) are analyzed to determine the position of the wafer center. Once the wafer edge, wafer notch, and wafer center are identified, the resist line, edge bead removal line, or measurement is determined (step 208 of Figure 17.). Ship - sent down - dare in Li - 2 Λ -. In the case of - edge - I small - bead - good, at 270, the processing area of interest is defined by using the wafer edge and target edge bead removal lines along with the edge bead removal to find tolerances. The method of continuing the line edge bead removal line at 2 72, wherein the processed area in each of the collected digital images or pictures is converted from a reddish brown image to a green color for processing. At 274, an upright image projection is captured in the processing region of interest, similar to the upright image discussed with reference to step 222. The 2 76 ‘ Canny type or other acceptable edge detection stroke/filter operates on an upright projection. At 278, the peak position of the filter output within a particular range is stored in an edge histogram for a digital image or picture -24-200820364. In general, an edge histogram is a counter that identifies the edge position relative to a predetermined critical threshold. The true edge of the histogram is the position with the largest number of counts. At 280, after processing all of the images or images, by adding each image or picture edge histogram, the edge histogram of each picture is used to create a complete wafer edge histogram. At 282, the wafer edge histogram is filtered, and the control loop determines the target edge bead removal position closest to the selected given threshold , as the first edge of the image or the first edge of the picture. The target position for the line. In other words, the difference between the last recognized edge position on the digital image and the first edge on the next digital image is separated or halved, thereby narrowing the true edge position. At 284, the target edge bead is removed and compared to each image or picture edge bead removed edge histogram. At 286, the closest edge of the image in the edge of the image or the edge of the picture is selected as the edge of the picture to remove the edge position. At 2 8 8, the target edge bead removes the edge position and at 2 90, the multiplied difference is added to the old target edge bead removal edge position 'This produces a new image or a new target edge of the image. The bead removes the edge position, which is done by a simple servo control loop with only gain. At 292, the above process is repeated until all digital images or pictures are processed. The refining step can be performed at 2 94 'after the discovery of the digital image or the edge of the picture to remove the edge position. That is, the image is removed from the image or the edge of the picture. The roughness of each edge of the bead removal line is measured. One variation of the above procedure is that the Canny-type edge detector or its -25-200820364 can accept edge detection routines/filters to filter the green buffer data. The output of the detector/filter is critical. The projection of the critical data can then be utilized. This allows the number of edge pixels in the edge bead removal line to be calculated to see if the edge bead removal line is valid. Once the above process is completed, the edge bead removal position data is then compared to known process tolerances for wafer pass/fail decisions. Failed wafers can be stripped and re-operated to save manufacturing chamber manufacturing costs. Figure 22 is a top view of wafer 300 with multilayer resist. The wafer 300 includes a wafer edge 301, a wafer notch 304, a resist layer 306, 307, a wafer region 308 with a resist removed, a resist edge 3 09 of the layer 306, and a resist layer 307. The edge of the resist 31 1 , the edge bead removal distance 3 12 of the resist layer 306, and the edge bead removal distance 3 13 of the resist layer 3 07. During fabrication of wafer 300, a multilayer resist can be exposed on wafer 300. In this case, the _ main cover _ I cover - crystal - 圚 1 circle - | ji - Dolly ^ melon is important, each edge bead removal line is associated with a specific resist layer. The method of the processing steps that have been shown and described can be utilized to collect relevant individual information for each edge bead removal line of interest. Therefore, despite the defects caused by the resist layer, all defects and unwanted specification deviations can be identified, such as the wafer area 8 where the resist should be present but removed, or the wafer that the resist should be removed but presented. Area 1 2 0. The separated and differentiated edge bead removal lines can be accumulated on a single wafer by repeating the process or method steps shown and described. In the foregoing description, the use of the terms -26-200820364 for the sake of brevity, clarity, and understanding does not imply that there are unnecessary limitations beyond those required by the prior art, as the purpose of such words is Used for description and intended to be broadly interpreted. Furthermore, the description and illustrations of the present invention are intended to be illustrative, and the scope of the invention The features, discoveries, and principles of the present invention, the manner of construction and use, the features of the structure, and the advantageous and novel useful results obtained are now described; the novel and useful structures, devices, components, devices, parts, and combinations thereof are described In the scope of the attached patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic top view of a semiconductor wafer with its edge beads removed, in accordance with an embodiment of the present invention; FIG. 2 is a schematic cross-sectional view taken along line 2-2 of FIG. And according to the hair __ 明__原_理_二二_皇_施丽_边_缘_检„查_系. Figure 3 is a top plan view illustrating an edge inspection system in accordance with an embodiment of the present invention; Figure 4 is a partial schematic view of the wafer of Figure 1 Figure 5 is a generalized schematic view of a wafer image in accordance with the principles of the present invention; Figure 6 is a generalized schematic view of the wafer image of Figure 5 after image compression in accordance with the principles of the present invention; Figure 7-1 6 illustrates and describes Embodiments of image compression and wafer edge measurement/inspection of the inventive principle; FIG. 17 is a flow -27-200820364 illustrating an edge bead removal measurement method of an embodiment; FIG. A flow chart for determining the position of the edge of the wafer; FIG. 19 is a flow chart illustrating a method of determining the position of the gap on the edge of the wafer in an embodiment; FIG. 20 is a flow chart illustrating a method of determining the center position of the wafer in an embodiment; 1 is a flow chart illustrating a method of determining the distance from the wafer edge to the edge bead removal location around the wafer circumference of an embodiment; and FIG. 22 is a top view of a wafer having multiple layers of relief. [Major component symbol description] 5 0: Semiconductor wafer 1 00: Edge region 102: Wafer edge _————LM丄益圆—________________________—__________________________ ______________________________________ — 1 0 6 : Wafer gap 1 0 8 : Resistor (Layer) 1 1 〇: Wafer area (with resist removed) 1 1 2 : Resistor center 1 1 4 : Resistor edge 1 16 : Distance 118: (There should be a resist but it has been removed Wafer area 1 20 : (should have been removed but there is a resist present) Wafer area 130: exposed top area -28 - 200820364 134 : 136 : 138 : 140 : 150 : 152 : 154 :
158 ： 160 ： 162 ： 164 ： 166 ： 168 ：158 : 160 : 162 : 164 : 166 : 168 :
174 ： 176 ： 178 ： 180 ： 182 ： 184 ： 186 ： 188 : 晶圓底部區域 頂部斜面 晶圓邊緣標準 底部斜面 邊緣檢查系統 頂部邊緣感應器 底部邊緣感應器 標準邊緣感應器 控制器 底座 工作台組合體 相機 相機 相機 馬—^_一 —______ 編碼器 支撐板 通信鏈 通信鏈 通信鏈 通信鏈 (頂部）檢查區域 (標準）檢查區域 (底部）檢查區域 -29 200820364 190 :像素陣列 192 :已壓縮影像 200 :邊緣小珠移除量測方法 204 :步驟 2 0 6 :步驟 2 0 8 :步驟 300 :晶圓 3 0 1 :晶圓邊緣 3 04 :晶圓缺口 3 0 6 :阻劑層 3 07 :阻劑層 3 0 8 :晶圓區域 3 0 9 :阻劑邊緣 3 1 1 :阻劑邊緣 2——邊嚴—小—嚴嚴除________________ 3 1 3 :邊緣小珠移除距離 400 :晶圓 402 :晶圓邊緣 404 :被擷取影像 406 :非壓縮影像 408 :線 4 1 0 :線段 4 1 2 :已壓縮影像 4 1 4 •晶圓軸線 -30 200820364 4 1 5 :影像 4 1 6 :阻劑軸線 4 1 8 :邊緣小珠移除線 420 :影像 422 :(已呈現的）邊緣小珠移除線 423 :邊緣小珠移除線 4 2 4 :內公差線 425 :邊緣小珠移除線 4 2 6 :外公差線 428 :(在規格外側的）部分 430 :(在規格以內的）部分 43 2 :滑動放大桿 434 :刻度尺 4 3 6 :視窗 8_ ·—邊—緣 „靜_ —面—寬------------------------------------------------------ 43 8 :點 440 :游離者 4 5 0 :影像 451 :圖案 4 5 2 :第一邊緣小珠移除線 454 :第二邊緣小珠移除線 4 5 6 :晶圓斜面 45 8 :開放空間 4 6 0 :影像 -31 - 200820364 462 :影像 464 :圖案 470 :非壓縮影像（實際影像） 471 ·已隱藏的圖案 472 :已壓縮影像 474 :點 475 :邊緣小珠移除線 A-F :線段 R :旋轉方向 X :第一次元 Y :第二次元 -32-174 : 176 : 178 : 180 : 182 : 184 : 186 : 188 : Wafer bottom area top bevel wafer edge standard bottom bevel edge inspection system top edge sensor bottom edge sensor standard edge sensor controller base table assembly Camera Camera Camera Horse_^_一—______ Encoder Support Board Communication Chain Communication Chain Communication Chain Communication Chain (Top) Inspection Area (Standard) Inspection Area (Bottom) Inspection Area-29 200820364 190: Pixel Array 192: Compressed Image 200 : Edge Bead Removal Measurement Method 204: Step 2 0 6 : Step 2 0 8 : Step 300: Wafer 3 0 1 : Wafer Edge 3 04 : Wafer Gap 3 0 6 : Resistor Layer 3 07 : Resistance Agent layer 3 0 8 : Wafer area 3 0 9 : Resistor edge 3 1 1 : Resistor edge 2 - edge strict - small - severely removed ________________ 3 1 3: edge bead removal distance 400: wafer 402: Wafer edge 404: Captured image 406: Uncompressed image 408: Line 4 1 0: Line segment 4 1 2 : Compressed image 4 1 4 • Wafer axis -30 200820364 4 1 5 : Image 4 1 6 : Resistor axis 4 1 8 : edge bead removal line 420: image 422: (presented) edge bead removal line 423: edge bead removal line 4 2 4 : inner tolerance line 425: edge bead removal line 4 2 6 : outer tolerance line 428 : (outside the specification Part 430: (within specification) part 43 2 : sliding magnification rod 434: scale 4 3 6 : window 8_ · - edge - edge „ static _ — surface — width —---------- ------------------------------------------- 43 8 : Point 440: Free 4 5 0 : Image 451 : Pattern 4 5 2 : First edge bead removal line 454 : Second edge bead removal line 4 5 6 : Wafer bevel 45 8 : Open space 4 6 0 : Image-31 - 200820364 462 : Image 464 : Pattern 470 : Uncompressed image (actual image) 471 · Hidden pattern 472 : Compressed image 474 : Point 475 : Edge bead removal line AF : Line segment R : Direction of rotation X : First Dimension Y: second dimension -32-