200813751 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電路分解架構，尤其是一種低功率 有限狀態機電路之分解架構。 【先前技術】 將一個有限狀態機(finite state machine ; FSM)電路切割成 若干個次狀態機(sub-machine)電路，已被證明可以有效地大幅 降低整體有限狀態機電路之平均功率(average p〇wer)。其原理 疋§此有限狀恶機運作時，只驅動其中之一之次狀態機電路， 並停止其它不需使用之次狀態機電路之運作，藉此，降低整體 有限狀態機電路中之切換動作(switching activities)，進而達到 降低平均功率之目地。 以往之文獻大多只討論如何降低有限狀態機電路之平均 功率’本發明挺出一種新的改良架構，不僅可以降低整體有限 狀態機電路之平均功率，並且亦可降低整體有限狀態機電路之 峰值功率(peak power)。 隨著積體電路之複雜度增加與工作頻率提高，功率消耗 之問題變得愈來愈嚴重，也愈來愈重要。動態功率消耗以電路 中之信號切換動作為主，其原理係當電路中之邏輯閘之輸入值 5 200813751 有變動時，寄生電容會有一電流經由vDD或vss進行充放電。 因此，動態功率消耗與電路中之信號切換動作係具有一成正比 之關係存在。 一個有限狀態機可被定義成6組集合{I，S，δ，〇, λ，sj， 其中Ϊ係輸入(input)之集合，S係狀態(state)之集合，δ係IxS->2s 是狀態轉移之函數，〇係輸出(0utpUt)之集合，χ係〗xS—2〇是 輸出之函數’最後S〇^S是初始狀態之集合。一個有限狀態機 亦可以用狀態轉換圖(state transition graph ; STG)來加以描述， 有限狀態機Μ之STG可記成GM(VM，EM)，其中Vm係節點 (node)之集合，代表 Μ 之狀態(state)集合;Em = {<u, v>，u，γ Vm} 係邊(edge)之集合，每一邊代表在Μ之中由一狀態u跳至另一 狀態v ’所有之邊都被標上一組輸入及輸出，其在圖中係 代表輸入觸發狀態之變動以及產生相對之輸出。 對有限狀態機電路而言，一種有效降低信號切換動作之 方式係關掉整體有限狀態機電路中暫時沒有使用之部份，亦即 將一有限狀態機電路切割成若干個次狀態機電路，並且只驅動 其中之一以及停止其它不需使用之次狀態機電路。然而，值得 注意的是，一個分割出來之次狀態機電路與原來傳統未作分割 之有限狀態機電路係有所不同，亦即每一個次狀態機電路係會 存在一些從另一個次狀態機電路出發或到達另一個次狀態機 電路之狀態，而這將會使得電路在分割及設計上更趨複雜。 6 200813751 -種有限狀誠電路之蝴方輕稱為“循序邏輯分解 (sequential logic decomposition; SLD)’’之切割架構(如第 一 A 圖 所示）。以將一有限狀態機電路切割成兩個次有限狀態機M1、 M2為例，其利用鎖住次有限狀態機Ml、M2之時脈，把其中 不需使用之次有限狀態機Ml或M2之暫存器停止，藉此使得 被停止時脈之次有限狀態機Ml或M2之處理下一狀雜之组合 電路之輸入不會改變，進而降低次有限狀態機Ml、M2整體 電路之輸入信號改變。更詳細資料可以參閱j.c.M〇nteri〇and A· L· Oliveria，“Finite State Machine Decomposition for Low Power”，Proc· Design Automaton Conference，1998, pp· 758_763 與 L· Benini and G· De Micheli，“State Assignment for Low200813751 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates to a circuit decomposition architecture, and more particularly to a decomposition architecture of a low power finite state machine circuit. [Prior Art] Cutting a finite state machine (FSM) circuit into several sub-machine circuits has been proven to effectively reduce the average power of the overall finite state machine circuit (average p 〇wer). The principle 疋§ When the finite-shaped machine is in operation, only one of the state machine circuits is driven, and the operation of the other state machine circuits that do not need to be used is stopped, thereby reducing the switching action in the overall finite state machine circuit. (switching activities), thereby achieving the goal of reducing the average power. Most of the previous literatures only discuss how to reduce the average power of finite state machine circuits. The present invention provides a new and improved architecture that not only reduces the average power of the overall finite state machine circuit, but also reduces the peak power of the overall finite state machine circuit. (peak power). As the complexity of integrated circuits increases and the operating frequency increases, the problem of power consumption becomes more and more serious and more and more important. The dynamic power consumption is mainly based on the signal switching action in the circuit. The principle is that when the input value of the logic gate in the circuit 5 200813751 changes, the parasitic capacitance will be charged and discharged via vDD or vss. Therefore, the dynamic power consumption has a proportional relationship with the signal switching action in the circuit. A finite state machine can be defined as a set of six sets {I, S, δ, 〇, λ, sj, where the set of input systems, the set of S systems, and the δ system IxS-> 2s Is a function of state transition, the set of 〇 system output (0utpUt), χxS-2 〇 is the function of output 'last S 〇 ^ S is the set of initial state. A finite state machine can also be described by a state transition graph (STG). The finite state machine STG can be recorded as GM (VM, EM), where the Vm system node (node) represents the Μ State set; Em = {<u, v>, u, γ Vm} A set of edges, each side representing a state u jumping from one state to another v 'all sides Both are labeled with a set of inputs and outputs, which in the figure represent changes in the input trigger state and produce a relative output. For the finite state machine circuit, a way to effectively reduce the signal switching action is to turn off the part of the overall finite state machine circuit that is not used temporarily, and also to cut a finite state machine circuit into a number of secondary state machine circuits, and only Drive one of them and stop other secondary state machine circuits that are not needed. However, it is worth noting that a segmented secondary state machine circuit is different from the traditional finite state machine circuit that is not split, that is, each secondary state machine circuit system has some slave state machine circuits. The state of starting or arriving at another secondary state machine circuit, which will make the circuit more complicated in segmentation and design. 6 200813751 - The finite-form circuit of the circuit is called the "sequential logic decomposition (SLD)" cutting structure (as shown in Figure A). The finite state machine circuit is cut into two. Taking the finite state machines M1 and M2 as examples, the clocks of the secondary finite state machines M1 and M2 are locked, and the registers of the secondary finite state machine M1 or M2, which are not needed to be used, are stopped, thereby being stopped. The input of the combined circuit of the next finite state machine Ml or M2 of the clock will not change, thereby reducing the input signal change of the overall circuit of the sub-finite state machine M1, M2. For more details, please refer to jcM〇nteri〇 And A·L· Oliveria, “Finite State Machine Decomposition for Low Power”, Proc· Design Automaton Conference, 1998, pp· 758_763 and L· Benini and G· De Micheli, “State Assignment for Low
Power Dissipation55, in the Solid-State Circuits, IEEE Journal of Volume 30, Issue 3, 1995, pp· 258-268 〇 而另一種有限狀態機電路之切割方式係稱為“組合邏輯 分解(combinational logic decomposition ; CLD)”之切割架構(如 第一 B圖所示）。以切割成兩個次有限狀態機Ml、M2為例， 其利用數個及閘(AND gate)對不須使用之次有限狀態機Ml或 M2之輸入進行阻擋。例如··當次有限狀態機Ml電路在關閉 之狀態時，係由解碼器送出一邏輯0之信號給次有限狀態機 Ml電路前之三個及閘，藉此將次有限狀態機Ml電路之輸入 變為邏輯〇。如果次有限狀態機Ml電路之後還是一直為關閉 7 200813751 狀態時，送入次有限狀態機Ml電路之輸入亦將恆為邏輯〇。 藉此，此分解架構亦可以降低輸入次有限狀態機ΜΙ、M2之 輸入轉換頻率以減少電路中之信號切換動作。更詳細資料可以 參閱 S· H· Chow，Y· C· Ho, T· Hwang and C. L. Liu，“Low Power Realization of Finite State Machine—A Decomposition Approach，，， ACM TODAES，vol· 1，1996, pp· 315-340。 然而，根據上述之組合邏輯分解之切割架構，如果利用 及閘來控制次有限狀態機Ml、M2之動作與否時，當要關掉 其中一個次有限狀態機Ml或M2時，及閘會強迫被關掉之次 有限狀態機Ml或M2之輸入全部為邏輯〇。因此，在次有限 狀態機m、M2轉移之瞬間，會造成兩個次有限狀態機M1 與M2都會有輸入信號之切換動作，其效果係等同兩個次有限 狀悲機Ml、M2同時運作。舉例來說，從次有限狀態機mi 跳至次有限狀態機M2時，次有限狀態機mi前之及閘會強迫 次有限狀態機Ml之所有輸入全部為邏輯〇，而此同時，儲存 狀態之暫存器FF〇、FFi、FF2會把内容值灌進次有限狀態機 M2。所以在次有限狀態機Ml轉移至M2這一瞬間，次有限 狀悲機Ml、M2都會有輸入信號之切換動作，此一現象將會 造成很大之峰值功率(因為次有限狀態機Mi、m2 —起變動）。 鑒於以上所述之有限狀態機電路分解架構之缺點，實有 需要持續發展新的改良電路分解架構以克服先前技藝之各項 8 200813751 缺失。所以，如何避免有限狀態機電路同時進行狀態切換以及 如何降低有限狀態機電路之峰值功率與平均功率等，是此技術 領域必然會遭遇之問題，亦是本發明所要解決之問題。 【發明内容】 鑒於上述之發明背景，為符合產業上某些利益之需求， 本發明提供一種有限狀態機電路之分解架構，以解決上述傳統 有限狀態機電路分解架構未能達成之標的。 本發明揭露一種有限狀態機電路之分解架構，其藉由一 儲存模組依一選擇信號選取輸出一狀態信號，並問鎖其他未被 選取之狀態信號，藉此，僅改變一有限狀態機次電路之輸入以 降低有限狀癌、機整體電路之峰值功率(peak p0wer)與平均功率 (average power);並藉由一緩衝模組調整信號傳遞時間，使得 此狀悲#5虎與此選擇信號可以同時被此儲存模組接收，藉此， 避免因信號處理之級數差異而產生延遲錯誤。 本發明提供一種有限狀態機電路之分解架構，其包含： 複數個有限狀態機次模組，係對應接收複數個第一狀態信號與 一第一輸入信號，並對應輸出複數個第二狀態信號、複數個輸 出信號與複數個第一選擇信號；一選擇模組，係接收此些第二 狀態信號、此些輸出信號、此些第一選擇信號與一第二選擇信 9 200813751 號，並依此第二選擇信號選取此些第二狀態信號其中之一、此 些輸出信號其中之一與此些第一選擇信號其中之一輸出；一暫 存模組，係接收此選擇模組輸出之第二狀態信號與第一選擇信 號，並暫存後輸出此第二狀態信號與此第二選擇信號；一解碼 模組，係接收此第二選擇信號，並解碼後輸出一第三選擇信 號；以及一儲存模組，係接收一第二輸入信號、此第二狀態信 號與此第三選擇信號，並輸出此些第一狀態信號與此第一輸入 信號，其中此儲存模組係以此第二輸入信號取代此第一輸入信 號，並以此第二狀態信號取代此第三選擇信號所選之第一狀態 信號。 本發明更提供一種有限狀態機電路之分解架構，其包 含：兩有限狀態機次模組，係對應接收兩第一狀態信號與一第 一輸入信號，並對應輸出兩第二狀態信號、兩輸出信號與雨第 一選擇信號；複數個多工器，係對應接收此兩第二狀態信號、 此兩輸出信號、此兩第一選擇信號與一第二選擇信號，並依此 第二選擇信號選取此兩第二狀態信號其中之一、此兩輸出信號 其中之一與此兩第一選擇信號其中之一輸出；複數個正反器， 係對應接收此些多工器輸出之第二狀態信號與第一選擇信 號’並暫存後輸出此第二狀態信號與此第二選擇信號；一解瑪 器，係接收此第二選擇信號，並解碼輸出一第三選擇信號；複 數個儲存裝置’係對應接收一第二輸入信號、此第二狀態信號 200813751 與此第三選擇信號，並且輸出此兩第一狀態信號與此第一輸入 信號，其中此些儲存裝置係以此第二輸入信號取代此第一輸入 信號，並以此第二狀態信號取代此第三選擇信號所選取之第一 狀態信號；以及一緩衝模組，係用以使此第二狀態信號與此第 三選擇信號可同時輸出至此些儲存裝置。 【實施方式】 本發明在此所探討的方向為一種有限狀態機電路之分解 架構。為了能夠徹底地瞭解本發明，將在下列描述中提出詳盡 之步驟及喊。賴地，本發明域行並絲錄此項領域之 技藝者所熟習之特殊細節。另—方面，眾所周知之組成或步驟 亦並未描述於細節中，避免造成本發明不必要之限制。本發明 之較佳實施例會詳細描述如下，然而除了這些詳細描述之外， 本《X明還可以廣泛地施行在其他之實施例巾，且本發明之範圍 亦不受限定，其以之後之專利範圍為準。 清參照第二圖，其為本發明之一較佳實施例之概略系統 方塊圖。複數個有限狀態機次模組M1、M2、…、Mn，係對應 接收複數個第-狀態信號與—第—輸人信號(其中此第一輸入 U虎搭配此複數個第一狀態信號形成複數個信號川4)，並對應 輸出複數個第二狀態錄112、複數個触雜ιΐ6與複數個 第選擇域114。在本實施例中，冑限狀態機次模組μ〗、 11 200813751 Μ2、…、Mn係由切割一有限狀態機電路11〇所形成，且其等 之架構係可依實際需求切割而成，並不受限等分切割之架構， 其中，n22且η為自然數。在本實施例中，第一輪入信號係 包含一 i位元資料(i > 〇且i為自然數）；每一第一狀態信號係 包含一 j位元資料(j > 〇且j為自然數)；每一第二狀態信號 係包含一 j位元資料；每一輸出信號116係包含一 q位元資料 (q > 0且q為自然數）；以及每一第一選擇信號1M係包含一 k 位元資料(k > 0且k為自然數），其中，每一 m位元信號1〇4 係由一 i位元第一輸入信號與一 j位元第一狀態信號所組成， 亦即m = i+j，而第一選擇信號114之位元數]^與有限狀態機 次模組Μ!、M2、…、Mn之個數η的關係為n£2k。 一選擇模組120，係接收上述之第二狀態信號112、輸出 信號116、第一選擇信號114與一第二選擇信號134，並依據 第二選擇信號134選取此些第二狀態信號112其中之一、輸出 信號116其中之一與第一選擇信號114其中之一輸出，其中， 選擇模組120輸出之信號124 (包含第二狀態信號與第一選擇 信號)與輸出信號122係由有限狀態機次模組Mi、M2、…、 Mn其中之一所產生。在本實施例中，第二選擇信號134係— 相對第一選擇信號114之k位元資料，p位元信號124係由一 j位元第二狀態信號與一 k位元第一選擇信號114所組成，即 p=j+ko 12 200813751 一暫存模組130，係接收選擇模組120所輸出之信號i24 (包含第二狀態信號與第一選擇信號），並且暫存後輸出此第二 狀態信號132與上述之第二選擇信號134。 一解碼模組140,係接收暫存模組130所輸出之第二選擇 信號134，並且解碼後輸出一第三選擇信號142，其中，第二 選擇信號142係包含一 r位元資料(r == 2k)。 一儲存模組150，係接收一第二輸入信號1〇2、暫存模組 UO所輸出之第二狀態信號132與解碼模組14〇所輸出之第三 選擇信號142，並輸出有限狀態機次模組Μα、M2、···、Mnm 對應接收之複數個信號1〇4(第一狀態信號與第一輸入信號）。 在本實％例中’儲存模組150係以第二輸入信號1〇2取代第一 輸入信號，並以第二狀態信號132取代第三選擇信號142所選 之第一狀態信號，亦即，儲存模組15〇係依據第三選擇信號 142選取一第一狀態信號，並以第二狀態信號132取代此第一 狀態信號，而其他未被選取之第一狀態信號則維持不變，藉此 僅改變一有限狀態機次模組之輸入以避免有限狀態機電路110 之所有輸入狀態同時改變，以降低有限狀態機電路11()之峰值 功率(peak power)與平均功率(average power)。 一緩衝模組160，係用以使得暫存模組130所輸出之第二 狀態信號132與解碼模組140所輸出之第三選擇信號142可以 同時抵達儲存模組150，藉此，避免因信號處理之級數不同而 13 200813751 產生延遲錯誤。在本實施例中，緩衝模組160係延遲暫存模組 130處理第二狀態信號132電路之時脈162，而所延遲之時脈 162之時間係相等於解碼模組140將第二選擇信號134解碼成 第二選擇信號142所需之時間，藉此，暫存模組丨3〇所輸出之 第二狀態信號132與解碼模組140所輸出之第三選擇信號142 即可同時輸出至儲存模組150以避免因信號處理之級數不同 而產生延遲錯誤。在另一實施例中，亦可將緩衝模組16〇加在 暫存模組130與儲存模組150之間以作為第二狀態信號132之 資料緩衝，藉此，使得信號處理之級數相同以避免上述之延遲 錯誤。 請參照第三圖，其為一有限狀態機之狀態轉換圖(state tmnsition graph ; STG)。在本實施例中，此有限狀態機係僅用 以說明本發明之範例，其並非用以限定本發明之實施。此有限 狀fe機係包含7個狀態，其等分別為si(狀態為〇〇〇)、S2(狀態 為001)、S3(狀態為111)、S4(狀態為010)、S5(狀態為100)、 S6(狀態為011)以及S7(狀態為1〇1)，其中此7個狀態被分割 成為兩個狀態之子集合S’ = {Sl，S4，S6}與S，，= {S2，S3, S5, S7} ’然後分別利用S’與S”構成稍後說明之有限狀態機次模組 Μι、M2之分解架構。 當Sl(狀態為000)輸入為〇時，狀態變成S6(狀態為〇11) 且輸出為00 ;當S1輸入為1時，狀態變成S4(狀態為010)且 200813751 輸出為00。當S4(狀態為oio)輸入為〇時，狀態變成％(狀態 為011)且輸出為〇〇 ;當S4輸入為1時，狀態變成S6且輸出 為10。當S6(狀態為〇11)輸入為〇時，狀態變成S1(狀態為〇〇〇) 且輸出為01 ;而當S6輸入為1時，狀態變成不同子集合之 S2(狀態為001)且輸出為01。當S2(狀態為〇〇1)輸入為〇時， 狀悲變成S5(狀態為1〇〇)且輸出為〇〇 ;當§2輸入為1，狀態 變成S3(狀態為in)且輸出為00。當S3(狀態為⑴)輸入為〇 時，狀態變成S5(狀態為1〇〇)且輸出為00;當S3輸入為1時， 狀態變成S7(狀態為ιοί)且輸出為〇〇。當S5(狀態為1〇〇)輸入 為〇時，狀態變成不同子集合之Sl(狀態為000)且輸出為1〇 ; § S5輸入為1時，狀態變成S2(狀態為〇〇1)且輸出為1〇。當 S7(狀態為1〇1)輸入為〇時，狀態變成S5(狀態為1〇〇)且輸出 為〇〇 ’·而當S7輸入為1時，狀態變成不同子集合之％(狀態 為011)且輸出為1〇。下列表一係上述之有限狀態機之真值表， 其中FF0攔位係控制有限狀態機次模組％、m2開關之暫存器 FF0之内容值(稍後說明）。 目前狀態 輸入 下一狀態輪出Power Dissipation 55, in the Solid-State Circuits, IEEE Journal of Volume 30, Issue 3, 1995, pp. 258-268. Another way to cut a finite state machine circuit is called "combinational logic decomposition (CLD). )" cutting structure (as shown in Figure B). Taking the two finite state machines M1, M2 cut into an example, it uses several AND gates to block the input of the secondary finite state machine M1 or M2 that is not needed. For example, when the finite state machine M1 circuit is in the off state, the decoder sends a logic 0 signal to the third gate of the sub-finite state machine M1 circuit, thereby using the sub-finite state machine M1 circuit. The input becomes logical 〇. If the secondary finite state machine M1 circuit is still turned off after the 7 200813751 state, the input to the secondary finite state machine M1 circuit will also be a logical 〇. Thereby, the decomposition architecture can also reduce the input switching frequency of the input sub-finite state machine ΜΙ, M2 to reduce the signal switching action in the circuit. For more details, please refer to S·H·Chow, Y·C· Ho, T·Hwang and CL Liu, “Low Power Realization of Finite State Machine—A Decomposition Approach,, ACM TODAES, vol· 1,1996, pp· 315-340. However, according to the above-described combination logic decomposition cutting architecture, if the gate and the gate are used to control the action of the secondary finite state machine M1, M2, when one of the secondary finite state machines M1 or M2 is to be turned off, The input of the finite state machine Ml or M2 that is forced to be turned off by the gate is all logical 〇. Therefore, at the moment when the sub-finite state machine m and M2 are transferred, the two finite state machines M1 and M2 will have input. The switching action of the signal is equivalent to the operation of two sub-finite sorcerers Ml, M2. For example, when jumping from the sub-finite state machine mi to the sub-finite state machine M2, the singular state machine mi All the inputs of the secondary finite state machine M1 will be forced to be logical 〇, and at the same time, the storage state registers FF〇, FFi, FF2 will fill the content value into the secondary finite state machine M2. Therefore, the secondary finite state machine M1 Transfer to M2 In an instant, the sub-finite straits Ml, M2 will have the switching action of the input signal, this phenomenon will cause a large peak power (because the secondary finite state machine Mi, m2 changes). In view of the above limited state The shortcomings of the circuit decomposition architecture, there is a need to continue to develop new improved circuit decomposition architectures to overcome the lack of prior art 8 200813751. So, how to avoid the state switching of finite state machine circuits and how to reduce the peak value of finite state machine circuits Power and average power, etc., are inevitable problems in the technical field, and are also problems to be solved by the present invention. [Invention] In view of the above-mentioned background of the invention, the present invention provides a limited amount in order to meet the needs of certain interests in the industry. The decomposition architecture of the state machine circuit solves the problem that the conventional finite state machine circuit decomposition architecture fails to achieve. The present invention discloses a decomposition architecture of a finite state machine circuit, which selects an output state according to a selection signal by a storage module. Signal and ask to lock other unselected status signals, thereby Change the input of a finite state machine circuit to reduce the peak power (peak p0wer) and average power of the finite cancer, the overall circuit of the machine; and adjust the signal transmission time by a buffer module to make this shape The tiger and the selection signal can be simultaneously received by the storage module, thereby avoiding delay errors due to the difference in the level of signal processing. The present invention provides a decomposition architecture of a finite state machine circuit, which includes: a plurality of finite states The machine module is configured to receive a plurality of first state signals and a first input signal, and correspondingly output a plurality of second state signals, a plurality of output signals and a plurality of first selection signals; a selection module receives The second state signal, the output signals, the first selection signals and a second selection signal 9 200813751, and selecting one of the second state signals, the output signals according to the second selection signal One of the first selection signals is outputted by one of the first selection signals; a temporary storage module receives the second status signal and the first selection signal output by the selection module And temporarily storing the second status signal and the second selection signal; a decoding module receives the second selection signal and outputs a third selection signal after decoding; and a storage module receives the first a second input signal, the second state signal, and the third selection signal, and outputting the first state signal and the first input signal, wherein the storage module replaces the first input signal with the second input signal And replacing the first state signal selected by the third selection signal with the second state signal. The invention further provides a decomposition architecture of a finite state machine circuit, comprising: two finite state machine modules, corresponding to receiving two first state signals and a first input signal, and correspondingly outputting two second state signals, two outputs Signal and rain first selection signal; a plurality of multiplexers corresponding to receiving the two second state signals, the two output signals, the two first selection signals and a second selection signal, and selecting according to the second selection signal One of the two second state signals, one of the two output signals and one of the two first selection signals are output; the plurality of flip-flops are corresponding to the second state signal receiving the output of the multiplexers The first selection signal 'and temporarily stores the second state signal and the second selection signal; a damper receives the second selection signal and decodes and outputs a third selection signal; the plurality of storage devices are Correspondingly receiving a second input signal, the second state signal 200813751 and the third selection signal, and outputting the two first state signals and the first input signal, wherein the The storage device replaces the first input signal with the second input signal, and replaces the first state signal selected by the third selection signal with the second state signal; and a buffer module is used to make the second The status signal and the third selection signal can be simultaneously output to the storage devices. [Embodiment] The direction of the invention discussed herein is a decomposition architecture of a finite state machine circuit. In order to fully understand the present invention, detailed steps and shouts will be set forth in the following description. Lai Di, the domain of the present invention and the specific details familiar to those skilled in the art. In other instances, well-known components or steps are not described in detail, and are not intended to limit the invention. The preferred embodiments of the present invention will be described in detail below, but in addition to these detailed descriptions, the present invention can be widely applied to other embodiments, and the scope of the present invention is not limited, and the subsequent patents The scope shall prevail. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a block diagram showing a schematic system of a preferred embodiment of the present invention. a plurality of finite state machine modules M1, M2, ..., Mn, corresponding to receiving a plurality of first-state signals and a -first-input signal (where the first input U-hu is matched with the plurality of first state signals to form a complex number The signal is 4), and correspondingly outputs a plurality of second status records 112, a plurality of touches ιΐ6 and a plurality of selection fields 114. In this embodiment, the limit state machine module μ, 11 200813751 Μ 2, ..., Mn are formed by cutting a finite state machine circuit 11 , and the structure of the system can be cut according to actual needs. There is no limited unequal cut architecture, where n22 and η are natural numbers. In this embodiment, the first round-in signal includes an i-bit data (i > i and i is a natural number); each first state signal includes a j-bit data (j > 〇 and j a natural number); each second state signal includes a j-bit data; each output signal 116 includes a q-bit data (q > 0 and q is a natural number); and each first selection signal The 1M system includes a k-bit data (k > 0 and k is a natural number), wherein each m-bit signal 1〇4 is composed of an i-bit first input signal and a j-bit first state signal. The composition, that is, m = i + j, and the number of bits of the first selection signal 114 is related to the number η of finite state machine modules Μ!, M2, ..., Mn is n £ 2k. The selection module 120 receives the second state signal 112, the output signal 116, the first selection signal 114 and a second selection signal 134, and selects the second state signals 112 according to the second selection signal 134. 1. Outputting one of the output signals 116 and one of the first selection signals 114, wherein the signals 124 (including the second state signal and the first selection signal) and the output signal 122 output by the selection module 120 are finite state machines One of the secondary modules Mi, M2, ..., Mn is generated. In the present embodiment, the second selection signal 134 is - relative to the k-bit data of the first selection signal 114, and the p-bit signal 124 is comprised of a j-bit second state signal and a k-bit first selection signal 114. The composition, that is, p=j+ko 12 200813751, a temporary storage module 130 receives the signal i24 (including the second state signal and the first selection signal) output by the selection module 120, and outputs the second after the temporary storage. The status signal 132 is coupled to the second selection signal 134 described above. A decoding module 140 receives the second selection signal 134 output by the temporary storage module 130, and outputs a third selection signal 142 after decoding, wherein the second selection signal 142 includes an r bit data (r = = 2k). A storage module 150 receives a second input signal 1〇2, a second status signal 132 output by the temporary storage module UO, and a third selection signal 142 output by the decoding module 14〇, and outputs a finite state machine. The secondary modules Μα, M2, . . . , Mnm correspond to the received plurality of signals 1〇4 (the first state signal and the first input signal). In the present example, the storage module 150 replaces the first input signal with the second input signal 1〇2, and replaces the first status signal selected by the third selection signal 142 with the second status signal 132, that is, The storage module 15 selects a first status signal according to the third selection signal 142, and replaces the first status signal with the second status signal 132, and the other unselected first status signals remain unchanged. Only the input of a finite state machine module is changed to avoid simultaneous changes in all input states of the finite state machine circuit 110 to reduce the peak power and average power of the finite state machine circuit 11(). A buffer module 160 is configured to enable the second status signal 132 output by the temporary storage module 130 and the third selection signal 142 output by the decoding module 140 to arrive at the storage module 150 at the same time, thereby avoiding the signal The number of levels processed is different and 13 200813751 produces a delay error. In this embodiment, the buffer module 160 delays the clock 162 of the second state signal 132 circuit by the temporary storage module 130, and the delayed clock 162 is equal to the decoding module 140 to select the second selection signal. The time required for decoding 134 into the second selection signal 142, whereby the second state signal 132 output by the temporary storage module 丨3〇 and the third selection signal 142 output by the decoding module 140 can be simultaneously output to the storage. Module 150 avoids delay errors due to different levels of signal processing. In another embodiment, the buffer module 16 can be added between the temporary storage module 130 and the storage module 150 as a data buffer of the second status signal 132, thereby making the signal processing level the same. To avoid the above delay errors. Please refer to the third figure, which is a state transition diagram (STG) of a finite state machine. In the present embodiment, the finite state machine is only used to illustrate the examples of the present invention, and is not intended to limit the implementation of the present invention. This finite-feature machine consists of seven states, which are si (state 〇〇〇), S2 (state 001), S3 (state 111), S4 (state 010), and S5 (state 100). ), S6 (state 011) and S7 (state 1〇1), wherein the 7 states are divided into sub-sets of two states S' = {Sl, S4, S6} and S,, = {S2, S3 , S5, S7} 'and then use S' and S respectively to form the decomposition structure of the finite state machine module Μι, M2 described later. When the input of Sl (state 000) is 〇, the state becomes S6 (the status is 〇11) and the output is 00; when the S1 input is 1, the state changes to S4 (state 010) and the 200813751 output is 00. When the S4 (state oio) input is 〇, the state becomes % (state 011) and The output is 〇〇; when the S4 input is 1, the state changes to S6 and the output is 10. When S6 (state 〇11) input is 〇, the state changes to S1 (state 〇〇〇) and the output is 01; When the S6 input is 1, the state becomes S2 of the different subset (state is 001) and the output is 01. When the input of S2 (state 〇〇1) is 〇, the sorrow becomes S5 (state is 1〇〇) and the output For 〇〇; when § 2 loses When 1, the status changes to S3 (the status is in) and the output is 00. When the input of S3 (state (1)) is 〇, the status changes to S5 (state is 1〇〇) and the output is 00; when the S3 input is 1, The state changes to S7 (state ιοί) and the output is 〇〇. When S5 (state 1 〇〇) input is 〇, the state becomes Sl of different subsets (state is 000) and the output is 1〇; § S5 input is At 1 o'clock, the state changes to S2 (state is 〇〇1) and the output is 1〇. When S7 (state 1〇1) input is 〇, the state changes to S5 (state is 1〇〇) and the output is 〇〇'· When the S7 input is 1, the state becomes % of the different subsets (state 011) and the output is 1 〇. The following list is the truth table of the above finite state machine, wherein the FF0 interceptor controls the finite state machine The content value of the register FF0 of the module % and m2 switches (described later). The current state inputs the next state round.
15 200813751 S4 010 0 S6 011 00 0 1 S6 011 10 0 S6 011 0 S1 000 01 0 1 S2 001 01 1 M2 S2 001 0 S5 100 00 1 1 S3 111 00 1 S3 111 0 S5 100 00 1 1 S7 101 00 1 S5 100 0 S1 000 10 0 1 S2 001 10 1 S7 101 0 S5 100 00 1 1 S6 011 10 0 表一上述之有限狀態機之真值表 請參照第四圖，其為本發明依第三圖之實施例所實施之 一較佳有限狀態機電路之分解架構圖。兩有限狀態機次模組 Ml、M2，係對應接收兩第一狀態信號與一第一輸入信號(其中 此第一輸入信號係分別搭配此兩第一狀態信號），並對應輸出 兩第二狀態信號、兩輸出信號與兩第一選擇信號。其中，有限 狀態機次模組Μ!、MZ係切割一有限狀態機電路11〇所形成， 且其等之架構係可依實際需求切割而成，並不受限等分切割之 200813751 架構，例如：Ml具有上述S’ = {Sl，S4, S6}之狀態子集合；而 M2具有上述S” = { % S3, S5, S7}之狀態子集合。在本實施例 中，第-輸入信號係包含-i位元資料(i > 0且i為自然數）； 母一第一狀態信號係包含一 j位元資料(j > 〇且j為自然數）； 每-第二狀態信號係包含- j位元資料；每一輪出信號係包含 一 q位元資料(q > 0且q為自然數)；以及每一第一選擇信號係 包含一 k位元資料(k>0且k為自然數），其中，i==1、j = 3、 卜q = 2，然不限於此，其等可依實際需求而加以調整，而 第一選擇信號之位元數k與有限狀態機次模組之個數n的關係 為 η $ 2k。 複數個多工器MUX (係對照第二圖之選擇模組12〇)，係 對應接收上述之弟一狀恶信號、輸出信號、第一選擇信號與一 第二選擇信號，並依第二選擇信號選取此兩第二狀態信號其中 之一、輸出信號其中之一與第一選擇信號其中之一輸出，並且 在本實施例中，此些多工器MUX輸出之第二狀態信號、第一 選擇信號與輸出信號係由有限狀態機次模組Μι、m2其中之一 所產生。此外，第二選擇信號係一相對第一選擇信號之k位元 資料，然不限於此。 複數個正反器FF3、FF2、FF1、FF0 (對照第二圖之暫存 杈組130)，係對應接收複數個多工器所輸出之第二狀態 #遽與第一選擇信號，並暫存後輸出此第二狀態信號(由FF3、 17 200813751 FF2與FF1輸出)與上述之第二選擇信號(由FF〇輪出），此第二 選擇彳§號即上述控制有限狀態機次模組、Μ:開關之暫存器 FF0之内容值。 一解碼器(係對照第二圖之解碼模組14〇)，係接收正反器 FF0所輸出之第二選擇信號，並解碼後輸出一第三選擇信號， 其中，此第三選擇信號係包含一 r位元資料(r = 2k)。因此，當 k- 1日守’2位元之第三選擇信號即可以直接控制兩有限狀態機 次模組Ml、M2開關。 複數個閂鎖器(對照第二圖之儲存模組150)，係對應接收 一第二輸入信號、正反器FF3、FF2與FF1所輸出之第二狀態 信號與解碼器所輸出之第三選擇信號，並且輸出兩有限狀態機 次模組Ml、M2所對應接收之兩第一狀態信號與一第一輸入 信號。在本實施例中，此些閂鎖器係以第二輸入信號取代第一 輸入信號，並以第二狀態信號取代第三選擇信號所選取之第一 狀態信號，亦即，此些閂鎖器係依據第三選擇信號將第二狀態 信號傳送到開啟之有限狀態機次模組Ml或M2以取代原第一 狀態信號，而其他未被選取之第一狀態信號則維持不變，藉此 僅改變一有限狀態機次模組之輸入以避免有限狀態機電路110 之所有輸入狀態同時改變，並降低有限狀態機電路110之峰值 功率與平均功率。在另一實施例中，上述之複數個閂鎖器亦可 用§己憶體等餘存裝置取代。 200813751 -緩衝器（第二圖之儲存模組16G)，係用以使得正反器15 200813751 S4 010 0 S6 011 00 0 1 S6 011 10 0 S6 011 0 S1 000 01 0 1 S2 001 01 1 M2 S2 001 0 S5 100 00 1 1 S3 111 00 1 S3 111 0 S5 100 00 1 1 S7 101 00 1 S5 100 0 S1 000 10 0 1 S2 001 10 1 S7 101 0 S5 100 00 1 1 S6 011 10 0 Table 1 The truth table of the above finite state machine, please refer to the fourth figure, which is the third figure of the present invention. An exploded architecture diagram of one of the preferred finite state machine circuits implemented in an embodiment. The two finite state machine modules M1 and M2 respectively receive two first state signals and a first input signal (where the first input signal is respectively matched with the two first state signals), and correspondingly output two second states. The signal, the two output signals and the two first selection signals. Among them, the finite state machine module Μ!, the MZ system cuts a finite state machine circuit 11〇, and its architecture can be cut according to actual needs, and is not limited to the unequal cut 200813751 architecture, for example :Ml has the state subset of S' = {Sl, S4, S6}; and M2 has the state subset of S" = {% S3, S5, S7}. In this embodiment, the first input signal system Contains -i bit data (i > 0 and i is a natural number); the mother-first state signal contains a j-bit data (j > 〇 and j is a natural number); each-second state signal system Include -j bit data; each round of signal contains a q-bit data (q > 0 and q is a natural number); and each first selection signal contains a k-bit data (k > 0 and k It is a natural number), where i==1, j=3, and q=2, but it is not limited to this, and the like can be adjusted according to actual needs, and the number of bits of the first selection signal k and the finite state machine The relationship between the number n of the secondary modules is η $ 2k. The multiple multiplexers MUX (in contrast to the selection module 12〇 of the second figure) are corresponding to the above-mentioned brothers. a signal, an output signal, a first selection signal and a second selection signal, and selecting one of the two second state signals, one of the output signals, and one of the first selection signals according to the second selection signal, and In this embodiment, the second state signal, the first selection signal, and the output signal output by the multiplexer MUX are generated by one of the finite state machine modules Μι, m2. In addition, the second selection signal is The k-bit data relative to the first selection signal is not limited thereto. The plurality of flip-flops FF3, FF2, FF1, FF0 (in contrast to the temporary storage group 130 of the second figure) are corresponding to receiving a plurality of multiplexers Outputting the second state #遽 and the first selection signal, and temporarily storing the second state signal (outputted by FF3, 17 200813751 FF2 and FF1) and the second selection signal (rounded by FF )), The second option 彳§ is the content value of the above-mentioned finite state machine module, Μ: switch register FF0. A decoder (comprising the decoding module 14 第二 of the second figure) receives the flip flop The second selection signal output by FF0, and decoded Outputting a third selection signal, wherein the third selection signal includes an r-bit data (r = 2k). Therefore, when the k- 1 day keeps the third selection signal of the '2 bits, the two limited signals can be directly controlled. The state machine module M1, M2 switch. The plurality of latches (cf. the storage module 150 of the second figure) are corresponding to receive a second input signal, the second state output by the flip-flops FF3, FF2 and FF1 The signal and the third selection signal output by the decoder, and output two first state signals and a first input signal corresponding to the two finite state machine modules M1, M2. In this embodiment, the latches replace the first input signal with the second input signal, and replace the first state signal selected by the third selection signal with the second state signal, that is, the latches The second state signal is transmitted to the open finite state machine module M1 or M2 according to the third selection signal to replace the original first state signal, and the other unselected first state signals remain unchanged, thereby Changing the input of a finite state machine module avoids simultaneous changes in all input states of the finite state machine circuit 110 and reduces the peak power and average power of the finite state machine circuit 110. In another embodiment, the plurality of latches described above may be replaced by a residual device such as a memory. 200813751 - Buffer (storage module 16G of the second figure), used to make the flip-flop
FF3 ^FF2>FF1 H〇^ J 第三選擇信號可同時抵達複數_，藉此，避免信號處理 級數不同而產生延遲錯誤。在本實施例中，緩衝$ 16〇=遲 正反器FF3〜FF1之時脈，而所延遲之時脈係相等於解碼器⑽ 將第二選擇錢解碼成第三聰錢所需之脈係，藉此正反器 FF3〜FF1所輸出之第二狀態信號與解碼_ i4〇輸出之第三選擇 信號即可_輸技複數侧鎖如避紅叙延遲錯誤。 請參照第五A圖與第五B圖，其等係分別為第三圖所示 之實施例以習知組合邏輯分解(CLD)之切割架構與以第四圖 之分解架構實施之信號波形圖。此兩波形圖係僅用以說明縱向 所示之信號彼此間的相互關係，而其橫向係代表時間軸，至於 其他未標示之單位(例如電壓單位、時間單位)在此均省略以求 圖示之簡潔。 請參照第五A圖，在τ5時間點時，狀態從有限狀態機次 模組Ml之S6跳至有限狀態機次模組M2之S2，且信號 M1—ON從1變〇 (表示關閉有限狀態機次模組mi)，信號 M2一ON從0變1 (表示開啟有限狀態機次模組M2)，因此， Ml輸入從1011變〇〇〇〇，而m2輸入從〇〇〇〇變1〇〇1。在丁9 時間點時，狀態從M2之S5跳至Ml之S1，且信號M1J3N 從0變1 (表示開啟Ml)，信號M2_ON從1變0 (表示關閉 200813751 M2) ’因此，Ml輸入從〇〇〇〇變〇〇〇〇，而M2輸入從0100變 0000。在Tu時間點時，狀態從Ml之S6跳至M2之S2，且 信號M1—ON從1變〇 (表示關閉M1)，信號M2_〇N從0變1 (表示開啟M2)，因此，Ml輸入從1011變〇〇〇〇，而M2輸入 從 0000 變 1001。 請參照第五B圖，在T5時間點時，狀態從有限狀態機次 模組Ml之S6跳至有限狀態機次模組M2之S2，且信號 Ml一ON從1變〇 (表示關閉有限狀態機次模組Ml)，信號 M2—ON從0變1 (表示開啟有限狀態機次模組M2)，因此， Ml輸入從1〇11變i〇u，而M2輸入從xxxx變1001。在T9 時間點時，狀態從M2之S5跳至Ml之S1，且信號M1J3N 從0變1 (表示開啟Ml)，信號M2_ON從1變0 (表示關閉 M2)，因此，Ml輸入從1011變0000，而M2輸入從0100變 0100。在T13時間點時，狀態從Ml之S6跳至M2之S2，且 信號M1J3N從1變0(表示關閉Ml)，信號M2_ON從0變1 (表示開啟M2)，因此，Ml輸入從1011變1011，而M2輸入 從 0100 變 1001。 狀態在Ml、M2間 互相轉移 Ml之輸入值變化 M2之輸入值變化 1011—0000 0000—1001 20 200813751 M2^M1 〇〇〇〇->〇〇〇〇 0100—0000 M“M2 1011—0000 0000-> 1001 表二A使用組合邏輯分解之切割架構，狀態在mi、m2 之間互相轉移時，輸入有限狀態機次模組撾卜河2之輸入值 變動狀況FF3 ^FF2>FF1 H〇^ J The third selection signal can reach the complex _ at the same time, thereby avoiding delay errors caused by different signal processing stages. In this embodiment, buffering the clock of $16〇=late flip-flops FF3~FF1, and the delayed clock is equal to the pulse system required by the decoder (10) to decode the second selection money into the third currency. Therefore, the second state signal outputted by the flip-flops FF3 FFFF1 and the third selection signal outputted by the decoding _i4 即可 can be used as a singularity side lock such as a delay error. Please refer to FIG. 5A and FIG. 5B, which are respectively the waveform diagram of the conventional combined logic decomposition (CLD) cutting architecture and the fourth graph decomposition architecture implemented in the embodiment shown in FIG. . The two waveform diagrams are only used to illustrate the relationship between the signals shown in the longitudinal direction, and the horizontal system represents the time axis. As for other unlabeled units (such as voltage units and time units), they are omitted here for illustration. Simple. Referring to FIG. 5A, at time τ5, the state jumps from S6 of the finite state machine module M1 to S2 of the finite state machine module M2, and the signal M1_ON changes from 1 (indicating that the finite state is turned off) The machine module mi), the signal M2_ON changes from 0 to 1 (indicating that the finite state machine module M2 is turned on), therefore, the M1 input changes from 1011, and the m2 input changes from 〇〇〇〇1〇. 〇1. At the time point of D9, the state jumps from S5 of M2 to S1 of M1, and the signal M1J3N changes from 0 to 1 (indicating that M1 is turned on), and the signal M2_ON changes from 1 to 0 (indicating that 200813751 M2 is turned off) 'So, Ml input from 〇 It changes to 〇〇〇〇, and the M2 input changes from 0100 to 0000. At the Tu time point, the state jumps from S6 of M1 to S2 of M2, and the signal M1_ON changes from 1 to 〇 (indicating that M1 is turned off), and the signal M2_〇N changes from 0 to 1 (indicating that M2 is turned on), therefore, Ml The input changes from 1011, and the M2 input changes from 0000 to 1001. Referring to FIG. 5B, at time T5, the state jumps from S6 of the finite state machine module M1 to S2 of the finite state machine module M2, and the signal M1_ON changes from 1 (indicating that the finite state is turned off) The machine module M1), the signal M2_ON changes from 0 to 1 (indicating that the finite state machine module M2 is turned on), therefore, the M1 input changes from 1〇11 to i〇u, and the M2 input changes from xxxx to 1001. At the T9 time point, the state jumps from S5 of M2 to S1 of M1, and the signal M1J3N changes from 0 to 1 (indicating that M1 is turned on), and the signal M2_ON changes from 1 to 0 (indicating that M2 is turned off), therefore, the M1 input changes from 1011 to 0000. And the M2 input changes from 0100 to 0100. At the time T13, the state jumps from S6 of M1 to S2 of M2, and the signal M1J3N changes from 1 to 0 (indicating that M1 is turned off), and the signal M2_ON changes from 0 to 1 (indicating that M2 is turned on), therefore, the M1 input changes from 1011 to 1011. And the M2 input changes from 0100 to 1001. The state changes between M1 and M2. The input value of M1 changes M2. The input value changes 1011—0000 0000—1001 20 200813751 M2^M1 〇〇〇〇->〇〇〇〇0100—0000 M “M2 1011—0000 0000 -> 1001 Table 2A uses the cutting logic of the combinatorial logic decomposition. When the state shifts between mi and m2, the input value of the finite state machine module is input.
狀態在Ml、M2間 Ml之輸入值變化 M2之輸入值變化 1011—1011 xxxx—>1001 1011—0000 0!00->0!00 轉移時，輸入有限狀態機次模組Ml、M2之輸入值變動狀況 (xxxx表任意值或隨意值） 表二A與表二b係分別為使用組合邏輯分解之切割架構 與使用第四圖之分解架構，狀態在有限狀態機次模組ΝΠ、M2 之間互相轉移時，輸入有限狀態機次模組Ml、M2之輸入值 變動狀況。根據上述之波形圖與下列表格資料，在第五A圖 與表二A中，當Ml與M2間互相狀態轉移時，會有M1與The value of the input value of M1 between Ml and M2 changes the input value of M2. 1011—1011 xxxx—>1001 1011—0000 0!00->0!00 When transferring, input the finite state machine module Ml, M2 The change of the input value (any value or random value of the xxxx table) Table 2A and Table 2b are respectively the cutting architecture using the combinatorial logic decomposition and the decomposition architecture using the fourth graph, the state is in the finite state machine module, M2 When transferring between each other, the input value changes of the finite state machine modules M1 and M2 are input. According to the above waveform diagram and the following table data, in the fifth A diagram and the second table A, when M1 and M2 transition state to each other, there will be M1 and
表二B使用第四圖之分解架構，狀態在]^^、M2間互相 21 200813751 M2之輸入同日寺改變之情況，此時mi、⑽都會有信號切換之 動作’亦即增加電路之峰值功率。另-方面，在第五B圖與 表二B中’當Ml與]vi2間互相狀態轉移時，並不會發生Ml 與1^2之輸入同時產生變化之情況，一定會有一個Ml或M2 之輸入是保持不動，例如··當目前狀態從M1轉移至M2時， Ml之輸入是ι〇11—1〇11維持不變。因此，本發明之分解架構 對正體有限狀恶機電路之峰值功率P〇Wer)係具有明顯地 降低之功效。Table 2B uses the decomposition structure of the fourth figure, the state is between ^^^, M2 and 21. The input of 200813751 M2 is changed in the same day. At this time, mi and (10) will have the action of signal switching', that is, increase the peak power of the circuit. . On the other hand, when the state transitions between M1 and vi2 in the fifth B and the second B, the M1 and 1^2 inputs do not change at the same time, there must be a M1 or M2. The input is kept still, for example, when the current state is transferred from M1 to M2, the input of M1 is ι〇11-1〇11 remains unchanged. Therefore, the decomposition architecture of the present invention has a significantly reduced effect on the peak power P〇Wer of the positive finite-nosed machine circuit.
Ml之輸入值變化 M2之輸入值變化 1 1000—1010 1 0000—>1001 2 1010->1011 2 1001—0001 3 1011—0000 3 0001-^0100 4 0000—0011 4 〇1〇〇->〇〇〇〇 5 0011—1011 5 0000-^1001 6 1011—0000 6 1001->1111 7 1111—1101 8 1101—0101 9 0101-^0100 —^. 表三A使用組合邏輯分解之切割架構，]vn、M2之所有 輸入變動 22 200813751Input value change of M1 Change of input value of M2 1 1000-1010 1 0000—>1001 2 1010->1011 2 1001—0001 3 1011—0000 3 0001-^0100 4 0000—0011 4 〇1〇〇-> ;〇〇〇〇5 0011—1011 5 0000-^1001 6 1011—0000 6 1001->1111 7 1111—1101 8 1101—0101 9 0101-^0100 —^. Table 3A uses a combinational logic decomposition of the cutting architecture ,]vn, M2 all input changes 22 200813751
Ml之輸入值變化 M2之輸入值變化 1 1000—1010 1 xxxx—1001 2 1010—1011 2 1001->0001 3 1011—0000 3 0001—0100 4 0000—0011 4 -——_ 0100-^1001 5 0011—1011 5 1001—1111 6 1111—1101 7 1101—0101 8 0101—0100 表三B使用第四圖之分解架構，]vq、M2所有輪入變動 (xxxx表任意值或隨意值） 表二A與表三B係分別為使用組合邏輯分解之切割架構 與使用第四圖之分解架構，有限狀態機次模組Ml、M2所有 輸入變動。就平均功率(average power)而言，平均功率之大小 係與Ml、M2總輸入變化次數有關。因此，比較表三A以及 表三B，從表三A中可發現，使用組合邏輯分解(CLD)之切割 架構時，Ml、M2輸入變動次數之總和是15 ;而從表三B中 可發現’使用本發明之分解架構時，Ml、M2輸入變動次數之 總和是13。由此，本發明之分解架構對整體有限狀態機電路 23 200813751 之平均功率係具有明顯地降低之效果。 凊參照第六圖，其為第三圖所示之實施例以第四圖分解 架構並以不同輸入實施之信號波形圖。此波形圖係僅用以說明 縱向所示之信號彼此間的相互關係，而其橫向係代表時間軸， 至於其他未標示之單位(例如電壓單位、時間單位)在此均省略 以求圖示之簡潔。在I時間點時，狀態從有限狀態機次模組 Ml之S6跳至有限狀態機次模組m2之S2，且信號Ml ON 從1變0 (表示關閉有限狀態機次模組Mi)，信號m2—ON從〇 變1 (表示開啟有限狀態機次模組M2)，因此，Ml輸入從ion 變1001，而M2輸入從χχχχ變1〇〇1。在時間點時，狀態 從M2之S7跳至Ml之S6,且信號Ml—ON從0變1(表開啟 Ml)，信號M2—ON從1變〇 (表關閉M2)，因此，Ml輸入從 1011變1011，而M2輸入從1101變1101。在Ti3時間點時， 狀態從Ml之S6跳至M2之S2，且信號MI-ΟΝ從1變0 (表 示關閉Ml)，信號M2_0N從〇變i (表示開啟M2)，因此， Ml輸入從1011變1011，而M2輸入從11〇1變1〇〇1。根據此 波形圖’有限狀態機次模組Ml、M2之輸入並不會同時改變， 例如·在時間點Ts時，僅改變]VL2之輸入；在時間點τ13時， 僅改變M2之輸入；甚至在時間點Tll時，有限狀態機次模組 Ml、M2之輪入均維持原輸入。 顯然地，依照上面實施例中之描述，本發明可能有許多 24 200813751 與差異。因此需要在其附加之權利要求項之細内加以 理解，除了上述詳細之描述外，本發明還可以廣泛地在盆他之 實施例中施行。上述僅為本發明之較佳實施_已，並_以 限林翻之㈣補細；凡其它魏縣發騎揭示精神 下所完成之等效改魏修飾，均應包含在町所述之中請專利 範圍内。 【圖式簡單說明】 第 A圖係有限狀態機電路之一種習知循序邏輯分解 (sequential logic decomposition ; SLD)之切割架構； 第一 B圖係有限狀態機電路之一種習知組合邏輯分解 (combinational logic decomposition ; CLD)之切割架構； 第二圖係本發明之一較佳實施例之概略系統方塊圖； 第三圖係一有限狀態機之狀態轉換圖（state transiti()n graph ； STG)； 第四圖係本發明依第三圖之實施例所實施之一較佳分解 架構圖， 第五A圖係第三圖之實施例以習知組合邏輯分解之切割 架構所實施之信號波形圖； 25 200813751 第五B圖係第三圖之實施例以第四圖之分解架構實施之 信號波形圖；以及 第六圖係第三圖之實施例以第四圖之分解架構並以不同 輸入實施之信號波形圖。 【主要元件符號說明】 110 有限狀態機電路 120 選擇模組 130 暫存模組 140 解碼模組 150 儲存模組 160 緩衝模組 102 第二輸入信號 104 第一輸入信號與第一狀態信號 112、 132 第二狀態信號 114 第一選擇信號 116、 122 輸出信號 124 第二狀態信號與第一選擇信號 134 第二選擇信號 142 第三選擇信號 162 延遲時脈 26M1 input value change M2 input value change 1 1000-1010 1 xxxx—1001 2 1010—1011 2 1001->0001 3 1011—0000 3 0001—0100 4 0000—0011 4 ———_ 0100-^1001 5 0011—1011 5 1001—1111 6 1111—1101 7 1101—0101 8 0101—0100 Table 3B uses the decomposition structure of the fourth figure, ]vq, M2 all round-in changes (xxxx table arbitrary or random values) Table 2A And Table 3B are respectively the cutting architecture using the combinational logic decomposition and the decomposition architecture using the fourth diagram, and all input changes of the finite state machine modules M1, M2. In terms of average power, the average power is related to the total number of input changes of M1 and M2. Therefore, comparing Table 3A and Table 3B, it can be found from Table 3A that when using the combination logic decomposition (CLD) cutting architecture, the sum of the number of M1 and M2 input changes is 15; and from Table 3B, it can be found 'When using the decomposition architecture of the present invention, the sum of the number of input changes of M1 and M2 is 13. Thus, the decomposition architecture of the present invention has a significant reduction in the average power system of the overall finite state machine circuit 23 200813751. Referring to the sixth diagram, which is a signal waveform diagram of the embodiment shown in the third figure, which is decomposed in the fourth diagram and implemented with different inputs. This waveform diagram is only used to illustrate the relationship between the signals shown in the longitudinal direction, and the horizontal system represents the time axis. Other unlabeled units (such as voltage units and time units) are omitted here for illustration. concise. At time I, the state jumps from S6 of the finite state machine module M1 to S2 of the finite state machine module m2, and the signal Ml ON changes from 1 to 0 (indicating that the finite state machine module Mi is turned off), the signal m2—ON changes from 〇1 (indicating that the finite state machine module M2 is turned on), therefore, the M1 input changes from ion to 1001, and the M2 input changes from χχχχ1 to 1. At the time point, the state jumps from S7 of M2 to S6 of M1, and the signal M1-ON changes from 0 to 1 (the table turns on M1), and the signal M2-ON changes from 1 (the table turns off M2), therefore, the M1 input is from 1011 changes to 1011, and the M2 input changes from 1101 to 1101. At the Ti3 time point, the state jumps from S6 of M1 to S2 of M2, and the signal MI-ΟΝ changes from 1 to 0 (indicating that M1 is turned off), and the signal M2_0N changes from 〇 to i (indicating that M2 is turned on), therefore, M1 is input from 1011. Change 1011, and the M2 input changes from 11〇1 to 1〇〇1. According to this waveform diagram, the input of the finite state machine module M1, M2 does not change at the same time, for example, at the time point Ts, only the input of VL2 is changed; at the time point τ13, only the input of M2 is changed; At the time point T11, the round input of the finite state machine modules M1, M2 maintains the original input. Obviously, the invention may have a number of 24 200813751 and differences in accordance with the description in the above embodiments. It is therefore to be understood that within the scope of the appended claims, the invention may be The above is only the preferred implementation of the present invention _ has been, and _ to limit the forest to (4) to make up the fine; the other equivalent Wei Wei decoration in the Weixian hair riding revealing spirit should be included in the town Please be within the scope of the patent. [A brief description of the diagram] Figure A is a conventional sequential logic decomposition (SLD) cutting architecture of the finite state machine circuit; the first B diagram is a conventional combinational logic decomposition of the finite state machine circuit (combinational) The second embodiment is a schematic system block diagram of a preferred embodiment of the present invention; the third diagram is a state transition diagram of a finite state machine (state transiti() n graph; STG); The fourth embodiment is a preferred decomposition architecture diagram of the embodiment of the present invention according to the third embodiment, and the fifth embodiment is a signal waveform diagram implemented by the conventional combination logic decomposition cutting architecture. 25 200813751 Figure 5B is a signal waveform diagram of the embodiment of the third figure implemented by the decomposition architecture of the fourth figure; and the embodiment of the third figure of the sixth figure is implemented by the decomposition structure of the fourth figure and implemented with different inputs. Signal waveform diagram. [Description of main component symbols] 110 finite state machine circuit 120 selection module 130 temporary storage module 140 decoding module 150 storage module 160 buffer module 102 second input signal 104 first input signal and first state signal 112, 132 Second state signal 114 first select signal 116, 122 output signal 124 second state signal and first select signal 134 second select signal 142 third select signal 162 delay clock 26