TW200816391A - Method of manufacturing split gate flash device - Google Patents

Abstract

A method for fabricating a split gate flash device is described. A substrate includes a memory cell region, a high voltage circuit region and a low voltage circuit region is provided. A first oxide layer is formed on the substrate in the high voltage circuit region. A second oxide layer is formed on the substrate in the low voltage circuit region. A first conductive layer is formed on the first and second oxide layers. A tunneling oxide layer is formed on the substrate in the memory cell region. Stack gate structures are formed on the tunneling oxide layer. A conformal third oxide layer is formed on the substrate in the memory cell region. A second conductive layer is formed on the third oxide layer. A portion of the second conductive layer is removed. The first conductive layer is patterned to form gates of the high/low voltage devices.

Description

200816391

Pt.ap653 21245twf.doc/t IX. Description of the Invention: [Technical Fields of the Invention] β 暇 relates to a method of manufacturing a semiconductor device, and particularly to a method for manufacturing a separated gate flash memory. [Prior Art] For HVt/, the body (nonvoIatile mem〇ry) is now used to store structure data, program 〇 2:44. Flash memory is a kind of non-volatile memory. It can perform multiple data storage, reading and erasure operations. It has become a fast-growing product in the semiconductor market. Recently, in order to reduce the manufacturing cost of a semiconductor element and simplify the process, it has been gradually developed to integrate the memory cell of the memory with the components of the peripheral circuit (P:hery circuit) on the same wafer. For example, if the flash memory and the peripheral circuit are integrated on the same chip, it is called edded fiash memory. In addition, in consideration of the reliability in the memory cell area I, the components in the peripheral circuit area are required to be high-performance (high perf〇rmance) and the voltage applied to the device, etc. There are 70 characteristics of the memory cell area and the peripheral circuit area, and oxide layers of different thicknesses are disposed between the gate or the stacked gate structure and the substrate, so that the components can be operated in operation. For example, FIG. 1 is a schematic view of a conventional flash memory structure. The structure includes a substrate 100, a dielectric layer 11 〇, a 611016 pt.ap653 21245 twf.doc/t high temperature oxide layer 112, The gate oxide layer 114, the stacked gate structure 120, the erase gate 140, the select gate 142, the gate 144 of the high voltage component, and the gate 146 of the low voltage component. The substrate 100 includes a memory cell region 102, a high voltage circuit region 104, and a low voltage circuit region 106. Each of the above regions is isolated by an isolation structure 108, and the high voltage circuit region 104 is combined with the low voltage circuit region 106 to be a peripheral circuit region. The stacked gate structure 120 includes a floating gate 122, an inter-gate dielectric layer 124, a control gate 126 and a cap layer 130, starting from the tunneling dielectric layer. The control gate 126 includes a doped polysilicon layer 126a and a metallization layer 126b. It is noted that the polycrystalline stone between the selective gate 142 and the floating gate 122 in the memory cell region 102. The internal polyoxidation (IPO) is composed of a high temperature oxide layer 112 and a gate oxide layer 114. The gate oxide layer between the gate 144 of the high voltage device and the substrate 100 in the high voltage circuit region 104 and the gate oxide layer between the gate 142 and the substrate 100 in the memory cell region 102 are also tunneled dielectric layer 110. The high temperature oxide layer 112 and the gate oxide layer 114 are formed. A gate oxide layer 114 is disposed between the gate 146 of the low voltage component in the low voltage circuit region 106 and the substrate 100. In order to increase the speed of memory erasing, the thickness of the polycrystalline oxide layer in the memory cell region is reduced. However, in the conventional flash memory, the polysilicon interlayer oxide layer in the memory cell region 102 has the same high temperature oxide layer 112 and gate oxide layer 114 as the gate oxide layer of the high voltage device, and is reduced in the memory cell region 102. At the same time as the thickness of the polycrystalline tantalum oxide layer, the thickness of the gate oxide layer of the high voltage 7 200816391 pt.ap653 21245twf.doc/t element is also reduced, which reduces the "Time_Dependent Dielectric Breakdown (TDDB)". The test value causes the life of the high voltage component to be shortened, so that the reliability of the high voltage component is lowered. 'In addition, the gate oxide layer in the high voltage circuit region 1〇4 and the low voltage circuit region 1〇6 is separated from the edge of the structure 108. In the manufacturing process, the cleaning process is thinned to reduce the electrical properties of the high voltage component and the low voltage component. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a method for fabricating a split gate flash memory. The thickness of the gate oxide layer of the high voltage component can be increased. A further object of the present invention is to provide a method for manufacturing a split gate flash memory, which can solve the high voltage. The problem of thinning the gate oxide layer at the edge of the isolation structure in the road area and the low voltage circuit area. The present invention provides a method for manufacturing a separated gate flash memory, which first provides a substrate including a memory cell region, a high voltage circuit region, and a low voltage circuit region, {; and a plurality of isolation structures have been formed in the substrate. Then, the substrate in the high voltage circuit region is depleted of a first oxide layer. Then, a second oxide layer is formed on the substrate in the low voltage circuit region. Next, a first conductor layer is formed on the first oxide layer in the high voltage circuit region and the second oxide layer in the low voltage circuit region, and a tunneling oxide layer is formed on the substrate in the memory cell region. Subsequently, A plurality of stacked gate structures are formed on the tunnel dielectric layer in the cell region. Subsequently, a conformal third oxide layer is formed on the substrate in the cell region. Furthermore, the brother in the cell region Forming a second conductor layer on the trioxide layer. Subsequently, the second conductor layer in the region is removed. Then, the first conductor layer is patterned, 8 200816391 pt.ap653 21245twf.doc/t in the high voltage circuit region Forming a plurality of high-voltage component road regions The gate of a plurality of low voltage components. According to the preferred embodiment of the present invention, in the method of edge separation of the above-mentioned separated interpoles, the stacking gate structure includes starting from the crossing layer. In order to be the first, the gate, the inter-gate dielectric layer, the second gate, and the cap layer. According to a preferred embodiment of the present invention, in the method of manufacturing the u body, the stacked gate structure Furthermore, the gap i: ct;:;, the cover layer and the second gate are both sides, and are located on the inter-gate dielectric layer. In the method for manufacturing the flash memory according to the preferred embodiment of the present invention, The material of the first gate is flashed, and the material of the 'electrode layer in the above-mentioned isolated or oxidized layer' includes the oxygen-cutting method in the flash memory according to a preferred embodiment of the present invention. One or two, the knife is away from the gate or polycrystalline stone. The material of the gate is doped polycrystalline as in the preferred embodiment of the present invention. In the manufacturing method of the flashing body, the top + stripping pole is in accordance with a preferred embodiment of the present invention. Including emulsifying stone eve. In the manufacturing method of the flash memory, Yu Xin = in the above-mentioned * off gate in the Gaochangjian circuit area 3^ into the first 氡 layer. Then, the removed first-patterned mask layer is removed. The solidified cover layer covers the first oxide layer. c

L 200816391 pt.ap653 21245twf.doc/t Next, remove the first patterned mask layer. According to a preferred embodiment of the present invention, in the above method of manufacturing the separation of the dummy/memory, the first conductor layer is formed by forming a first conductor material layer on the soil floor. Next, a second patterned mask layer is formed over the layer of conductive material in the high voltage circuit region and the low voltage secret region. Then, the first layer of conductor material not covered by the second patterned mask layer is removed. Next, the second patterned mask layer is removed. According to a preferred embodiment of the present invention, in the above method of fabricating a separate flash memory, a method of removing a portion of the second conductor layer in the memory cell region includes an etch back method. The present invention provides a method for fabricating a split gate flash memory, the first, and the germanium substrate, including a memory cell region, a high voltage circuit region, and a low voltage circuit region. ^ Forming a first oxide layer on the substrate. Furthermore, a multi-separation structure is formed in the substrate. Next, the first of the memory cell region and the low voltage circuit region is removed. Then, a second oxide layer is formed on the substrate in the low voltage circuit region. The first conductor layer is formed on the first oxide layer in the south (four) road region and the germanium layer in the low voltage circuit region. Next, the 匕 in the memory cell: 化化. After the tunneling dielectric in the memory cell two-co-structure. Following the 'basicization in the memory cell area' Furthermore, the third oxygen layer in the memory cell region: then, the first conductor layer is patterned to form a plurality of low voltages between the two voltage elements in the high voltage circuit region and in the low voltage circuit region 10 200816391 pt. Ap653 21245twf.d〇c/t In accordance with the present invention, the smear of the flash memory is only described by the fine W, and the first gate of the separation gate is formed by the above-mentioned separation gate to form the first map. The upper layer covered by the upper layer is removed, the first layer is not patterned, and then the first patterned layer is removed. Then, the proposed separation layer is removed. Quick memory o Selective gate gate oxide layer - palladium reporter, & 3 彳 隹 釭 釭 亚 亚 亚 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 土 土 土The thickness to increase the test value of TDDB can prolong the life of high-order components and improve the reliability of high-voltage components. After the gate oxide layer of the device and the low voltage component, the conductor layer for forming the closed electrode is formed directly on the gate oxide layer: thus y is used to improve the interlayer oxide layer at the edge of the isolation structure in the south and low voltage circuit regions. The problem of thinning due to the cleaning process is to improve the electrical properties of the high-voltage component. The features and advantages of the above-mentioned and other objects of the present invention are more clearly understood, and the preferred embodiments are exemplified below. The drawings are described in detail below. [Embodiment] FIG. 2A to FIG. 2B are cross-sectional views showing a manufacturing process of a split gate flash memory according to an embodiment of the present invention. First, please refer to Figure 2Α. A substrate 200 is provided, such as a tantalum substrate. The substrate 200 includes a memory cell region 202, a high voltage circuit region 2〇4 and a low voltage circuit region 206, and an isolation structure 2〇8 has been formed in the substrate 200, and each region is isolated by the isolation structure 208. The combination of the high voltage circuit region 204 and the low voltage circuit region 206 is a peripheral circuit region. In addition, the ion implantation process can be performed on the memory cell 2〇2, the high voltage device region 2〇4, and the substrate 200 in the low voltage device region 206, respectively, for the memory cell region 202, the high voltage device region 2G4, and the low voltage device region. The #well zone and other doped zones are formed in the substrate 200. For the towel, the ion implanted material may be either n-type or p-type, depending on the design of the component. And its process

The method should be well known to those of ordinary skill in the art and will not be described again. Next, an oxide layer 21 is formed on the substrate 200. The material of the oxide layer 21 is, for example, oxidized ten, and its formation method is, for example, a thermal oxidation method. In the present embodiment, the isolation structure 2〇8 is formed in the substrate 200, and the oxide layer 21G is formed on the substrate 200, but is not intended to limit the present invention. In another embodiment, an oxide layer 21〇 may be formed on the substrate, and an isolation structure 2〇8 may be formed in the substrate 200, and the isolation structure is applied to the shallow trench isolation structure, and the axis method is It is generally known to the person skilled in the art, so it will not be repeated here. The 'k' cup is shown in Fig. 2B, and a patterned grass layer 212 is formed on the oxide layer 210 in the memory cell 2〇2 and the surface electrode 2〇4. The circuit [ 然 ^ ' removes the unmasked mask j 212 covering the wire oxide 210 ' and the south voltage circuit region 204 Φ ® π Λ Λ γ p 元件 p element gate d down the oxide layer 210 as a high voltage component The gate layer, the removal method is, for example, a dry method. 202 ^ In this example, the conversion mask layer 212 is formed on the oxide layer 21 () in the memory cell area and the touch circuit area, and 12 12,216,391 pt.ap653 21245 twf.doc/t mask layer 212 is used as In the case of the mask, only the oxide layer 210 in the low voltage circuit region 2〇6 is removed, and the oxide layer 21〇 in the memory cell region 2〇2 is removed in the subsequent process. In another embodiment, the patterned mask layer 212 can be formed only on the oxide layer 21〇 in the stamping circuit region 204, so that when the pattern=layer 212 is used as a mask, the unmasked layer is simultaneously removed. The oxide layer in the memory cell region 202 and the low voltage circuit region 2〇6 is rewritten by the patterned mask layer. Next, referring to FIG. 2C, the patterned mask layer 212 is removed, and the removal method is, for example, ash. Or engraving. Then, an oxide layer 214 is formed on the low-voltage circuit region 2 (10) / soil bottom, and the formation method thereof is, for example, dry oxygen, = method or 疋 in situ vapor generation (m situ ste_qing (10) 廿〇 n, ISSG) #舜Referring to FIG. 2D, a conductor layer 216, a melon, a gasification layer, and a ruthenium layer 214 are formed on the substrate 200. The conductor sound is, for example, a material solution method of doping the V body layer 216 to form a green color, for example, first chemical vapor deposition, refining the poly(four) layer, and then performing a doping process, or - pre-rolling The phase deposition method forms a field-doped polysilicon layer. The conductors 1 in the layer circuit region 204 and the low voltage circuit region 206 are patterned to form a mask layer 218. The covered 'body 4' is removed, and the unmasked mask layer 218 is removed to cover the reed 210, leaving the oxygen 216 formed in the high voltage circuit region 204. Wherein the conductor layer 218 of the conductor layer 216 on the oxide layer 214 in the region 206 is covered by the conductor layer. Next, the patterned mask is removed 13 200816391 pt.ap653 21245twf.d〇c/t Layer 218 The removal method is, for example, ashing or side method. Next, referring to Fig. 2F, the oxide layer 21A on the substrate 200 in the memory cell region 2'2 is removed, and the removal method is, for example, a dry side method. A tunneling oxide layer 220 is formed on the substrate 200 in the memory cell region 2〇2. The material of the teeth with the dielectric layer 22 is, for example, oxidized stone, and the method of forming it is, for example, a thermal oxidation method. Thereafter, a stacked gate structure 222 is formed on the pass-through dielectric layer 220 in the memory cell region 2〇2. The stack gate structure 222 is, for example, sequentially first from the tunnel dielectric layer 22, the pole 224, the idle dielectric layer 226, the second idle pole 228, and the cap layer 23 = the stack gate structure 222 The utility model further includes a spacer layer, a top cover layer and a second interpole, and two side walls, and the material of the dielectric layer 226 of the gate is 226, and the material of the middle gate 224 is, for example, doped polycrystalline stone. The shape f method is, for example, a chemical vapor deposition method to form an undoped multi-(four) layer tantalum bonding process; or a direct chemical vapor deposition method; The material of the inter-gate dielectric layer is, for example, yttrium oxide or yttrium/mouse/oxygen cutting, and the formation method thereof is, for example, chemical vapor deposition. The material of the gate 228 is, for example, a conductor layer, such as doped polycrystalline stone or bis = 8a and a metal ceramsite island. The method for changing the polycrystalline spine is the same as that of the first gate 224, and the materials of the metallization layer are, for example, Wei He, Wei Qin, Wei D, and Wei Zhi as the floating gate; TM 14 200816391 Ptap653 21245twf.doc/t In addition, the top cover layer 230 is, for example, a single layer of the junction 2 and the top cover layer is composed of two layers, such as the material of the top cover layer, such as oxidized stone, gasification, and gas. Oxidize H. The single-layer cap layer is formed by, for example, forming a cap material layer, other suitable materials, and removing a portion of the cap material layer by etching. Further, the material of the anisotropic layer 230a is, for example, a top cover of a nitride nitride or oxynitride structure, and the material of the cap layer 230b is, for example, a tetra-bright material.

O material. The top cover layer 2 is applied to the top cover layer 2 to form a layer of the top cover layer 2 on the layer of the bird layer or the other suitable substrate 2〇0, for example, the material layer before the substrate layer, and then the steering property is diligently ^The cover layer 2 is formed by stacking the structure milk of the stack, for example, the above-mentioned material layer of the knife. The material layer of the f layer, and then patterning all the surfaces of all the above-mentioned eggs, 曰, until the tunnel dielectric layer, please refer to 2G, in the base layer 234. The formation method of the oxide layer 234 is a deposition process for forming a conformal cerium oxide. A high temperature oxidation followed by a material in the oxide layer is, for example, doping = (4). The layered vapor deposition method forms an undoped multi-turn correction method, for example, by chemically constructing a portion of the conductor layer in the Γ2, "the outermost one of the stacks 222, 236, and the stacking gate junction forming a fourth The whip of the structure 222 can remove the high voltage circuit region 204 and the low voltage 15 200816391 pt.ap653 21245twf.doc/t secret area, the method of removing the conductor layer, for example, is again According to Figure 2H, the patterned conductor layer 2]6 = very fine between the seam elements formed in the road zone 204, The pole 242 between the health components is formed in the power grid, and when the conductor /^\206 is patterned, the high voltage circuit region 2〇4 and the low voltage circuit tunneling dielectric layer 220 and the oxide layer 234 are patterned and patterned. . — . The oxidized layer of the occupational layer of the e (four) (four) component

The above is formed separately, not with the fourth 238 (select = (by the thickness of the gate layer 21 by the tantalum oxide layer 220 and the oxide layer 234), so that the thickness of the gate oxide layer of the high-depletion element can be effectively increased. In addition, since the thickness of the service layer of the high-voltage component is increased, the test value of the TDDB can be improved, and the life of the two components can be improved, and the reliability of the high-voltage component can be improved.

In addition, since the oxide layer 21Q and the oxide layer 214 in the high voltage circuit region 204 and the low voltage circuit region 2〇6 are formed, the conductor layer 216 for forming the gate is directly formed on the oxide layer 21 and the oxide layer 214. Therefore, the problem that the oxide layer 210 and the oxide layer 214 at the edge of the isolation structure in the high-voltage circuit region 204 and the low-voltage circuit region are changed by the cleaning process can be improved to improve the electrical properties of the high-voltage component and the low-voltage component. In summary, the present invention has at least the following advantages: 1. In the manufacturing method of the split gate flash memory proposed by the present invention, the gate oxide layer of the ink element is formed separately in the process, and thus Effectively increase the thickness of the gate oxide layer of the high voltage component. 2. The manufacturer of the split gate flash memory according to the present invention 16 200816391 pt.ap653 21245twf.doc/t The high voltage component manufactured by the method has a high TDDB test value, a long service life and a high Reliability. 3. The method for cracking the split gate flash memory proposed by the present invention can improve the problem that the gate oxide layer at the edge of the isolation structure in the rolling circuit region and the low voltage circuit region is thinned by the cleaning process, so The formed high voltage component and low voltage component have better electrical properties. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and anyone skilled in the art can make some modifications when not in the range of t, so the present invention == Capricorn is subject to the definition of the patent application scope attached to it. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a conventional split gate flash memory structure. FIG. 1 is a schematic diagram showing the manufacturing process of the flash memory of the present invention. FIG. Sectional view. [Main component symbol description]

100, 200: substrate 102, 202: memory cell region 104, 204: high voltage circuit region 106, 206: low voltage circuit region 108, 208 · isolation structure 110, 220 · dielectric layer 112 · south temperature oxide layer 114: Gate oxide layer 17 200816391 pt.ap653 21245twf.doc/t 120, 222: stacked gate structure 122: floating gate 124, 226: gate dielectric layer 126: control gate 126a, 228a: doped polysilicon layer 126b 228b: metal telluride layer 130, 130a, 130b, 230, 230a, 230b: cap layer 132, 232: spacer 140: erase gate 142: select gate 144, 240: gate 146 of high voltage component, 242: gates 210, 214, 234 of low voltage components: oxide layers 212, 218: patterned mask layer 216: conductor layer 224: first gate 228: second gate 236: third gate 238: fourth Gate 18

Claims (1)

200816391 pt.ap653 21245twf.doc/t X. Patent Application Scope 1. A method for manufacturing a separated gate flash memory, comprising: providing a substrate including a memory cell region, a high voltage circuit region and a low voltage a circuit region, and a plurality of isolation structures are formed in the substrate; a first oxide layer is formed on the substrate in the high voltage circuit region; and a second oxide layer is formed on the substrate in the low waste circuit region; Forming a first conductor layer on the first oxide layer in the high voltage circuit region and the far oxide layer in the low voltage circuit region; forming a tunneling oxide layer on the substrate in the memory cell region; Forming a plurality of stacked gate structures on the tunneling dielectric layer in the memory cell region; forming a conformal third oxide layer on the substrate in the memory cell region; and the third in the memory cell region Forming a second conductor layer on the oxide layer, (part of the second conductor layer in j; and a high voltage one: body layer) to form a plurality of gates in the high voltage circuit region. f... (4) forming in the low voltage circuit region Multiple low friction components 2. If applied The split gate flash memory according to the first item of the first aspect of the present invention comprises: a gate dielectric layer and a second gate top 19 from a dielectric layer, and a second gate top 19 200816391 pt.ap653 21245twf. The manufacturing method of doc/t, in which the 43th of the first gate body is 2, the distraction described in the second item. 5 5. If the patent application scope is 2nd, the heart of the bamboo, the handsome polycrystalline 'Mi w item The method for separating the gates is described in which the gates of the gates are 从6 from the soil ^, the net memory > the stone eve / the nitrite eve / the oxidized stone eve o system ^ ^ 1 1 Isolation of the Yimen ▲ White (4), the material of the second questioning pole is: :::Recalling the body of the metal. _ Shi Xi or polycrystalline 7. The separation gate described in the second paragraph of the patent scope The method of the method of manufacturing, wherein the material of the county layer includes nitrogen cutting, and the method of separating the idle flash and the traitor, as described in Item 1 of the system A, the quilting of the electric towel on the substrate. The method of forming an oxide layer includes: forming the first oxide layer on the substrate; and forming the first oxide layer in the circuit region a grading-patterned mask layer; 移除 removing the quaternary layer that is not covered by the first _ mask layer; and removing the first patterned mask layer. The method for separating a gate flash memory according to any one of the preceding claims, wherein the method for forming the first conductor layer comprises: forming a first conductor material layer on the substrate; Forming a second patterned mask layer on the conductive material layer 20 in the circuit region 20 200816391 pt.ap653 21245twf.doc/t; removing the first conductive material layer not covered by the second patterned mask layer And removing the second patterned mask layer. A method for manufacturing a split gate flash memory according to claim 1, wherein a portion of the second cell layer in the memory cell region is removed by a retrace method. A method for fabricating a split gate flash memory, comprising: providing a substrate comprising a memory cell region, a high voltage circuit region and a low voltage circuit region; forming a first oxide layer on the substrate; forming in the substrate a plurality of isolation structures; removing the memory cell region and the first oxide layer in the low voltage circuit region; forming a second oxide layer on the substrate in the low voltage circuit region; the first in the high voltage circuit region Forming a first conductor layer on the second oxide layer in the oxide layer and the low voltage circuit region; forming a tunneling oxide layer on the substrate in the memory cell region; and forming the tunneling layer in the memory cell region Forming a plurality of stacked gate structures on the electrical layer, forming a conformal third oxide layer on the substrate in the memory cell region; forming a second conductor layer on the third oxide layer in the memory cell region; Remove part of the memory cell a second conductor layer; and patterning the first conductor layer to form a plurality of gates of the 21L 161816 pt.ap653 21245 twf.doc/t south voltage 7L in the high voltage circuit region, and forming the low voltage circuit region The gate of a plurality of low-voltage components. _ The method for manufacturing a split gate flash memory according to claim 11 wherein the stacked gate structures comprise from the pass-through dielectric layer —The gate, the dielectric layer of a gate, the second pole, and the top layer. The square gate of the body is the flashing memory of the separation gate described in item 12, f—method, 〃, middle The stacked gate structure further includes a spacer wall located on the two sides of the top layer and the second gate, and located on the dielectric layer of the gate. The manufacturing of the body is as described above. The materials of β* and Zhongwuhai gates include doped polysilicon. 15·The manufacturing method of the 12th body of the patent scope of the patent, in which the knife of the human body is very fast flash memory fossil eve / nitrogen cut / oxygen _ towel is (four) 1 The electric layer (4) is covered by the material or the oxygen is i; the 12 items of the body are _ extremely fast flash memory crystal slabs of metal. / ' M pole material is a push晶石夕或多 17. As in the manufacturing method of the 12th item of the scope of the patent application, the knife in t, I has a flash flash memory. 18. If the application of the /jr layer (4) includes nitriding eve. a manufacturing method, wherein; the separation gate of the separated gate flash memory layer and the low-circuit area of the low-voltage circuit region in the high-voltage circuit region; - forming on the rolled layer - first Figure 22 200816391 pt.ap653 21245twf.doc / t removing the first oxide layer not covered by the first patterned mask layer; and removing the first patterned mask 19. The method of manufacturing the split gate flash memory of claim 11, wherein the method of forming the first conductor layer comprises: forming a first conductor material layer on the substrate; Forming a second patterned mask layer on the conductive material layer in the south voltage circuit region and the low voltage circuit region; removing the first conductive material layer not covered by the second patterned mask layer; And removing the second patterned mask layer. 20. The method of fabricating a split gate flash memory according to claim 11, wherein a portion of the second cell layer in the memory cell region is removed by a re-etching method. C 23