TW200411788A - Manufacturing method for MCM package - Google Patents

Abstract

A manufacturing process for MCM (multi-chips-module) package includes the following steps. First, a plurality of first packages and second packages, and an intermediate carrier strip are provided. The intermediate carrier strip has a plurality of intermediate carrier units. Each intermediate carrier has an opening, a first surface and a second surface. Second, each first package is provided on the first surface corresponding thereto in order to electrically connect to the corresponding intermediate carrier unit. After that, a film is provided and the intermediate carrier strip and the first packages attached thereto are flipped on the film via the back surfaces of the first packages. Then, the second packages are disposed onto the intermediate carrier strip. Finally, the intermediate carrier strip is separated into a plurality of individual intermediate carrier units in order to form a plurality of MCM packages having the first package, the second package and the individual intermediate carrier unit. The intermediate carrier strip has enough space for performing punch and pick-up steps such that improve the pick-up step and alignment step.

Description

200411788 V. Description of the invention (1) (1), [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor package structure, and more particularly to a method for manufacturing a multi-chip package structure using an intermediate carrier strip.

(1) L. Previous technology J. In recent years, as the design of electronic products has been gradually developed toward the trend of small area, light weight, thin thickness, high function, and high performance, semiconductors = have been developed towards system module structures to enable semiconductor structures. The manufacturing process of garments and the testing of garments can be simplified and more efficient. Generally speaking, the polycrystalline silicon and the system are composed of at least two packages, which can be a side-by-side type. As shown in Figure 1, the two packages On the carrier board 13 and through the conductive element 14 (^ Pingguangtong. In addition, the multi-chip package structure can also be-three-dimensional stack_bujie (stack-type (as shown in Figure 2)) or a stack mode package configuration (shown in FIG 3 ~ FIG. 4). Conversely said perspective first, referring to FIG. 2, the first package body 21 by a system eleven electrically flip-chip connected to the first carrier plate 211, a brother b The solar chip 212 is made of the second chip 222 in a flip-chip manner. The mounting body 22 includes the first package 21 and the second package 22, and the carrier plate 221. Yes = chip package (MCM package) The first === body or a conductive element 213 (such as a solder ball) on its lower surface (excluding the second and second package bodies 22 being electrically conductive. The first figure) is used for the electrical element 223 on its lower surface ( (Not shown in the figure) the body also includes the signal of the second conductor 21 and the second package 22) used to pass the first package 1 back, such as with the motherboard or 200411788 (2) Description '---- the other electronic device is electrically connected. Shijie =, please refer to Figure 3 and Figure 4, which is another stacking mode package structure mentioned above. It should be noted that the reference symbols of each component in Figure 3 and Figure 4 are the reference symbols of each component in Figure 2 Corresponding. The intermediate carrier board has a port 201, and a second chip 222 in the second package body is received in the opening 201, and is connected to the first package body 21 through an intermediate carrier board unit 20. . Wherein, the first package 21 further includes a first conductive element 213 (such as a solder ball) on its lower surface (not shown in the figure) for electrical conduction with the intermediate carrier unit 20, and the middle of the board unit 20 A third conductive element 23 (such as a solder ball) is formed on the surface to be electrically conductive with the first package 22. The second package M also forms a second conductive element 223 on its lower surface for transmitting the signals of the second package 22 and the signals of the first package 21 through the intermediate carrier unit 20 and communicating with the outside, such as It is electrically connected with the motherboard or other electronic components. • Among them, the packaging steps of the multi-chip package structure shown in FIG. 3 are as follows: first, an intermediate carrier board unit 20, a first package body 21, a second, and a garment 22 are provided, which are respectively formed with a first conductive layer; The element 213 and the second conductive element 2f 3-on it. Then 'provide a jig board 24 (as shown in FIG. 5), and use the protruding pad 241 on the jig board 24 (its height is slightly larger than the overall height of the multi-chip package structure after packaging is completed). Into the opening 242 of the back 4. Then, the intermediate carrier board tooling body 22 is placed on the second carrier body 22, so that the second chip 222 in the second package body 22 can be held in a port 201, and temporarily fixed to the third conductive element 23 by Second seal = 2 on the second carrier board 221. Then, the first package body is temporarily fixed on the intermediate carrier board unit 20 by the first V electrical component 213.

200411788 5-Description of the invention (3) " ----- When the first conductive element 213 and the second conductive element 22 3 are refreshed, the first package 21 and the intermediate carrier unit 2 are processed. And the second interconnected and fixed. Since the thickness of the wearable body 22 is relatively small, and there is not enough time for the machine to pick it up to place it on the second package 22. In addition, $ ::: yuan = the size of the second package 22 is similar, & the middle carrier board list: When 20 people are connected to each other and the government body 22 is connected, it is impossible to perform positioning correction. Therefore, how to solve the above problems is the main spirit of the present invention. It has the structure and structure, with the number a in the method coefficients, integrated in the middle, and the first placed on the rubber plate unit film to form the unit system, [invention in view of the above-mentioned improvement of the manufacturer previously included the following two package body load Contents of the board] Questions, methods, and technical steps: And the purpose of the present invention is to use the questions provided. Firstly, the present invention provides a plurality of interlayer carrier strips, and each of these intermediate systems provides a multi-chip packaged multi-chip package with a special multi-chip package structure to manufacture a plurality of first packages and a plurality of first surfaces. And a second surface, such as an intermediate carrier board unit, on a package film, and the second table includes a plurality of unitary connections between the first bonding board and the middle surface. On the first surface of the multi-chip package. After that, a carrier strip is provided to borrow the second package body. Finally, the packaging unit is divided. The second package middle carrier strip carrier unit is provided with the first packages so that they correspond to the corresponding one of the adhesive films, and the back side of the first package after the connection is mounted and removed. In the glue, each multi-chip package and an independent intermediate system after the singulation has a plurality of openings disposed on the intermediate carrier strip.

200411788

Carrier board unit. There are-slots m between the carrier strips, and the space of each intermediate carrier unit is to be punched: the independence of the system "the intermediate carrier unit has a larger space to cut the steps. Again *, because there is enough carrier unit r on the middle carrier strip, the first package or the second package and the middle are free of the second ^, it is better to use the positioning point for positioning correction to avoid problems. Or the position deviation of a single body when it is set on the intermediate carrier unit (four), [Embodiment] The related drawings of the makeup will explain the structure of the multi-day Japanese film packaging structure according to the preferred embodiment of the present invention. Production method. Figures 6 to 10 disclose a method for manufacturing a multi-chip package structure according to a preferred embodiment of the present invention. 6 and FIG. 7, first, a plurality of f-packages 31 and-intermediate carrier strips 3 are provided. The intermediate carrier strip 3 has a plurality of intermediate carrier plates τ〇30. Wherein, each of the intermediate carrier board units 30 has an opening 301, a first surface 302, and a second surface 300 (as shown in FIG. 7); and each intermediate carrier board unit 30 has a The slot hole 304 (slot) may also be a cutting line (not shown in the figure). The first package 31 includes at least a first chip 312 and a first carrier board 3u. The first chip 312 and the first carrier board 31 are electrically connected in a flip-chip package. However, the above-mentioned first package body may also be a wire-type package body, that is, the first chip 312 may also be electrically connected to the first carrier board 311 by wire bonding (not shown in the figure). Among them, the first package body 31 further includes a first conductive element 313 (such as a solder ball) in the 200411788 V. Description of the Invention (5) --- the lower surface of a carrier plate 311. Next, as shown in FIG. 7, after the first packages 3 丨 are disposed on the first surface 302 of the intermediate carrier units 30, a reflow step is performed to enable the first conductive elements 313 to enable the The first package 31 is fixed and electrically connected to the corresponding intermediate carrier units 30. Further, after the reflow step, but can be a primer (under-fill) filling step (not shown in the figures) intermediate the first surface 30 of the carrier plate unit 302 of the first package body 31 of the first The lower surface of the carrier plate 3 11 further strengthens the connection strength between the first package body 3 丨 and the intermediate carrier plate element 30. Furthermore, as shown in FIG. 8, an adhesive film 4 is provided, and the connected first package bodies 31 and the intermediate carrier strip 3 are turned over to make the first chip in the first package bodies 31. The back of 312 is fixed on the adhesive film 4. Afterwards, as shown in FIG. 9, a plurality of second packages 32 are provided, which include at least a second chip 322 and a second carrier board 321, and the second chip 322 is connected to the second carrier board 3 2 1. The chip package is electrically connected. Wherein the second package body 32 further comprises a second conductive element 323 (e.g., solder balls) to the second carrier plate 321 beneath the surface. Next, a plurality of third conductive elements 305 (such as solder balls) are disposed on the second surface 3O3 of the intermediate carrier units 30. The second packages 32 are respectively set to correspond to the openings 301, and a reflow operation is performed to make the second packages 32 and the second surface 30 of the intermediate carrier unit 30. 3 interconnected. In addition, after the re-soldering step, an under-fill filling step (not shown in the figure) may be performed on the second surface 303 of the intermediate carrier unit 30 and the second loading of the first package body 32. Between the upper surfaces of the boards 321 to further strengthen the connection between the second package body 32 and the intermediate carrier unit 30.

Page 12 200 411 788 V. invention is described in (6) intensity. Carry out the encapsulation steps ^ H ^ performed-cutting step, in order to form a plurality of multi-wafer mounting orders at the slot 3 04 on the middle carrier strip 3: between the carrier strip 3 and remove the adhesive film 4 contains the first package body 31 and the first package body of each multi-chip package unit system board unit 30 (as shown in FIG. 10). If the body 2 is an independent middle-loaded cutting line, the cutter can be used. : 30 of the intermediate board units are -steps. The cutting step is performed by a knife or laser cutting method. Finally, the adhesive film 4 is removed to form a plurality of multi-wafer packages το. The 'per-multi-chip #' unit includes the first package body ^ a package body 32 and the separated intermediate carrier board unit 30. In the above-mentioned manufacturing method of the multi-chip package structure, the stupid cow ㈣ 3 ί can also be fixed on the adhesive film 4 V-, and then a step of dividing the middle carrier strip 3 is performed first, that is, before the middle A cutting step is performed at the slot 304 on the carrier strip 3 to judge the intermediate carrier strip 3 without dividing the adhesive film 4 so as to form the intermediate carrier strip into a plurality of independent carrier board units 30, and then The second packages 32 are respectively set to correspond to the openings S and so on S, and a reflow operation is performed to make the second packages 32 and the second surface 3 of the intermediate carrier unit 30. 3 Interconnection: In addition, in the manufacturing method of the above-mentioned multi-chip package structure, the first package body 31 and the first conductive element 313 can also be temporarily fixed and electrically connected to the corresponding intermediate carriers by the first package 31 and the first conductive element 313. After the board unit 30, an adhesive film 4 is provided to overturn the connected first packages 31 and the intermediate carrier strip 3 to continue the connection between the second package 32 and the intermediate carrier strip 3. Steps before proceeding

200411788 V. Description of the invention (7) '-a step of knowing and an under_fill filling step (not shown in the figure) to further strengthen the first package 31, the second package 32 and the intermediate carrier unit 30 connection strength. Since the mid-carrier strip 3, each of the intermediate carrier plate means having a slot 304 between 3〇, so independent of the ratio of the intermediate carrier plate means having a step between more 3〇 * sufficient for performing the punching or cutting. In addition, it can also provide a larger one: two Γ side positioning points, such as the 301 edge (not shown in the figure) at the middle of the single carrier 30 yuan (not shown in the figure), two packages 32 and the middle carrier unit 3〇 When connected = body-31 or brother to perform positioning correction to avoid the first-package; use a position to shift the position of the middle carrier board unit 30 = or brother two package 32 set above is only an example Sex, and the spirit and scope of the present invention, and it is the limit, sex. Any equivalent modification or change that should be included in the attached patent application:

Page 14 200411788 Brief description of the drawings (Wu), [Simplified description of the drawings] Fig. 1 is a schematic diagram showing a conventional multi-chip package structure of a side-by-side type. FIG. 2 is a schematic diagram showing a conventional three-dimensional stack type multi-chip package structure. FIG. 3 is a schematic cross-sectional view showing another conventional three-dimensional stack type multi-chip package structure with an intermediate carrier board. FIG. 4 is an exploded view showing a multi-chip package structure corresponding to FIG. 3.

FIG. 5 is a schematic diagram showing the structure of a fixture plate. 6 to 10 are schematic views showing a method for manufacturing a multi-chip package structure according to a preferred embodiment of the present invention. Description of component symbols: 11 First package of planar multi-chip package structure 12 Second package of planar multi-chip package structure 13 Carrier board 14 Conductive element

20 Intermediate carrier unit 201 Opening of intermediate carrier 21 First package 211 First carrier 212 First wafer 213 First conductive element

Page 15 200411788 Brief description of the drawings 22 The second package 221 The second carrier board 222 The second wafer 223 The second conductive element 23 The third conductive element 24 The fixture plate 241 The protruding pad 242 The opening of the fixture plate 3 The middle carrier strip 30 Intermediate carrier board unit 301 Opening of intermediate carrier board 302 First surface 303 Second surface 304 Slot hole 305 Third conductive element 306 Anchor point 31 First package 311 First carrier plate 312 First wafer 313 First conductive element 32 Second package 321 Second carrier 322 Second wafer 323 Second conductive element

Page 16 200411788 Simple illustration of the picture 4 Adhesive film Picture off Page 17

Claims (1)

200411788 Sixth, the scope of patent application is an intermediate carrier board, a first table1. A manufacturing method of a multi-chip package structure, including: providing a plurality of first packages and a plurality of second enclosures; providing an intermediate carrier board, The intermediate carrier board strip has a plurality of units, and each of the intermediate carrier board units has an opening surface and a second surface; the first packages are arranged on the first table of the intermediate carrier board units to cover the corresponding ones. The openings, the first packaging system are 22, 15 and the intermediate carrier board units are electrically connected; ~ < the second packages are respectively provided in the corresponding openings so as to be connected to the intermediate On the second surface of the carrier board unit, the second packages are electrically connected to the intermediate carrier board units; and "to report the intermediate carrier board strips to form a plurality of multi-chip package units, each wafer The packaging unit includes a first package body, a second package body, and an separated intermediate carrier board unit. 2 · The manufacturing method of the multi-chip package structure as described in the first patent application scope, which further includes providing an adhesive film to borrow the back of the first packages and the intermediate carrier strips after connection disposed on the film for the second package body and the like disposed on the second surface of the intermediate carrier such panel units 03 of the range-patent items as many as the second method of manufacturing a package structure of a wafer, wherein The connected first packages and the intermediate carrier strip are arranged in front of the adhesive film, and further include a flip of the connected first packages and the intermediate carrier strip. Page 18 200411788 VI. The scope of patent application covers the steps to make the backside of the first wafer in these first packages fixed on the adhesive film. 4. As the patent application range as much as in item 2 of the package structure of the wafer manufacturing method, wherein the intermediate divided carrier strip to form a plurality of multi-chip package unit further comprises a film removal step. Fan Li specifically requested application as 5 in the cuts are made in the package as its enclosure article carrier plate manufactured by the manufacturing method of square crystals were mounted into a plurality of items cut Step End step c - ^^ 1 cut by the punching step by the system Marching with the number of holes and grooves, there is a template of the second section of the J " \ special room, please apply for it. eThe item of the construction of the cover sheet crystal that is made by the method of the method is contained in the board. The Fanjianli technical secondary school should request the application. Cheng finished -s' Cut and cut 1 Steps cut by multiple pieces made by the method made by the French method Cut the step to cut the number of lines with the line Γ — the second round template Li Zai special room, please apply for Zhongzhong. 〇〇The first step of the first yuan Zhongdian Yuandian 1-1 single-conductor enclosure Fanfanli film one special crystal less, please apply as much as possible to the shape of the 9. 9. other structures made by law The multi-item item of the sealing chip is installed in the second body and the second body of the electrical guide is installed. Page 19 200411788 6. In the scope of the patent application, the independent intermediate carrier board unit further forms at least one first and third conductive elements on its lower surface. The first conductive element is connected between the independent intermediate carrier board unit and the first package. The three conductive elements are connected to the independent intermediate carrier board unit and the second package. 10 · The method for manufacturing a multi-chip package structure according to item 8 of the scope of patent application, wherein the first conductive element is electrically connected to the third conductive element through the independent intermediate carrier board unit. 11. The method for manufacturing a multi-chip package structure according to item 8 of the application, wherein the first conductive element is a solder ball. 1 2. The manufacturing method of the multi-chip package structure according to item 8 of the patent application scope, wherein the second conductive elements are solder balls. 1 3. The method for manufacturing a multi-chip package structure according to item 8 of the scope of patent application, wherein the third conductive element is a solder ball. 1 4. Patent application range as much as in item 1 package structure of the wafer manufacturing method, wherein the intermediate carrier strip by a plurality of lines and a plurality of insulating layers are alternately laminated layer of a conductive wiring layer formed with each other. 1 5. The method for manufacturing a multi-chip package structure according to item 1 of the scope of patent application, wherein the first package system includes at least a first chip and a first carrier board. Page 20 200411788 6. Scope of Patent Application 16 · As in the manufacturing method of the multi-chip package structure with the scope of patent application item 15, the first chip is electrically connected to the first carrier board in a flip-chip manner. 17 · The method for manufacturing a multi-chip package structure according to item 15 of the patent application, wherein the first chip is electrically connected to the first carrier board by wire bonding. 1 8. The patent application range as much as in item 1 of the package structure of the wafer manufacturing method, wherein the second chip package system comprises at least a second carrier and a second plate, the second chip is received in the opening. 1 9. The range of the patent application many as 18 wafer manufacturing method of the package structure, wherein the second chip is flip chip electrically connected to the second carrier plate. 2 0. The range of the patent application many as 18 wafer manufacturing method of the package structure, in a manner wherein the second chip is electrically connected to the second wire carrier plate. 2 1. The method for manufacturing a multi-chip package structure according to item 1 of the scope of patent application, wherein the intermediate carrier strip has at least one anchor point. 2 2. The manufacturing method of the multi-chip package structure according to item 1 of the scope of the patent application, wherein the positioning point is disposed at the edge of the opening. 2 3. —A method for manufacturing a multi-chip package structure, including: Page 21 200411788 6. The scope of the patent application provides a plurality of first packages and a plurality of second packages; an intermediate carrier strip is provided, and the intermediate carrier strip has a plurality of intermediate carrier units, and each of these intermediate carrier units is The first package body is provided with an opening, a first surface and a second surface; the first packages are disposed on the first surface of the intermediate carrier unit to cover the corresponding openings, the first package system and the The middle carrier board unit is electrically connected; a film is provided; the connected first package bodies and the middle carrier board strip are arranged on the film through the back surface of the first package body; Forming a plurality of independent intermediate carrier board units, the independent intermediate carrier board units and the first packaging systems electrically connected to them are respectively fixed on the adhesive film; the second packages are respectively provided corresponding to the openings. So that they are connected to the second surface of the independent intermediate carrier board units, and the second packaging systems are electrically connected to corresponding remote independent intermediate carrier board units respectively; and removing the adhesive film to form a plurality of Chip packaging unit, each multi-chip packaging unit includes a first package body, a second package body, and an independent intermediate carrier board XJX3 ^ Early Wu ° 2 4 · Manufacturing of a multi-chip package structure as described in the patent application No. 23 The method, wherein dividing the intermediate carrier strip is completed by a punching step. 2 5 · The method for manufacturing a multi-wafer sealing structure according to item 24 of the patent application, wherein the intermediate carrier strip further has a plurality of slots for the punching. 200 411 788 VI patent scope step. 2 6 · The manufacturing method of a multi-chip package structure according to item 23 of the patent application scope, wherein dividing the intermediate carrier board is performed by a cutting step. 27. Patent application range as much as 26 of the wafer manufacturing method of the package structure, wherein the mid-carrier strip having a plurality of cutting lines more for performing the cutting step. 28. The method for manufacturing a multi-chip package structure according to item 23 of the patent application, wherein the first package and the second package in the multi-chip package unit further form at least a first conductive element and a second conductive element, respectively. On its lower surface, the independent intermediate carrier board unit further forms at least one first three conductive elements on its lower surface. The first conductive element is connected to the intermediate carrier board unit and the first package, and the third conductive element is connected to the independent intermediate board. The carrier board unit and the second package. 9. The patent application 2 range item 28 as many wafer manufacturing method of the package structure, wherein the first conductive element intermediate carrier system by independent means and the third conductive member is electrically connected. 3 0. The range of the patent application many as 23 wafer manufacturing method of the package structure, wherein the carrier strip has at least one intermediate anchor point. Page 23 200411788 Page 24