TW200409253A - Manufacturing method of micro bump pitch IC substrate - Google Patents

Abstract

The present invention is related to a manufacturing method of micro bump pitch IC substrate. The main spirit of the invention is to use a dielectric layer to replace the conventional solder resist, in which the void-filling plated-metal process together with the etching method are used to solve the problem of the conventional semiconductor substrate which cannot meet the packaging demanding of increasingly fined pitch between IC bump pads. The invented method is capable of providing higher chip package density, In addition, for the structure request of the next generation super-high density IC chip design and package, a completely solving means on the manufacture of carrying substrate is provided.

Description

200409253 V. Description of the invention (1) ~ [Technical field to which the invention belongs] The present invention relates to a method of manufacturing a semiconductor carrier board, in particular, a carrier board for ultra-macro IC bonding, in order to respond to the next generation of I [Demand for increasing design and packaging density. [Previous technology] Due to the trend of thin, thin and short electronic products, coupled with the increasing number of functions, the I / O number of ICs has increased rapidly, and the relative packaging technology has been continuously updated. At present, most of the high-end products have used flip-chip packaging. fii P ch 1 p] technology, the packaging density is also increasing. The bump pitch of the wafer bonding chip (rapid pitch) has also been rapidly reduced from 300um to 200um. Due to the improvement of the alignment accuracy in the manufacturing process of the carrier board at present, the packaging requirement of 20um can be satisfied. However, the pitch required for the next-generation product's packaging technology has dropped to an ultra-fine pitch of less than 150 一般, and the general carrier board = the technology process and structure used are not enough to support this 1 (: packaging requirements, white ^ development The new carrier board structure and manufacturing method to provide a solution are conventional IC carrier board structures that are generally boards. The materials used are ceramics or organic conductors. Mechanical drilling or laser drilling are used to micro-connect the bumps ( bump) combined with two to eight layers of multilayer printed circuit material, and its multilayer structure of the circuit holes, and then pull the wire to make jc Cbump pad), and then prevent 200409253 V. Description of the invention (2) Welding A solder resist is used to set the solder pad area, and then the solder is applied by stencil printing. There are two conventional methods for setting solder pads. One is solder resist defined. lands), as shown in Figure 1 No, the other is a metal defined lands with a metal surface, as shown in Figure 2. When the distance between the wafer bonding pads is reduced to 150 ·, the wiring between the pads will cause the limited pad area to be too small. Due to the limitations of printing technology and the large grain size of the solder 102, the solder used cannot be filled into the pad 10, and the bonding strength with the wafer is insufficient due to insufficient solder volume (solder vlume), such as This is shown in Figure 1. Alternatively, because the width of the area covered by the solder resist 201 is too small (for example, '< 75nm), the adhesion of the solder resist is insufficient and the 202 is peeled off, as shown in Figure 2. Therefore, it is conventionally used. [Manufacturing method, ultra-macro κ carrier board cannot be produced.] [Summary of the Invention] Based on the lack of the above-mentioned conventional technology, the present invention provides an IC carrier board structure with a super-macro pitch for bonding pads and a manufacturing method thereof It mainly consists of replacing a conventional i-solder resist with a dielectric layer, and then using a CCD precision positioning laser drill to open the limited pad area, and then filling the hole. Metal plating process with corrosion Method, the bonding pad is enlarged and tin / lead is plated. In this way, the problems of "insufficient bonding pad strength" and the limitation of printing technology that cannot be applied to solder can be solved at the same time. At the same time, this method can also bond the pad (Bump pad), passive ^ pad (such as capacitor-Capacitor Pad), package alignment mark stem (

Fiducial Mark) position is raised 5 # The pad is buried in anti-capping agent. This structure strengthens the cover of the watch. It replaces the conventional method and is easy to use the UnderfiU process. It can be glued after the private IC is combined. Problems with Super Macro 1C Packaging. : Difficulty of two-J flow glue. Wafer packaging density ’yield rate. • This method can provide higher structural requirements such as packaging and long-term, 4th generation ultra-high density 1C chip design. "Construct the structure" to provide a complete solution in the production of the carrier board [Embodiment] Detailed description of the embodiment of the manufacturing method, focusing on the following 3 macro 1c carrier board clothing Figure 3 is shown as an example Niu Zhi / Su: Carrier board 30 丨, the carrier board 301 can be used, ^ carrier board steps, Figure 3 (A) is a (BT) or other organic materials, ma eimide Triazine 3〇1 surface is pre-formed a Made of pottery. On the carrier board copper cymbals. The third metal layer 302 'in FIG. 3 may be a plate through hole 303. FIG. 3 is formed in advance on the carrier board 301—formed in a plurality of carrier holes 303—the first metal layer 302 and the carrier board may be copper (CU). Money metal layer 300, the first chain metal layer 300 Figure 3 (D)-(E) Household weight + a Step of forming an inner layer with dry film (Dry Filn〇, Figure 3 (D) 3〇 The image of 4 and the first metal layer is used as a mask. After 30 minutes of the first mineral metal layer, the remaining part will form the inner layer circuit.

200409253

5. Description of the invention (4) 3 0 6 as shown in figure 3 (E). Figure III (F ::: is a black gasification inner layer step, which is oxidized, the inner layer depends on the method, ^ ^^ Λ Inner layer layer 3 0 7. ^ ^ Black emulsification Figure III (G)-(Η) Shown are the formation steps. Figure III (G) is a dielectric; the intervening electrical β layer and: the second metal layer are formed by a high temperature compression method of a dielectric layer 3008 and a metal, 309. This dielectric path 3 0 8 can be made of Triazing (BT) or other dielectric substances. The metal a 309 can be made of steel (Cu). Thinning and forming a second metal layer 30 9a. Shu Zeng 3U9 to Figure 3 (I)-(L) shows the step of forming the through hole of the dielectric layer. The image of Dry Film 3 10 is a laser mask (La ser

Figure (I)

Conformal Mask) 311, as shown in Figure 3 (J). As shown in FIG. 3 (κ), a plurality of dielectric layer vias 312 are formed on the dielectric layer 308, and a thin conductive conductive metal is formed in the dielectric layer vias 312 with a chemical mineral metal (which may be Cu). Two gold-plated metal layers 3 1 3 are shown in FIG. 3 (L).

Figure 3 (M)-(0) shows a step of forming a circuit layer. Figure 3 (M) uses the image of Photo Resist 31 5 as a mask, and the exposed part of the mask (see Figure 3) (Shown in (M)) The hole-plated ore copper (P 1 ating F i 1 1 ed Copper) 314 is filled in the dielectric layer circuit metal plating layer 3 丨 3 and the micro vias 3 1 2. As shown in FIG. 3 (N), a nickel / gold layer (Ni / Au) or tin 3 1 6 is plated on 3 1 4. The dry film mask is peeled off, and the second metal layer 3 009 a is etched by using nickel-plated gold or tin-lead layer 3 1 6 as an etching resist, and the remaining part forms the circuit layer 3 1 7 including Connection pads 3 1 8 a, 3 1 8 b, 3 1 8 c,

Page 8 200409253 As shown in figure three (0). Figure 3 (p) shows a coating-dielectric layer step, coating on the solder pad side [Bump Pad Side] -dielectric layer 3! 9 to replace the conventional solder resist 320, which is a conventional technology. On the solder ball side [BaU pad Side], a conventional solder resist 3 2 0 is applied.

Figures 3 (Q)-(R) show the steps of drilling a micro hole in a CCD alignment laser. The CCD alignment laser is used to drill holes in the dielectric layer 319 to open the bonding pads, passive component bonding pads, and packaging. The alignment target and the like are conducted to the micro vias on the surface (Micro Via) 32, and the conventional solder exposure method is used to form a solder resist solder ball pad 322 on the solder resist 320, and then electroless metal plating is applied to A thin metal conductive layer is formed, as shown in FIG. 3 (Q). Figure 3 (R) shows a process for filling a hole with metal. The solder ball pad (bal 丨 is not protected with metal plating), and the exposed pad side is applied with a plating resist 32 3. Fill the hole with a metal conductive layer 3 2 4 to fill the tiny holes of the pad.

^ Figures 3 (S)-(T) show a step of enlarging the pad area. First remove the plating resist 3 23 protected by the solder ball pad, expose the solder ball pad, and first apply a photosensitive plating resist ( Photo Piat ing Resist) 325 on the Bump Pad Side 'The image is used as a cover screen, the exposed part of the cover screen (such as passive components, a seal and a 1-position mark), and the exposed solder ball pad An electroplated nickel-gold (or tin / wrong) metal layer 3 2 6 is further applied, as shown in FIG. 3 (S). In Fig. 3 (τ), 'the photoresist resist 3 2 5 is stripped first, and then the photoresist is used as a photoresist: (Phot = Etching Resist) 32 7, and the image is used as a mask. Part is to enlarge the pad size (Bump Pad Size) on the pad surface metal conductive layer 324. In Figure 3 (U), nickel / gold (or tin / lead) bonding

Page 9 200309253 V. Description of the invention (6) Etching resist mask as an etching resist, using the etching process to form a plated nickel / gold (or tin tin) on the passive component solder pad 328, encapsulating the alignment target 329 and enlarging The solder pads 330 are formed on the surface of the dielectric layer 31 9 and the surface of the solder ball pad 331. In Figure 2 (V), the steel plate printing method can be used to transfer the Eutectic Solder Paste or even the Lead Free Solder to the pads in the future. at ten) 332 to improve the yield of 1C packages. Disadvantages of the prior art similar to the present invention are: the prior art uses a solder resist to set a pad limit area, and finally applies solder 'by means of a steel plate printing method for packaging. There are two ways to set a limit pad for a conventional solder resist. One is a sol resist defined lands, as shown in Figure 1, and the other is a metal surface. Limiting pads (metal defined lands), as shown in Figure 2. When the distance between the wafer and the bonding pads is reduced to 150 μm, the wiring between the bonding pads will cause the limited pad area to be too small. Due to printing technology limitations and the solder's own grain size, the solder used cannot be filled into the solder. Alas, the bonding strength with the I-A-Y tablets is not enough, as shown in Figure 1. Or, because the width of the area covered by the solder resist is too small (for example, <75um), the solder resist is peeled off due to insufficient drilling force, as shown in Figure 2. Therefore, the conventional manufacturing method cannot make an ultra-macro IC carrier board. By comparing one embodiment of the present invention with the prior art, the present invention has the following advantages:

Page 10, 200409253 V. Explanation of the invention (7) 1 · The solder resist is replaced by a dielectric layer, because the coefficient of expansion (Coefficient Thermal Expansion) is the same as that of the carrier substrate, so it can solve the problem due to the different coefficient of expansion The resulting carrier board is bent or twisted. At the same time, in the thermal stress test, the failure of the test can be solved due to the high homogeneity of the material, and the physical properties such as water absorption and glass transition point are good, which improves the reliability of the package. Solve the problem of insufficient bonding strength due to soldering due to too small filling filled via metal process. 3. On the surface of the dielectric layer, the metal appears larger and soiled on the dielectric layer by etching. At the same time, the passive component bonding pad and the secondary target can be raised to the surface of the dielectric layer. The point created by the conventional method can be solved. Second = embedded in the solder resist and the solder particle size is too large to print the material. 4 .The final surface of the enlarged pad and more flexible metal treatment of square nickel / gold, tin-lead plating, or organic flux film treatment, etc.) such as charter side = 嫂 t Ic Gold stub / tin bump directly Combined, 1 2 dozen gold wire packaging, etc., if solder solder is even applied and even soldered and flattened, it can even be coated with lead-free ^ tin-lead for the flip chip (F 1 ip Chip). ; 'More mentionable ^ This technology also has the effect of improving the wiring density of general flip chip substrates. § When the flip chip substrate is an IC design of 2 5 Oum P it ch, the feathers are dry.' ) At least 150um diameter, Li Baiheng should keep it, and the extra space of 70u can be reused for wiring 'bit wiring density, and further reduce the 6 ~ 8 layer board structure to as little as 46 layers 冋 =

Page 11 200409253 V. Description of the invention (8) Significant savings in manufacturing costs. Therefore, a manufacturing method of a macro-semiconductor carrier board of the present invention can indeed achieve the desired purpose and effect by the disclosed technology, and meets the requirements of novelty, advancement, and industrial applicability of the invention patent. However, the illustrations and descriptions disclosed above are only preferred embodiments of the present invention, and are not intended to limit the implementation of the present invention. Any person familiar with the technology will make changes based on the spirit of the present invention. Or modifications should be covered by the scope of patent application in the following case.

Page 12 200409253 Brief description of the diagram. Figure 1 shows the implementation of the conventional solder resist application-Solder Resist Define welding pad. Figure 2 shows the conventional application of solder resist. -Another implementation schematic diagram of Metal Define pad (Figure 3 (A)-(V) is a detailed illustration of an embodiment of a method for manufacturing an ultra-macro IC carrier board according to the present invention [Illustration of drawing number] ] 101 102 201 202 302 303 304 305 306 307 308 309 3 0 9a reference pad solder solder resist solder resist [peeling] carrier board 3 0 1 first metal layer carrier board through hole first forged metal layer dry Film (Dry Film inner layer circuit black oxide inner layer circuit layer dielectric layer metal foil second metal layer

Page 13 200309253 Schematic description Dry Film 310 Laser Conformal Mask 311 Dielectric layer through hole 312 Second forged metal layer 313 Plating Filled Copper 314 Photoresist ( Photo Resist) 315 Nickel gold layer (Ni / Au) 316 Circuit layer 317 Connection pad 318a, 318b, 318c Dielectric layer 319 Solder resist 320 Drilling small holes 321 Solder resist opening 322 Plating resist 323 Filling hole plating 324 Photo Plating Resist: 325 Electroplated nickel / gold or tin / lead metal layer 326 Photoresist etch resist 327 Passive component pad 328 Package alignment target 329 Mask pad (formed to enlarge) 330 Nickel plating Gold or tin / lead solder ball pads 331 Solder + Solder (Flatten) 332

Page 14

Claims (1)

200409253 VI. Scope of patent application 1 · A method for manufacturing an ultra-macro IC carrier board with an IC connection pitch of less than 180 μm, including: A step of providing a carrier board is to form a first metal on the surface of the carrier board in advance Layer, and a plurality of through-holes of the substrate are formed in advance on the substrate, and a first metal-plated layer is formed in the first metal layer and the through-holes of the substrate; a step of forming an inner layer circuit uses a cover screen The first metal plating layer and the first metal layer are etched, and the remaining portion forms the inner layer circuit. A black oxide inner layer step is a method of oxidizing the inner layer circuit to form a black oxide inner layer circuit on the surface of the inner layer circuit. A step of forming a dielectric layer and a second metal layer, covering the inner layer circuit with a dielectric substance, and then forming a metal foil on the surface of the dielectric layer, thinning the metal foil to form a second metal layer; A step of forming a dielectric layer via is to form a plurality of dielectric layer vias on the dielectric layer and form a second metal plating layer in the dielectric layer via;-a circuit layer step, system The second metal layer is etched with a nickel nickel gold layer or a tin-lead-lead layer as a money etch resist, and the remaining part forms the circuit layer; the step of coating to the dielectric layer, on the pad surface [Bump Pad Side] 'Coat a dielectric layer to replace the conventional solder resist used in the conventional technology, and apply the conventional solder resist on the 4-ball pad surface [B a 1 1 P ad Side]; The step of drilling a micro hole by a laser is to drill a micro hole in a dielectric shell with a CCD alignment laser to open a solder pad, a passive component bonding pad and a package. Page 15: 200409253 Patent application scope: Targets, targets, etc., are connected to tiny holes on the surface, and a conventional solder mask method is used to form a solder resist solder ball pad on the solder resist. (Ba i 1 P ad) The chemical copper is used as a thin conductive metal layer, and the solder ball pad is protected by an electric resist to avoid being covered by metal plating. Metal plating is applied, and the exposed pad side (Bump Pad Side) is filled with Hole plating, filling the tiny holes of the welding grate; Steps of enlarging the pad area, removing the resist protected on the solder ball pad, exposing the solder ball 塾, first applying a photosensitive plating resist (Phot pupting Resist) to the Bump Pad Side, to The image is a mask. The exposed part of the mask (such as passive component bonding pads, packaging alignment targets) and the exposed solder ball pads are then plated with a nickel-gold (or tin edge) metal layer to strip the plating resist. Then, a photo-etching resist is applied, and the image is a mask, and the part covered by the mask is a bump pad size on the pad conductive metal layer. Then, nickel / gold (or tin / wrong) combined with an etching resist mask is used as an etching resist, and an electroplating nickel / gold (or tin-lead) is formed on the passive component pads, packaging alignment targets, and enlarged welding by an etching process. Pad and solder ball pad surface. 2. According to the manufacturing method of the carrier board described in item 丨 of the scope of the patent application, Douzhong replaces the solder resist with a dielectric layer on the Bump Pad Side, and at the same time as another layer to manufacture more Large solder pads, the structure and manufacturing method of lifting solder pads, passive component bonding pads, and packaging alignment targets to bonding φ, replacing solder pads embedded in solder resist. 3. According to the manufacturing method of the carrier plate described in item 丨 of the scope of the patent application, the basin CCD is used to drill the micro holes with high precision, and then fill the holes with 2 micron metal plating. 200409253 VI. Scope of patent application Manufacturing method of small holes to achieve enhanced bonding strength. 4. The method for manufacturing a carrier board as described in item 1 of the scope of the patent application, wherein an anti-etching mask and a method of electroplating nickel-gold (or tin / lead etching resist) are used to produce a solder pad enlarged on the surface of the build-up metal. Due to the increase in area and the application of printed solder, flattening or electroplating of nickel / gold, tin / fault, or applying an organic flux layer, or even a manufacturing method combining gold bumps. 5. If the scope of patent application is the first In the manufacturing method of the carrier board, when this technology is applied to a general flip chip carrier board, the pads can be reduced, the wiring space and density can be increased, and the number of structural layers and the cost can be reduced. Page 17