SU907840A1 - Device for measuring error coefficient - Google Patents

Description

(5) DEVICE FOR MEASURING THE ERROR COEFFICIENT

I

The invention relates to telecommunications and can be used to determine the error rate of discrete communication channels.

A device for measuring the error rate is known, comprising a serially connected error analyzer and an error counter, a number counter, first and second number indicators and a serially connected degree counter and a degree indicator 1.

However, the measurement accuracy of the known device is low.

The purpose of the invention is to improve the measurement accuracy.

To achieve this goal, a first trigger, a cycle counter, a serially connected reading unit, a countdown counter, a second trigger, a key, a divider and a comparison unit, the first and second buffer registers, the delay element sequentially connected first element are introduced into a known device for measuring the error rate. And, the third trigger, the second element AND and the first element OR and the third element AND connected in series and the second element OR, the output of the error analyzer through the first trigger connected to the second in Odom second flip-flop, a third input connected with the control inputs

10 counters of the number, first and second buffer registers and a read block, with the first input of the first element I, with the input of the delay element and with the input of the cycle counter, to which the frame synchronization signal is applied, the first and second outputs of the error counter are connected respectively to the signal input of the block reading and with the second input of the first element OR, the output of which is connected to the first input of a degree counter, the second input of which is connected to the output of the second element OR, the second

the input of which is connected to the first output of the cycle counter, the second output of which is connected to the second input of the comparison unit, the output of which is connected to the second divider input and to the signal input of the number estimator, the installation input of which is connected to the third divider input and to the output of the delay element, the first and The second outputs of the number estimator are connected to the second - inputs respectively of the first and second elements And, the first and second inputs and the second output of the third trigger are connected respectively with the first input of the third element And ,. with the second input of the second element And and with the second input of the third element And, the corresponding signal outputs of the number counter, respectively, through the first and second buffer registers are connected to the inputs of the first and second number indicators, respectively, the key output, to the second input of which clock pulses are applied, connected to the clock the countdown input of the counting counter, and the combined input of the first trigger, the third input of the third trigger, and the control input of the degree counter give a reset signal

The drawing shows the structure electrical circuit of the proposed device.

The device for measuring the error rate contains an error analyzer 1, a Z error counter, a read block 3, a key, a count counter 5, a count counter 6, a cycle count 7, a compare block 8, a divider 9 first and second buffer registers 10 and 11, the first and second second indicators 12 and 13 numbers, counter 1A degrees, indicator 15 degrees, first 16 and second 17 elements OR, first 18, second 19 and third 20 elements AND, first 21, second 22 and third 23 triggers and element 2 delays.

The device works as follows.

Let the duration of the reset cycle be N 100 clock cycles, the number display is two-bit (A, B),

When sbruse, timed to cycle 1C, counter 1 is set to - (1 + IgN), i.e. by 10, the first trigger 21 is set to a state where, at the input of the second trigger setup

Li will be low, and the signal from its output will close the key,

Let during the cycle analyzer 1 received two errors. Simultaneously with the arrival of the first error, the first trigger 21 is thrown, which unlocks the second trigger 22, which in turn blocks the key in the absence of errors.

After N clock cycles, after the reset, the signal of the first cycle 1C is received, with which the recorded information is transferred to the buffer 6 from the sweeper 6 to the buffer registers 10 and 11. The third trigger 23 does not change its state. The same cycle signal W, which enters block 3, transfers the accumulated number of errors from counter 2 to counter 5, and also sends the second trigger 22, opening key 4, through which the clock frequency T1-1 from the device input goes to counter 5. subtracting it has the number of errors in it. The 1C cycle signal through the delay element 24 resets the decimal counter of counter 6 and divider 9. Thus, when errors are multiplied by ten, this is compensated by the fact that the degree of reset is set to 1 more than Ig N.

Claims (1)

1. USSR author's certificate N, cl. H About L11 / 08, ig (prototype).