SU855963A2 - Clock pulse generator - Google Patents

Description

(54) GENERATOR OF CLOCK IDS G1ULTS

The invention relates to computing and discrete automation and can be used to generate a series of pulses in the asynchronous reception of information represented by a potential two-position code, as well as to synchronize the operation of digital devices. According to the main author. St. No. 307502 is a known clock generator (GTI) consisting of a paraphase quartz driver connected to a clock device and a clock generator, the first input of which is connected to the output of the clock device. The synchronizing device contains a switching device (trigger) and half-adder, made on the same elements AND-NOT (OR-NOT), as well as an additional gate that eliminates the reduction of the duration of the first clock pulse 1. The disadvantage of this clock generator is the possible reduction of the duration of the last clock pulse impulse, therefore, it is possible to change the number of pulses in the series being formed. The purpose of the invention is to eliminate the distortion of the shape of the last clock pulse generated when the input signal is removed. The goal is achieved by the fact that a clock generator, consisting of a paraphase quartz generator of a synchronization device containing a switching device and a half-accumulator, a clock pulse generator connected to the inputs of the switching device, the logical element of AND-HE (OR-HE) whose outputs are connected in pairs with the outputs of the first logic elements of the switch and the outputs of the switching device and with an additional input of the output logic element of the half-adder, additionally enter Logs are OR or NOT, while the input of the logic element is NOT connected to the output of the output logic element of the half adder, and the output is connected to one of the inputs of the logical element OR, the other input of which is connected to the input bus, and the output to the second additional input of the output logic element half-adder, with single and zero inputs of the switching device and with the second input of the clock pulse generator.

The drawing shows a diagram of the GTI.

GTI contains a paraphase quartz driver 1, a valve 2, a switching device, presented in the form of a trigger with a separate start, made on the elements AND-NOT (OR-NO) 3 and 4, half-adder on the logical elements AND-NOT (OR-NOT) 5- 7 and logical elements OR - 8 and NOT 9, shaper 10 clocks. The input signal is fed to the bus 11. The single and zero outputs of the trigger of the switching device are pairwise connected to the corresponding inputs of the first two logic elements 5 and 6 of a half-adder, the outputs of which are connected to the same-named inputs of the trigger. Two other inputs of the first logic elements 5 and 6 of the half adder are connected to the outputs a and a of the quartz former I. The output of the half adder is connected to the first input of the former 10 clock pulses. The inputs of the valve 2 are connected in pairs with the outputs of the first logic elements 5 and 6 of the half adder and the outputs of the switching device 3 and 4, and the output with the reset inputs of the switching device and with the first additional input of the output element 7 of the half adder.

The input of the logical element NOT 9 is connected to the output of the output logic element 7 of the half adder, and the output is connected to one of the inputs of the logical element OR 8, the other input of which is connected to the length 11, and the output to the second additional input of the output logical element 7 of the half adder, with a single and zero inputs 3 and 4 of the switching device and the second input of the driver 10 clock pulses.

The diagram of the GTI shows that the signal from the output of the synchronizing device is fed to the input of the HE 9 logical element, is inverted and fed to the input of the logical element OR 8. Thus, despite the signal removal from the bus 11, the output of the logical element OR 8 is kept high until.

until the signal from one of the outputs of the first half-adder elements changes the level to zero.

In this case, a high level appears at the output of the synchronization device, i.e. the output pulse is formed completely, and at the output of logic element 9 there will be a low level as a result of the logical addition of two logical zeros at the inputs of the logical element OR

8, at its output there will be a logical zero, which, arriving at one of the inputs of the output logic element 7 of a half adder, keeps the synchronizer at a high level until the next input signal arrives at the busbar 11.

In the proposed generator, the distortion of all clock pulses that are generated in response to the input signal during its duration is eliminated. Using it in binary conversion devices

the information provided by the potential code eliminates information corruption.

Claims (1)

Invention Formula Clock generator auth. St. No. 307502, characterized in that, in order to eliminate the distortion of the shape of the last clock pulse while removing the input. an additional signal, the OR or NOT logic elements are added to it, while the input of the logic element is NOT connected to the output of the output logic element of the half adder, and the output to one of the inputs of the logic element OR, the other input of which is connected to the input bus, and the output - to the second additional input of the output logic element of the half-adder, with the single and zero inputs of the switching device and with the second input of the clock generator. Sources of information taken into account in the examination 1. USSR author's certificate No. 307502, cl. H 03 K 3/57, 1970.