SU752466A1 - Information retrieval device - Google Patents

Description

(54) USTRS STVO FOR INFORMATION Sampling

Claims (2)

The invention relates to computational technology and can be used in devices for sampling and processing data pulses and synchronous 1 pulses when reading information from a loop of cyclic-action devices (memory devices), and 1 is a memory device on magnetic disks. In one of the known devices for sampling data pulses and cHH3qpc "pulses, the principle of operation is that, as a result of logical signals over the input pulse sequence, the data pulses are generated from the JXJ sync pulses. The closest technical solution to this is a device for selecting information that contains the circuit of the NAND element, two inverters, where the output of the first inverter is connected to the first input of the first NAND element, the output of the second NAND element is connected to the first input of the third AND element -NO, the input of the device is connected to the second input of the pnx element AND-NOT and to ne; f5BOm input of the fourth element NAND 2. A disadvantage of the known devices is a relatively large amount of equipment. In addition, for most applications of similar devices, it is necessary to select not sync pulses and data, but units of zero zeros (both in data and in sync pulses), as well as a clock frequency. The known devices do not provide for the separation of the indicated sequences, which limits their functional capabilities. The purpose of the invention is to simplify the device. This goal is achieved by the fact that the device contains an adjustable delay element, and its output is connected to the second input of the fourth AND-NOT element, the input of the first inverter and the first input of the second AND-NO element, the output of the second inverter is connected to the second input of the second AND-NO element , the outputs of the first and fourth 37th anewTQwroB AND-NOT are connected respectively to the second and third inputs of the third NAND, the input of the device is connected to the input of the controlled element. delay element and the input of the second inverter. In FIG. 1, a functional diagram of the device for sampling information is shown; FIG. 2 is a time diagram of the operation of the device. The device contains porvady and second inverters 1, 2, the first, second, third and fourth elements AND-NOT, an adjustable element 7 delay. In accordance with the method of recording information in memory on magnetic disks, in the pulse sequence read from the track of a magnetic disk, there is service information, which is characteristic code combinations. To decrypt overhead information in certain parts of the input sequence, it becomes necessary to count the number of zeros and ones both in the data and in the clock pulses. The device allows, by means of a small number of simple logical operations on the input sequence, to receive pulses at one of its outputs at times, corresponding to reading O, i.e., there is no data impulse on the track, and at the other - an imp; 1s at the time point corresponding to reading 1 both in sync pulses and in data. The presence of pulses at positions O simplifies the task of deciphering and other operations on the input data. mi In addition, the device generates a clock sequence at the output of the second AND-NOT element 5 (see, FIG. 2, which ensures synchronism of further processing of the read information. The device operates as follows. The input pulse sequence arriving at the device input {FIG. 2, a) , gets to one of the inputs of the first and fourth elements 3.6 AND-NOT and, being inverted by the second inverter 2 (Fig. 2, e), to one of the inputs of the second element 4 AND-NOT. In addition, being delayed on the control element 7 of the delay at half the frequency of the sync impulses (Fig. 2, b), the now delayed input sequence 6 is fed to the other inputs of the second and fourth elements 4,6 AND-NOT and in the inverse form from the output of the inverter 1 ((fig, 2, r) i) to another input of the first element 3 AND-NOT. Thus, at the output of the fourth element 6 AND-NOT, we have a pulse sequence corresponding to twice the number 1 of the input pulse sequence (FIG. 2), at the output of the first element 3 AND-HE is a sequence corresponding to the synchro pulses, if before There was no data pulse (Fig. 2, d) at the output of the second element 4 AND-NOT — the sequence corresponding to O (Fig. 2, g). By applying pulse sequences from the outputs of the first, second and fourth elements 3, 4, 6 AND-NOT to the corresponding inputs of the third element 5 AND-NOT, at the output of this element, we obtain a clock sequence that has the same form when entering any kind of service information on input device (Fig. 2, a). The use of this device makes it possible to reduce the amount of equipment in the memory control device, simplify further processing of the read information and increase the reliability of the external memory. The invention The device for sampling information, containing the elements AND-NOT, inverters, the outputs of one of which are connected to the first inputs of the first and elements AND-NOT, the second and first inputs of the third and fourth elements, respectively, AND-NOT connected to the input of the device, the output of the second element NAND is connected to the first input of the third element, characterized in that, in order to simplify the device and increase its reliability, it contains a controllable delay element, the output of which is connected to the second input of the fourth NAND element, ode first inverter and the first input of the second element AND-NOT, the second input of which is connected to the output of the second, the outputs of the first and fourth elements of the INE are connected respectively to the second and third inputs of the third element AND-NOT, the inputs of the adjustable delay element and the second inverter are connected to the input of the device . Sources of information taken into account during the examination 1. The device EC-5S51, THAT, took it easy 6.4. Sync Pulse Node bm | fM doHMMe) 7524 ttummoboe pass eMachanMYGD 6 ow and control the bit ring and delta bit ring. NECK O57. 069.Г01. 2. USSR author's certificate No. 514338, cl. G 11 C 7 / OO. 1976 (prototype).