SU435521A1 - - Google Patents

Description

one

The invention relates to the field of discrete computing and is intended for use in systems and devices for processing discrete information and control.

Arithmetic sequential devices are known that contain multiplier and multiplicative registers, adder, coincidence circuits, and collective circuits.

However, the functionality of these devices is limited.

In order to eliminate this drawback, the proposed device additionally contains a pulse-number divider (CI).

The drawing shows the functional-logic diagram of the device.

The device contains a pulse generator 1 connected to the first input of circuit 2 (), the second and third inputs of which are connected to the outputs of circuits 3,4 (,), respectively, and the output of circuit 2 is connected to the first input of circuit 5 (), the output of which is connected to the counting the input of the first bit of the subtracting counter 6. The second input of the circuit 5 is connected to the second inputs of the circuit 7 () 4 and to the output of the circuit 8 (), to the inputs of which are connected the single outputs of the discharge triggers of the counter 6 and the unit inputs of the corresponding discharge triggers of the number imT1 pulse : in (DCI) 9. At the entrance of DC And 9 is connected to the output of the circuit 10 (). The circuit 10 is connected via the first input to the output of the generator 1, and the second to the output of the circuit 11 (), the first and second inputs of which are connected to the control buses used for setting the division and multiplication modes, respectively. The third input of circuit 10 is connected to the first inputs of circuits 4 and 7. The output of the latter is connected to the circuit 12 ("NOT) and to the first input of the circuit 13 (), the second input of which is connected to the bus to establish the mode of addition and to the first input of the circuit 3, the second input of which is connected to the bus for setting the subtraction mode. The output of the circuit 13 is connected to the counting input of the second bit of the counter of pulses 14, the output of the circuit 15 () is connected to the counting input of the first bit, the first input of which is connected to the output of the circuit 16 (). To the first input of the circuit 16 is connected bus "Division and the first input of the circuit 17 (" And), the second input of which is connected to the output of DCIP 9 and with the second inputs of circuits 16 and 18 (). The second input of circuit 15 is connected to the output of circuit 19 (), the first input of which is connected to the output of circuit 10, and the second input is connected to the bus “Multiplication, as well as to the first input of circuit 18, the output of which is connected to the first input of circuit 20 (). The output of pulse counter 21 is connected to the second input of circuit 20; the output of circuit 17 is connected to its input. The third input of circuit 20 is connected to the output of circuit 22 (), the third input of circuit 13 and the first inputs of circuit 5 and 23 are connected to the first input. The output of the circuit 12 and the third input of the circuit 15 are connected to the second input of the circuit 23. The first inputs of the circuits 7 and 4 and the output of the circuit 24 () are connected to the second input of the circuit 22. The inputs of the latter are connected to the single outputs of the bits of the detracting counter 25. To the counting input of the first discharge of the counter, the OUTPUT of the circuit 20 is connected. The device operates as follows. Add mode. The terms A and S are entered into subtractive counters 6 and 25, respectively. The output of the subtracting counters is formed by the collective circuit 8, 24, to which the unit outputs of the counter bits are connected. The presence of at least a unit in the counter 6 or 25 provides a high potential at the output of circuits 8 and 24, respectively. These high potentials through the circuit 4 are fed to the third input of the circuit 2. The signal from the output of the circuit 8 controls the circuit 5, and the signal from the output of the circuit 24 - the circuit 22. The addition command supplied to the control bus "Addition through the circuit 3 provides high potential at the second input of circuit 2. If one of the terms or both are different from zero, then the pulses from generator 1 applied to the first input of circuit 2 simultaneously arrive at the first inputs of circuits 5, 22, 23 and to the third input of circuit 13. The pulses from circuits 22 through the circuit 20 is fed to the input of the counter 25, which works in the mode i have a reverse account. Similarly, the pulses from the output of circuit 5 are fed to the input of the subtractive counter 6. When set to "About counter 6, circuit 5 is closed, and when set to" About counter 25, circuit 22. While there are different numbers from "About (On output high potential circuit 7) pulses from the output of circuit 2 are fed through circuit 13 to the second trigger input of counter 14 (circuit 13 is also controlled from the Addition bus. Each pulse at the output of circuit 13 subtracts one from the contents of counters 6 and 25. As soon as one of the counters 6 or 25 is set to "Oh, The high potential from the output of circuit 7 and from the corresponding circuit 22 and 5 is removed, and therefore, circuit 13 closes and circuit 12 opens circuit 23, the pulses at the output of which have the same price and through circuit 15 arrive at the first-stage counter input of counter 14 In the instant of setting both counters to "O high potential, the third input of circuit 2 is removed and the pulses coming to the output of the arithmetic unit are stopped. This completes the add operation. The addition operation takes place according to the formula (B-A) B-i-A if, and according to the formula 2B + (A-B) A + B, if. R e and m vy ch and t and n and. The subtraction operation is performed in the same sequence as the addition operation. The difference is that during the operation of the device, the circuit 13 is closed, since there is no signal at its second input from the "addition" bus. The pulses from generator 1 do not pass through it to the counting input of the second discharge of counter 14. As soon as one of the counters 6 or 25 is set to "O, high potential from output 7, as well as from the corresponding circuit 5 or 22, is removed, and circuit 12 opens circuit 23, the pulses at the output of which have the same price and through circuit 15 arrive at the counting input of the first discharge of counter 14. When both counters are set to "O high potential, the third input of circuit 2 is removed and the flow of pulses to the input counter 14. Number, gender occurs in a result of subtraction is A-B, if A and B if. Multiply mode. The command "multiply applied to the bus" Multiply through circuit 11 provides a high potential at the second input of circuit 10 and at the first input of circuits 18 and 19. If at least one is recorded in the counter 25, then the high potential from the output of circuit 24 is fed to the third input circuits 10 and pulses from generator 1, fed to the first input of circuit 10, are fed to the input of DCI 9 and to the first input of circuit 19. In this case, the factor B is used as a divider for DRCI 9, where the number from counter 6 is prewritten. connected to the input of counter 25, used by o as a factor multiplier register through circuits 18 and 20. In general, the number of pulses arriving at the output of the device, .В, where K is the number of pulses at the output of DCHI 9. Each of the pulses of the DCHI circuit through circuits 18 and 20 goes to the register counter 25 factor L and consistently reduces its value by one. As long as a significant number still counts in counter 25, at output 24 there is a signal permitting the passage of pulses from generator 1 to the input of counter 14 through circuits 19 and 15. When the number in counter b (factor L) is akimized to “O , and this will happen at a time when the number of pulses from the output of DCHI 9 K will be equal to the number recorded in the counter 25 (L), i.e. when (the number of pulses passed to the input of counter 14), then it will equal i.e. the value of the product of numbers

 After the counter 25 is set to "O high potential" from the output of the circuit 24 and, consequently, from the input of the circuit 10, the input pulses of the device cease to flow.

Dividing mode.

The dividend A is entered into the counter 25, and the divider B is entered into the counter 6. A potential is applied to the bus "Fission. This signal is fed through the circuit 11 to the second input of the circuit 10 and to the first input of the circuit 16.

If the number A recorded in the counter 25 is not equal to "O", then through the circuit 24 a high potential is supplied to the third input of the circuit 10 and the pulses from the generator through the circuit 10 are fed to the input of the DCI circuit 9, and through the circuit 17 to the input of the counter 14.

As DCHI 9, a pulse division divider with a variable division factor is used.

The dividing ratio of DCHI 9 is set equal to the number recorded in counter 6, i.e., equal to divisor B. When a sequence of pulses is fed to the DCHI input (with dividing ratio B), every Bth pulse appears at the DCHI 9 output, and through the circuits 19, 15 passes to the counting input of the first bit of the counter 14.

Determine the number of pulses, which will be fed to the input of dchi.

The pulses applied to the DCCHI 9 input are simultaneously fed to the input of counter 21, i.e., the / r-bit counter (where n is selected depending on the required division accuracy).

The pulses from the output of the divider through the circuit 20 are fed to the input of the counter 25. Each pulse supplied to the input of the counter 25 corresponds to 2 pulses input to the DCI. At the moment when the counter 25 is set to "O, and this happens when exactly A pulses are applied to its input, high Potential from the input of circuit 10 is removed and the pulses to the input of DCI are stopped and, consequently, to the output of the device. By this time, the number of pulses applied to the DChI input is L-LX2, and the number of pulses at the DChI output (i.e., the L-2 output

de scheme) equals -. So that

In particular, obtained as a result of division in a similar way, the lower n bits correspond to the fractional part of the private and the rest to the whole part of the private.

As a result, the quotient is determined to the accuracy of 0.00 ... 0.1, i.e., to 2-.

Subject invention

A sequential arithmetic unit containing a pulse generator, pulse counters, logic "AND," OR, "NOT, characterized in that, in order to expand the functional

capabilities, it additionally contains a divisor of the number of consecutive pulses; the pulse generator is connected to the first input of the first “AND” circuit; to the second and third inputs of which are connected the outputs of the first and second circuits “OR, respectively, the output of the first“ AND circuit is connected to the first input of the second “And circuit, the output of which is connected to the counting input of the first bit the first subtractive counter; the second input of the second circuit “AND is connected to the second inputs of the third circuit“ AND and the second circuit “OR and to the output of the third circuit“ OR, to the inputs of which are connected the single outputs of the bit triggers of the first subtractive counter, which are also connected to the single inputs of the corresponding divider bits the number of consecutive pulses, the input of which is connected to the fourth output

schemes "And, the first input of which is connected to the output of the pulse generator; the second input of the fourth circuit "And connected to the output of the fourth circuit" ILR1, the first and second inputs of which are connected to the control

spines "Division and Multiplication, respectively; the third input of the fourth AND circuit is connected to the first input of the second OR circuit and with the first input of the third AND circuit, the output of the third AND circuit is connected to the NOT circuit

and to the first input and first circuit "AND, the second input of which is connected to the control bus" Addition and to the first input of the first circuit "OR, to the second input of which the control bus is connected" Subtraction; the output of the fifth circuit “AND is connected to the counting input of the second digit of the pulse counter; The output of the first OR circuit, the first input of which is connected, is connected to the counting input of the first discharge of the pulse counter.

with the output of the sixth circuit "And, the first input of the sixth circuit. We" and connected to the bus "Division and the first input of the seventh circuit" And, the second input of which is connected to the output of the divisor of the number of consecutive pulses and

the second inputs of the sixth OR circuit are connected to the output of the ninth AND circuit, the first input of which is connected to the output of the fourth AND circuit, and the second to the multiplication bus, as well as to the first input of the eighth circuit And, the output of which is connected to the first input of the sixth OR circuit, to the second input of which the output of the counter is connected; the output of the seventh is connected to the input of the counter

And, the third input of the sixth OR circuit is connected to the output of the 11th AND circuit, the first input of which is connected to the first inputs of the second and tenth AND circuit and the third input of the fifth circuit to the second input

of the tenth circuit “And connected to the output of the circuit“ NOT, and the output - to the third input of the fifth circuit; second input of the eleventh circuit “And connected to the first input of the third circuit“ And to the output of the seventh circuit

"OR, to the inputs of which are connected one