SU409277A1 - DEVICE FOR COMPRESSION AND CODING OF ANALOG MESSAGES IN SYSTEMS WITH CODE-PULSE MODULATION - Google Patents

Description

The invention relates to the field of telemarkets.

The known devices for: compressing and coding analog messages in systems with code-and-pulse modulation, containing serially connected sampler, analog-to-digital converter, increment analysis unit, outputs of which are connected to the inputs of the IM unit, as well as a generator and emulsions, one of the outputs of which are connected: and connected to the impulse input of the disirtizer, and the frequency divider.

Weighted devices, realizing the priori rejection of redundant choices to the original message based on the increment analysis, require a recalculated frequency of the signal, estimate the current spectrum width of the message using prediction, send data to the channel that should be supplied with a large number of service data (address ) information on the current estimate of the width of the spectrum and the corresponding time interval for this estimate. They do not allow data from a large number of sources to be combined due to the variable frequency of the survey, and sometimes they result in a large amount of overlap due to latency.

The purpose of the invention is to increase the efficiency of using channel data transmission capacity.

This is achieved by the fact that the other generator output of the IMNulses is connected to the divide input, t frequencies, and the divider outputs to the pulse inputs of the analog unit of increments. The increment analysis unit includes series-connected interpolators, each of which contains a gated cascade, one of the inputs of which is connected via a delay element to one of the inputs of the subtraction circuit, another input to the corresponding output of the frequency divider, output to one of the inputs of the adder and the input of the recovery filter. The filter output is connected to another input of the subtraction circuit, one of the outputs of this circuit is connected to the normal circuit, and the other is connected to the prohibition circuit. The address generator is also entered into the interpolator. One of its inputs is connected to the first output of the threshold circuit, to the inputs of the first key and the forward routing stage connected to the inhibit circuit, the other input to the output of the first key and to the input of the second key, and the output through the second key to the adder. The second output of the threshold circuit is connected to another input of the first key.

Wah FIG. 1 shows a block diagram of the proposed device; on fit. 2 - the interpolator circuit is functional; in fig. 3, a-d-oscillo | -rams, explaining the principle of operation of the device. The pre-selector / device to which the original message is sent, the sequence

connected to the analog-to-digital converter 2, the message increment analysis unit 3 and the memory unit 4. The output of the generator of 5 pulses is connected to the impulse input of the dioecreizer; the other output of this generator is connected to the divider 6 of the frequency. The outputs of the divider are connected to the corresponding pulse inputs of block 3, containing n interpolators / 1-7,1, which have (except for the last) two outputs (one of them is connected to the memory block and the other to the subsequent interpolator) .

The proposed device operates as follows.

The message m (t) supplied to its input is fed to a diode /, the pulse input of which is connected to the generator 5 of pulses. Analog message (It is subjected to amplitude-pulse modulation with и and kirovi-ayno and sampling frequency / o-) The latter is selected from the condition o 2-FMai c (where FMBKC is m: t xymaly, the spectrum of the m (t) message spectrum is possible. Diokretizer output signal T (1 passes to the input of the converter 2, the quantizing message mn (t), by level. The digital output of the converter is supplied to you by the input of block 3, consisting of l identical interpolators.

At the same time, pulses arrive at the pulse input of the first interpolator 7 of block 3

with the frequency of trace Ba1Ni / i fo 2

where k is an integer selected from the condition. (Fiiun is the minimum amount of m (t) message spectrum from the frequency divider 6, which can serve as a counter for triggers). Pulses with frequency i fall on the gated cascade 8 (scheme “I”) of the first interpolator 7, and pass the signal from converter 2. Next, the signal goes to a regenerating digital filter 9, the impulse response of which digitally reproduces the impulse response of the analog stepwise interceptor nln more complex recovery filters, consistent with the pulse frequency applied to the block divider.

For the case of step interpolation, a storage device (memory) with a memory time of 7iiM / M (for an interpolator 7i, for an interpolator 7z, etc.) can serve as a recovery filter. At the same time, the input signal of the interpolator is fed to the delay element 10 (for digital data this is a charger, the read frequency j OTOporo is determined by the delay time of the Gsm signal in the recovery filter). For an arbitrary filter.

Next, the signals from the filter and the delay element are received by a subtractor //, the output of which is the difference (increment) between the input signal and the reconstructed one. from the input menu (2 times for the i-th ipsterpollator) of its samples. In the event that the value of any sample of this difference exceeds the set threshold, then the difference signal is subjected to further analysis in a subsequent interpolator, if not, then the output of the threshold device .12 goes through the shaping cascade 13 signal to the prohibition circuit 14, which eliminates the need for subsequent analysis in the next interpolator of block 5. The same signal, which is superimposed. "The address of the interpolator 7i in the address generator 15 passes through the key 16 and cyMiMaTOip 17 to the memory block 4 to record in it information about the absence in the original message of high-frequency components that exceed the amplitude of the set threshold. In this case, the memory unit operating in the start-stop mode receives samples from the gated cascade of the interpolator 7 of block 3, which are continuously recorded in the memory block. Samples of increments from interpolators 7, 7h, etc., in the absence of high-frequency components that exceed the threshold, are not recorded. If there comes such a moment that the increment intensity exceeds the threshold, then the corresponding address signal of the interpolator 7, formed in the address generator, goes through the key 16 and the adder 17 to the unit. Its appearance twice allows to judge about the absence of high-frequency components in the time interval between two address signals and correctly decode the coded information. The second record may appear if the first record already exists. For this purpose, self-locking control keys are used, 16 and} 8.

In the initial state, the key 16 is closed, and the key. open If the signal from the output of the subtractor 11 does not exceed the threshold, then the corresponding signal from the first output of the threshold device 12 goes simultaneously to the shaping stage 13, the open key (and closes it) and the address generator 16, where the interpolator address is superimposed on it. Next, the signal from the output of the address generator is fed through a closed key .16 to the adder 17 and then to the block by 1 ti. The key 16, after the passage of the signal, goes into the open state — self-blocking. It closes the shadow only after the signal from the output of the switch 18 arrives at its second input. Thus, the address signal indicating the absence of high-frequency components in the original message cannot be recorded a second time.

If after the described situation the threshold is exceeded, then from the second output of the threshold device 12 a signal is sent to the already closed key / S and then to the address generator. The output signal of the key 1-8 closes the key 16 and unlocks the key IS - locks it, which makes it impossible to enter a second time

b

“Signal for r-raising the threshold“ and the generator. Address.

The output signal of the generator address-and through the. Closed key 16. Enters through the adder 17 in the block .pam tee. Similarly, an analysis of the increments in the following interpolators of block 3 is performed. With this 1M, if the signal of the increments at the output of any of these interpolators is less than the threshold, then an address signal is generated for writing to the memory block.

In the event that the width of the spectrum continues to decrease, the previous interpreter also forms its own addressable signal. When expanding .cneKTipa messages, first, the address signals of the interleaved interlolators are formed, and then (the subsequent ones, i.e. the address signals, the subsequent interpolators enclose the signals of the previous interpolators, which allows for the correct interpretation of the coded information.

The process of coding information from the outputs of gated interpolator cascades is as follows: message increments for each interpolator | Follow not in real time, but with a delay relative to the real time adder for a time Gs equal to the delay in the recovery filters in all previous interno tors of block 3. For example, the signal delay from the interpolator ./ from block 3 Determines the delay in interpolators 7i and Zg and is equal to Ц, Γ, Γ ,,.

The oscillograms, according to which the device operates, are shown in FIG. 3: a - initial position ni (t, sampled at frequency / o, and reconstructed message / HIS (O in interpolator 7 of block 5; b - increment of message m (t), past interpolator 7i, and its restoration mzs ( t) in Interpolator 7, c - message increment / P2 (), past interpolator / 2, and its recovery / Pzv (t) IB interpolator 7z; d - for coded information about message m {t), received in the memory block.

For convenience, the oscillogram-we are combined by

6

time and signals are presented in analog form, and the scale of the sho axis; time for the oscillogram, illustrating the input signal of the block. pam, this is compressed twice.

Linear interpolators are taken as recovery filters.

Prev Invention

Claims (2)

1. A device for compressing and encoding analog messages in systems with code-impulse modulation, containing a serially connected sampler, an analog-to-digital converter and an increment analysis unit, the outputs of which are connected to the input of the memory unit, a pulse generator, one of the OUTPUTS of which is connected to A pulse collector input, and a frequency divider, characterized in that, in order to increase the efficiency of using the data transmission channel capacity, the other output of the pulse generator is li ne to the input of the frequency divider, the outputs of which are connected to the inputs of the pulse analysis unit increments. 2. The device according to claim 1, characterized in that the increment analysis block includes sequentially connected interpolators, each of which contains a gated cascade, one of the inputs of which is connected via a delay element to one of the inputs of the subtraction circuit, the other input corresponding output of the frequency divider, and the output is connected to one of the inputs of the adder and to the input of the recovery filter, the output of which is connected to another input of the subtraction circuit, one of the outputs of which is connected to the threshold circuit, and preta, address generator, one of the inputs of which is connected to the first output of the threshold circuit, to the inputs of the first key and forming cascade connected to the first circuit, and the other input is connected to the output of the first key and to the input of the second key, and the output through the second switch with the adder, the second output of the threshold circuit is connected to another input of the first key. (PiiiZ.2 8 .emiii). .