SU1686451A1 - Device for interfacing information source with processor - Google Patents

Abstract

The invention relates to computing and can be used to input real-time digital information into a processor or to be pre-recorded on magnetic media. The purpose of the invention is to increase the speed of the device while maintaining the reliability of the recording. The goal is achieved by introducing a write pulse driver into the device containing the memory block, multiplexer, NOT element, AND element, counters and triggers for writing and reading, the comparison circuit, adder, buffer register and retters of the setpoint. 1 il.

Description

The invention relates to computing and can be used to input digital information into a processor in real or quasi-real time.

The aim of the invention is to improve the speed of the device.

The drawing shows a diagram of the device.

The device contains the input information bus 1 of the device, the memory block 2, the buffer register 3, the group of output information buses 4 of the device, multiplexer 5, read counters 6 and write 7, adder 8. comparison circuit 9, set register 10, write triggers 11 and read 12, element 13, element 14 of delay, shaper 15 of write pulse, element 16, input device set buses 17, first 18 and second 19 output readiness buses of device, input write buses 20 and device read 21, inputs 22 and 23 additional bits Dov first and second

multiplexer information input groups 5.

The device works as follows.

In the initial state, the counters 6 and 7 and the trigger 11 are in the state O, and the trigger 12 is in the state 1. Element I 13 is locked with logical O from the output of the element NOT 16. Multiplexer 5 is connected to the direction of the counter 6 reading. In register 10 of the setpoint, an additional code for filling depth of memory block 2 is entered. On tires 18 and 19 readiness - logical O.

When the first information word arrives on bus 1, its sync pulse arrives through the write bus 20 to the input of recording trigger 11 and sets it to state 1. The latter switches multiplexer 5 to the direction of write counter 7, and the logical 1 from input 22 multiplexer.

On the leading edge of the incoming signal, the shaper 15 outputs an IMC /

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the pulse to the control input of the memory unit 2 and the installation input to the write trigger 11, the latter is reset on the falling edge of the pulse. Element And 13 at the time of the write operation is blocked by the signal from the inverse output of the record trigger 11. On the falling edge of the signal from the direct output of the trigger 11, the counter 7 increments the address of the record, as a result, a logical O appears at the output of the comparison circuit, which opens the element And 13 through the NOT 16 element and sets the trigger 12 to the signal from the output of the latter.

The leading edge of the signal from the inverted output of trigger 12 is fed to the input of buffer register 3 and the information from memory block 2 is written to register 3, and logical 1 appears on readiness bus 18. When writing to memory block 2 to the level specified in the register 10 of the setpoint, a logical unit occurs at the transfer output of the adder 8, which, via the readiness bus 19, enters the processor interrupt system.

The processor can begin to read information from the device on the signal on the ready bus 18 and consider all the information on the signal on the ready bus 19. The information receiving gate and the processor enters through the read bus 21 to the trigger input 12 and sets it to state 1. The signal from the inverted trigger output 12 is fed to the counting input of counter 6 reading and raises its state. The direct output of trigger 12 through delay element 14 issues a request to output the next word from memory block 2 to the buffer register 3. If there is no write operation at the current time and there is at least one word in block 2, the signal from the output of the AND element 13 resets to the 0th trigger 12 reads, thereby putting the next word in register 3. After receiving the last word, due to the equality of the codes of the counters 6 and 7 from the output of the comparison circuit 9, it sets the device to its initial state.

Claims (1)

Apparatus for interfacing an information source with a processor, comprising a write trigger and a read trigger, the installation inputs of which are input recording and reading buses of the device, respectively, a buffer register, the output group of which is a group of output information buses of the device, and a group information inputs connected to a group of outputs of the memory block, a reading counter, a counting input connected to the synchronous buffer register, the first output bus of the device and inverse the output of the reading trigger, the element I, the output connected to the reset input of the trigger, and the first input through the delay element - with the direct output of the reading trigger, the comparison circuit whose output connected to the reset inputs of the write counter and the read counter and through the NO element to the second input of the AND element, the third input connected to the inverse output of the recording trigger, multiplexer, adder and set register, and the direct output of the recording trigger is connected to the counting input of the recording counter, group the outputs of which are connected to the first groups of information inputs of the comparison circuit, multiplexer and adder, the transfer output of which is the second output bus of the device, and the second group of information inputs is connected to the group of outputs of the register of the setpoint, the group the information inputs of which is the device setpoint bus, the output counter of the reading counter is connected to the second groups of information inputs of the comparison circuit and multiplexer, the group the control inputs of which are connected to the forward and inverse outputs of the recording trigger, and the group of outputs to the group of address inputs of the memory unit, the group of information inputs of which is an input information bus of the device, characterized in that, in order to improve speed, a write pulse shaper is inserted into it, the auxiliary output of the multiplexer is connected via a write pulse shaper to the reset input of the recording trigger and the control input of the memory unit, the additional bits of the first and second multiplexer information input groups connected respectively to the bus unit and zero potentials of the device.