SU1492484A1 - Device for demodulation of phase-shift keyed signal - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to reduce the likelihood of error. The device contains delay units 1 and 6, phase detectors 2 and 7, frequency multiplier 3, filter 4, frequency divider 5, threshold unit 8, AND 9, trigger 10, phase shifter 11, modulator 12, limit amplifiers 13 and 19, differentiation unit 14, counter 15, rc. 16 pulses, delay line 17, and majority sampling unit 18. The goal is achieved by eliminating jumps in the phase of the reference voltage over the duration of one clock cycle, as well as by determining the initial phase of the reference oscillation and monitor the phase change over a three clock interval. 1 il.

Description

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The invention relates to telecommunication technology and can be used in data transmission systems.

The purpose of the invention is to reduce the likelihood of O1t1bki.

The drawing shows the structural-electrical circuit of the device.

The device contains 1t first delay element 1, first phase detector 2, frequency multiplier 3, filter 4, frequency divider 5, second delay element 6, second phase detector 7, threshold block 8, element 9, trigger 10, phase shifter 11, modulator 12, the first effort

t el-limiter 13, the differentiating unit 14, the counter 15, the generator 16 pulses, line 17 delay, block 18 majority sampling and the second amplifier-limiter 19.

The device works in the following way.

Let a sequence of phase-shift keyed pulses enter the device input. In the frequency multiplier 3, the phase manipulation is eliminated, and in the filter 4 the interference effect is attenuated. When the frequency divider 5 is switched on, the first delay element 1 of the phases (5-rotator 11 and modulator 12) forms a reference edge, which is fed to the first input of the first phase detector 2. The phase rotator 11 equalizes the phase of the signal on the second input of the binary 12.

The reference oscillation is also fed to the second input of the second phase detector 7 directly from the output of the divider 5 frequency, and to the first, and from the output of the lepporo delay element 1. Until the phase jump of the reference voltage appears, the phase difference of the voltages at the outputs of the second phase detector 7 is constant and is determined by the delay time of the first delay element 1. In this case, the threshold unit 8 does not work. At the time of the appearance of the phase jump of the reference voltage, the voltage at the output of the second phase detector 7 also changes in a jump. The threshold unit 8 is triggered and the state of the trigger 10 is reversed, which in turn leads to a change in the phase of the reference oscillation at the output of the modulator 12.

The input sequence of the phase of the impulse pulses is also fed to the input of the first amplifier

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renichitel 13, which generates pulses with clearly defined front and decline, limited in amplitude. These pulses are input to the differentiating input (from block 14, which provides vii; the output of the front and rear edges of pulses. Short pulses from the output of differentiating unit 14 are fed to the first input of counter 15. The second input of the last receives a pulse from the output of generator 16 pulse 5c whose clock frequency is much higher than the clock frequency of the input signal. The fla output of counter 15 appears overflow signal only if the number of pulses coming from the generator output 16 pulses is greater, how can they be delivered in a single information period; t) HHoro signal. This occurs when the phase of the information signal changes. Thus, the overflow signal 5 at the output of the counter 15 appears at the moments of the phase change of the input phase-shift keyed signal.

The overflow signals then go to delay line 17, which delays the input pulses by three cycles.

From the outputs of the delay line 17, the pulses in parallel arrive at the inputs of the majority sampling unit 18, at the output of which a signal appears only in the case of two pulses out of three, i.e. two of the three are sampled. This is done in order to determine the initial phase of the reference oscillation. Before transmitting information signals, the transmitter inserts a three-pulse service signal into the channel, and the phase of the signal changes at the beginning of the pulse. This allows the control sig0 to be obtained at the output of the majority sampling unit 18.

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The signal that, through the element AND 9, enters the second input of the trigger and sets its unit state. During the transmission of information signals, the majority sampling unit 18 operates according to the working information, generating the output signal of each phase when a sequence of three pulses is ya (5 satisfies condition two of three. Thus, unit 18 of the majoro sample | sample, through element 9,

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trigger 10 and modulator 12 controls the phase of support K (x11).

The elements of the device are shlbrana in such a way that the phase shift of the reference voltage according to the signal from the majority sampling block 18 at the output of the modulator 12 must be high potential. Otherwise, a phase change will not occur. This condition is realized by element 9. The second limiting amplifier 19 forks pulses of the form necessary for triggering element 9. In the second element 6 of the delay, the input signal is delayed by the time of formation of the reference voltage.

Consequently, the circuit is the first delay element 1, the second phase detector 7, the threshold unit 8, the trigger 10 eliminates the phase jumps of the reference voltage on the duration of the trial cycle, and the circuit the first force cut-limiter 13, differential1CP1 TS111 block 14, counter 15 , generator 1b and pIlkos, delay line 17, 18 majority sampling, element If 9, trigger 10 determines the initial phase of the reference oscillation and monitors the phase change over the interval in kg

Formula and 3 optics

A device for demodulating a phase-mapping signal, comprising a first phase detector, a phase shifter, a series of which are connected by a frequency multiplier, a filter, and a divider.

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frequencies, but connected by the first delay element, the second phase detector, the threshold unit and the trigger, the first delay element being connected to the second input of the second detector 1a, characterized in that, in order to reduce the probability of error, a pulse generator is introduced, the second delay element , series-connected pervPCH amplifier-limiter, differentiating unit, counter and delay lines, series-connected majority sampling unit and element I, series-connected modulator and the second an amplifier-limiter whose output is connected to the second input of the element I, the output of which is connected to the second input of the trigger, the output of which is connected to the first input of the modulator, the output of which is connected to the first input of the first phase detector, the second input of which is connected to the output of the second delay element, the input of which is connected to the inputs of the first amplifier-limiter and frequency multiplier; the output of the frequency divider is connected to the input Q of the first delay element, the output of which is connected to the second input of the mod via the phase shifter l torus delay line outputs connected to inputs of plaque (; ka majority sample, and the pulse generator output is connected to the second input of the counter and the third input member I.

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Claims (1)

Formula and test A device for demodulating a phase-shifted signal.! Containing a first phase detector, a phase shifter, a series-connected frequency multiplier, a filter and a frequency divider, connected in series with the first delay element, the second phase detector, the threshold block and a trigger, wherein the input of the first delay element is connected to the second input of the second phase detector, characterized in that, in order to reduce the probability of error, a pulse generator, a second delay element, are introduced in series connected first amplifier-limiter, differentiating unit, counter and delay line, series-connected majority block and element And, series-connected modulator and second amplifier-limiter, the output of which is connected to the second input of element And, the output of which is connected to the second input of the trigger, output which is connected to the first input of the modulator, the output of which is connected to the first input of the first phase detector, the second input of which is connected to the output of the second delay element, the input of which it is single with the inputs of the first amplifier-limiter and frequency multiplier, the output of the frequency divider is connected to the input of the first delay element, the output of which is connected through the phase shifter to the second input of the modulator, the outputs of the delay line are connected to the inputs of the majority block, and the output of the pulse generator is connected to the second counter input and the third, input element I.