SU1479935A1 - Data source/receiver interface - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in computer complexes. The aim of the invention is to expand the class of tasks to be solved by ensuring the transformation of information transmitted through the device. The goal is achieved in that the device containing the input and output switches, two counters, two decoders and the first group of registers are entered into a block of trigger conditions for the transformation, a block of elements AND, a block of elements OR, a second group of registers, two triggers, two elements OR, an element And the three delay elements. Information from the source is received in quanta (e.g., bytes) and stored in the buffer registers of the first group. After receiving the last quantum, the information in the converted form is transmitted to the output registers of the second group and is provided to the information receiver by words (for example, 32 or 64 bits). The reception and transmission of information is carried out independently and is accompanied by corresponding clock pulses. 1 il.

Description

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The invention relates to computing and can be used in computer complexes.

The aim of the invention is to expand the class of tasks to be solved by ensuring the transformation of information transmitted through the device.

The drawing shows the proposed device.

The device contains a block 1 trigger conditions conversion, consisting of flip-flops 2 (p is the number of quanta of input information), input switch 3 consisting of p groups of elements And 4, the first and second groups of registers 5 and 6, output switch 7, consisting of

k groups of elements AND 8 and groups of elements OR 9, counters 10 and 11, decoders 12 and 13, block 14 elements AND, formed by groups of elements AND 15, block 16 elements OR, formed by K x L groups of elements OR 17 (K is the number of words in the output message, L is the number of input information quanta placed in the output message), triggers 18, 19, AND 20 element, OR elements 21 and 22, delay elements 23, 24 and 25, group of inputs 26 for specifying conversion conditions, synchronous input 27 , a group of information inputs 28, installation input 29, synchronous input 30 reading, a group of information outputs 31, outputs 32 and 33

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The device works as follows

A trigger impulse arriving at input 2.9 sets triggers 18 and 19 to a single state. From the direct output of trigger 18 to output 33, there is a single potential allowing the source to issue information to a group of inputs 28. Each quantum of information from the sources is accompanied by a sync pulse input 27, which changes the state of the counter 10. Using the decoder 12 and the switch 3, the quanta of information on the register 5 is sequentially stored. The synchronization pulse of the write to the last register 5 is simultaneously set Pushes trigger 18 into a bullet state. At the same time, output 33 receives a zero potential that prohibits the release of information by the source, and from

the inverse of the trigger 18 to the input element And 20 receives a single potential, from which with a delay equal to the sum of the delays of elements 23 and 24, a chain consisting of element II 20, delay elements 23 and 24, trigger 19, normalizes the pulse readiness of the device to issue information to the receiver coming from output 32. At this point, the pulse from the output of the delay element 23, by gating the elements 15, transmits information from the regitres 5 to the registers 6 and simultaneously sorts it according to the information recorded in three Gery 2.

The information in block 1 is entered before operation of the device. The unit g of the output of one of the flip-flops 2 of each line permits the transfer of information from registers 5 through the corresponding elements 15 to the register 6 “Impulses from the output of the delay element 24 also goes to the input ele. OR 21 and sets the trigger 18 to a single state, which again allows the release of information by the source about

After receiving the ready pulse from output 32, the receiver of the information begins to send to the input 30 sync pulses of the request, which change the state of the counter 11. With the help of de 99354

the encoder 13 is made alternately issuing information through the corresponding elements AND 8 and elements OR 9 from the outputs of registers 6 to the outputs 31 of the device to the receiver of information. The signal opening elements AND 8 simultaneously sets the trigger 19 to the single state, which initiates a new

the cycle of transferring information from registers 5 to registers 6 provided that registers 5 are filled with new information (trigger 18 in the zero state).

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, p) is connected to the input-i-ro group of the first group, the formula of the invention

A device for coupling the source and receiver of information, containing the first and second counters, the inputs of which are the corresponding inputs of the device for connecting to the sync outputs of the source and receiver of information, two decoders, an input switch, the group of information inputs of which is a group of inputs of the device for connecting group of information outputs of the information source, 1- group of outputs of the input switch (i 1

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an input switch whose output group is a device output group for connecting information receiver information inputs to a group, characterized in that, to expand the class of tasks of the device, a trigger condition trigger block, an AND block, a second OR block, and a second a group of registers, two triggers, two OR elements, an AND element and three delay elements, the outputs of the registers of the first group are connected to the first group of inputs of the block of AND elements, the second group of inputs connected to the groups The first outputs of the flip-flop block for conversion conditions, the input group of which is a group of inputs for specifying the device conversion conditions, 1 is the output group of the AND block and is connected to the i-th input group of the OR element block, and j is the output group of which (j 1, k.) through the j-th register of the second group to the j-th group of information inputs of the output switch, the gate input of which is connected to the input of the device for connection to the clock output of the information receiver, the outputs of the first and second counters are connected respectively naturally with the inputs of the first and second decoders, groups of outputs of which are connected respectively to the groups of address inputs of the input and output switches, the inverse output of the first and direct output of the second flip-flops are connected respectively to the first and second inputs of the I element, the output of which is connected through the first delay element with the enable input of the AND block and the input of the second delay element, the output of which is the output of the device for connection to the readiness input of the information receiver and is connected to the input and output throwing the second trigger and the first input of the first OR element, the second input of which is the installation input of the device and through the third delay element is connected to the first input of the second OR element, the second input connected to the last output of the output group of the second decoder, and the output of the second OR element is connected to the input the second trigger setup, the setup and reset inputs of the first trigger are connected respectively to the output of the first element OR and the last output of the output group of the first decoder, and the direct output of the first A trigger is the output of a device for connecting to the readiness input of a source of information.

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Claims (1)

Claim A device for interfacing a source and receiver of information, containing the first and second counters, the inputs of which are the corresponding inputs of the device for connecting to the synchronizing outputs of the source and receiver of information, · two decoders, an input switch, the group of information inputs of which is a group of inputs of the device for connecting to the group of information information source outputs, the i-th group of outputs of the input switch (i = 1, p) is connected to the group of inputs of the i-th register of the first group, the output switch, the group of outputs of which is the group of outputs of the device for connecting to the group of information inputs of the information receiver, characterized in that, in order to expand the class of tasks to be solved by the device, it includes a block of triggers for conversion conditions, a block of AND elements, a block of OR elements, a second group of registers, two a trigger, two OR elements, an AND element, and three delay elements, with the outputs of the registers of the first group connected to the first group of inputs of the block of AND elements, the second group of inputs connected to the group of outputs of the block three gers of conversion conditions, the input group of which is the group of inputs for setting the device conversion conditions, the i-th group of outputs of the block of elements AND is connected to the ίth group of inputs of the block of elements OR, the i-th group of outputs of which (j = 1, k) is connected via j -th register of the second group to the j-th group of information inputs of the output switch, the gate input of which is connected to the input of the device for connecting to the synchronizing output of the information receiver, the outputs of the first and second counters are connected respectively to the inputs of the first first and second decoders, the output groups of which are connected respectively to the address inputs of the input and output switches, the inverse output of the first and direct outputs of the second triggers of the connected trigger and the first input of the first OR element, the second input of which is the installation input of the device and through the third element the delay is connected to the first input of the second OR element, the second input connected to the last output of the output group of the second decoder, and the output of the second OR element is connected to the input corresponding to the first and second inputs of the AND element, the output of which through the first delay element is connected to the enable input of the AND element block and the input of the second delay element, the output of which is the output of the device for connecting to the readiness input of the information receiver and connected to the reset input of the second trigger installation , the installation and reset inputs of the first trigger are connected respectively to the output of the first OR element and the last. 15 is the output of the group of outputs of the first decoder, and the direct output of the first trigger is the output of the device for connecting to the readiness input of the information source.