SU1109781A1 - Device for transmitting messages in adaptive telemetric systems - Google Patents

Abstract

1. A DEVICE FOR TRANSMITTING MESSAGES IN ADAPTIVE TELEMETRIC SYSTEMS, containing The second outputs of which are connected respectively via the first and second series-connected differentiating elements and rectifiers with the first and second inputs of the first and second counters, the outputs of the first first and second inputs of the OR element, the output of which and the outputs of the address encoder and the information encoder are connected to the first, second and third inputs of the code generator, the second input of the redundancy block and the code generator output respectively are the corresponding input and The output of the device, characterized in that, in order to increase the accuracy and transmission of messages, the second player and the elements And, the second and third outputs of the redundancy block, are introduced into the device. Inen respectively with the input of the first trigger and the combined second input of the address coder and the first inputs of the first and second elements (in AND, the outputs of the first and second rectifiers are connected respectively to the first and second inputs of the second trigger, the first and second outputs are connected to the second inputs the first and second elements And, the outputs of which are connected to the third inputs of the first and second counters, respectively, the fourth inputs of which are combined and connected to the second output of the chroniser. 2. The device according to claim 1, stating that the redundancy reduction block contains keys, triggers, AND elements, a comparison element, delay elements, and ele1 | 1ent memory, the output of the first key is connected to the input of the memory element, the first and second outputs of which are connected respectively to the first input of the second key and with the combined first inputs of the third key and the reference element, the output of the comparison element, the output of the first trigger and the first output cx of the second trigger, respectively third entrances lane And, the output of which is connected to the combined first inputs of the first delay element, the first trigger and E the second input of the second key, the output of the second key is connected to the zero potential bus, the output of the first key and through the second load element - to the second input of the first trigger and the first input the second trigger, the second output of the second trigger is connected to the first input of the second element And, the output of which is connected directly to

Description

the second input of the third key and through the third delay element with the second input of the second trigger, the second input of the second element AND and the combined second inputs of the first key and the comparison element are the first and second inputs of the redundancy reduction unit and the third key, respectively; The second element And are respectively the first, second and third outputs of the redundancy reduction unit.

The invention relates to information and measuring technology and can be used in adaptive address telemetry systems. A device for generating messages is known that contains a redundancy reduction block, memory blocks and a C11 service information generation block. The closest to the proposed technical essence is a device for transmitting messages in adaptive telemetry systems containing a chronizer, the output of which is connected to the first inputs address coder, information coder and redundancy reducer, the output of redundancy reducer is connected to the second inputs of the encoder of the address of the information coder and to the trigger input, The first and second outputs of the trigger are connected via the first and second successively connected differentiating elements and rectifiers with the first and second inputs of the first and second counters, and the outputs of the first and second counters, respectively. Yineny with the corresponding first and second inputs of the OR element, the output of which and the outputs of the address coder and information coder are connected with, respectively. the first, second and third inputs of the code generator, the second input of the redundancy reduction unit and the output of the code generator are respectively the input and output of the device 2. A disadvantage of the known devices is the low accuracy of transmitting messages jx, due to the large error in measuring the time intervals between successive significant readings of messages. The purpose of the invention is to increase the reliability and transmission of messages. This goal is achieved in that a device for transmitting messages in adaptive telemetry systems, comprising a chronizer, the first output of which is connected to the first inputs of an address coder, an information encoder and a redundancy reduction unit, the first output of a redundancy unit, trigger, the first and second outputs of which are connected via the first and second successively connected differentiating elements and rectifiers with the first and second inputs of the first, respectively and the second counters, the outputs of the first and second counters are connected to the corresponding first and second, inputs of the OR element, the output of which and the outputs of the address encoder and information encoder are connected respectively to the first, second and third inputs of the code generator, the second input of the redundancy block and the code generator output input and output of the device, respectively, the second trigger and the elements And, the second and third output of the redundancy redundancy block, are connected respectively to the input of the first trigger and combined the second input of the address coder and the first inputs of the first and second elements And, the outputs of the first and second rectifiers are connected respectively to the first and second inputs of the second trigger, the first and second outputs of which are connected to the second inputs of the first and second elements respectively, the outputs of which are connected to the third inputs, respectively, of the first and second counters, the fourth inputs of which are combined and connected to the second output of the chroniser. In addition, the redundancy block contains keys, triggers, AND elements, a comparison element, delay elements and a memory element, the output of the first key connected to the input of the memory element, the first and second outputs of which are connected respectively to the first input of the second key. and with the combined first inputs of the third key and the comparison element, the output of the comparison element, the output of the first trigger and the first output of the second trigger are connected respectively to the first, second and third inputs of the first element AND, the output of which is connected to the combined first inputs of the first element of the Sampler, the first trigger and with the second input of the second key, the output of the second key is connected to the zero potential bus, the output of the first key and through the second delay element to the second input of the first trigger and the first input of the second tr igger, the second output of the second trigger is connected to the first input of the second element And, the output of which is connected directly to the second input of the third key and through the third delay element to the second input of the second trigger, the second input of the second element And and the combined second inputs of the first key and the comparison element The first and second inputs of the redundancy block, respectively, the outputs of the third key, the first delay element and the second element And are respectively the first, second and third outputs of the reduction block Redundancy.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a block diagram of a redundancy unit; in fig. 3 - time diagrams for the device operation

The device (Fig. 1) contains a chronizer 1, a redundancy reduction block 2, an address coder 3, an information coder 4, a time coder 5, a code generator 6, a trigger 7, differentiating elements 8 and 9, rectifiers 10 and 11, binary counters 12 and 13, element OR 14, trigger 15, elements AND 16 and 17.

The redundancy reduction unit (Fig. 2) contains a comparison element 18, element 19, key 20, trigger 21, delay element 22, key 23, memory element 24, delay element 25, trigger 2.6, key 27, and element 28, the delay element 29.

The device works as follows.

Chronizator 1 outputs (Fig. Over) clock control pulses to the inputs of blocks 2-4. Block 2 redundancy gives (Fig. 3, c) pulses at the moments of the occurrence of significant samples to the input of the trigger 7; the pulses at the moments coinciding with the clock control pulses, if there is a significant reference to the inputs of the address 3 encoder and And 16 and 17 elements, the substantial readings to the input of the information encoder 3 (Fig. Wk),

Using these samples and clock signals, the address coder 3 generates code combinations that display the channel number (the address of the parameter to be measured) to which the count belongs, and encoder 4 generates a code that displays the value of the measured value of the significant sample. Encoder 5 measures the time interval (Fig. 3 d, h) the time intervals between true1 and the moments of occurrence of significant samples and forms, corresponding to the measured time intervals, code combinations, which are generated by the imaging unit 6 of the full code of reference in the moments of reading the significant samples from block 2. Unit 6 forms (FIG. 3c) the complete reference code.

Block 5 works as follows

At the moments of significant counts (Fig. Sv), a change in the state of trigger 7 (Fig. 3) occurs. Differentiated and passed through diodes 10 and 11 (Fig. 3 e,) pulses arrive at the trigger inputs of one and the stop inputs of another counter 12 and 13 and the trigger inputs 15. The trigger 15 controls (FIG. 3 L, m) passing, through the AND elements 16 and 17, the read samples (FIG. SC) of significant readings to the read inputs of the counters 12 and 13. Upon entering the read inputs of the counters 12 (13) signal, from the outputs of counters 12 (13) through the element OR 14 to block to 6, a code combination is output, corresponding to the measured time interval between the true moments of the occurrence of significant samples.

The redundancy reduction unit 2 operates as follows.

A signal from the output of the sensor enters the signal input of the key 23 and one input of the comparison element 18, and the other input of the comparison element 18 receives a signal from the output of the memory element 24. The signal from the output of the memory element 24 has a level (amplitude) corresponding to the value of the level of the last transmitted significant sample. If the amplitudes of the signals from the output of the sensor and the output of the memory element 24 are not equal to the specified aperture, the comparison element 18 emits a pulse that passed through AND 19 , is fed to the input of the trigger 21, the control input of the key 20 and the input of the element 22 of the delay. When a pulse arrives from the output of element 19 to the input of trigger 21, the latter overturns and a low (zero) potential is established at the output of trigger 21, thereby preventing the passage of pulses from the output of element 18 through element 19 when resetting information about the value of the previous essential reading from element 24 memories and records in the memory elements 24 of information about the meaning of the new substantial reference.

/ When a pulse arrives from the output of the element 19 at the control input of the switch 20, the latter opens and the memory element 24 is reset through the switch 20 (the memory capacitor is discharged). After the memory element 24 is zeroed out of the output of the delay element 22, a pulse arrives at the control input of the key 23, which opens the key 23 and the information about the current pargshetra value is written to the element 24 (the memory capacitor through the public key 23 is charged to the current value of the parameter / t to the level of meaning of the new substantial reference). At the same time, the pulse from the output of the Escherzka element 22 (Fig. 3 Sv) is transmitted to the signal output of the block 2 and reduced to the input voltage and to the input of the delay element 25. The impulse from the output of the element 25 draws | 1; and enters the inputs of the flip-flops 21 and 26. The flip-flop 21 returns to its original position, and the flip-flop 26 walks back to the zero state. A low potential is established at the output of the trigger 26, thereby prohibiting the passage of pulses from the output of element 18 through element 19 before the moment of reading the value of the new substantial count from redundancy reduction block 2. At the same time, a high potential is established at the output of the trigger 26, connected to the input of the element 28, which allows the passage of clock control pulses (Fig. 3a) through the element 28 and 28. The first clock control pulse received at the input of the element 28 after tilting 26, passes through the element 28 and provides a read (FIG. 3k) of a substantial reading from redundancy reduction unit 2. The clock pulse from the output of the element 28, having passed through the element 29 of the delay, sets the trigger 26 to its initial state. After this, the cycle of operation of redundancy block 2 is repeated. Thus, the proposed device provides a measurement of the time intervals between significant readings with high accuracy.

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Claims (2)

1. DEVICE FOR TRANSMISSION OF MESSAGES IN ADAPTIVE TELEMETRIC SYSTEMS, comprising a timing device, the first output of which is connected to the first inputs of the address encoder, information encoder and redundancy reduction unit, the first output of the redundancy reduction unit is connected to the second input of the information encoder, the first trigger, the first and second outputs which are connected respectively through the first and second series-connected differentiating elements and rectifiers with the first and second inputs of the first and second Counters, the outputs of the first the counters are connected to the corresponding first and second inputs of the OR element, the output of which and the outputs of the address encoder and the information encoder are connected respectively to the first, second and third inputs of the code generator, the second input of the redundancy reduction unit and the output of the code generator are the input and output of the device, different the fact that, in order to increase the reliability and transmission of messages, the second trigger and AND elements are introduced into the device, the second and third outputs of the redundancy reduction unit are connected with Accordingly, with the input of the first trigger and the combined second input of the address coder and the first inputs of the first and second elements AND, the outputs of the first and second rectifiers are connected respectively to the first and second inputs of the second trigger, the first and second outputs of which are connected to the second inputs, respectively, of the first and the second AND elements, the outputs of which are connected to the third inputs of the first and second counters, respectively, the fourth inputs of which are combined and connected to the rum output of the chronizer. 2. The device according to π. 1, the fact that the redundancy reduction unit contains keys, triggers, AND elements, a comparison element, delay elements and an element ₍ memory, the output of the first key is connected to the input of the memory element, the first and second outputs of which are connected respectively to the first the input of the second key and with the combined first inputs of the third key and the comparison element, the output of the comparison element, the output of the first trigger and the first output of the second trigger are connected respectively to the first, second and third inputs of the first element And, the output of which is connected is connected with the first inputs of the first delay element, the first trigger and With the second input of the second key, the output of the second key is connected to the zero potential bus, the output of the first key and through the second delay element with the second input of the first trigger and the first input of the second trigger, the second output the second trigger is connected to the first input of the second element And, the output of which is connected directly to the second input of the third key and through the third delay element to the second input of the second trigger, the second input of the second element And and the second second inputs of the first key and the comparison element are respectively the first and second inputs of the redundancy reduction unit, the outputs of the third key, the first delay element and the second AND element are respectively the first, second and third outputs of the redundancy reduction unit.