SU1197116A1 - Device for reception of binary signals - Google Patents

Abstract

A BINARY RECEIVING DEVICE containing a serially connected synchronization signal extraction unit and a synchronization unit, the first output which is connected to the clock input of the first registration unit, whose information input is combined with the input of the synchronization signal extraction unit and the outputs of the master oscillator are connected to the second and third inputs of the synchronization unit, characterized in that, in order to obtain the accuracy of the binary information, into it serially connected first register, first delay block, second register block, second register and switch, as well as the second delay block, pause detector, counter and trigger,. the KOTppdro output is connected to the control input of the switch, to the second input of which the output of the second delay unit is connected, while the output of the pause detector is connected to the setpoint input of the counter and to the first setup input of the trigger, the counter output is connected to the information input which, as well as to the clock input of the pause detector, to the second clock input of the second delay unit and to the control input of the second register is connected the second one of the synchronization unit, the first code of which It is connected to the first clock input of the second delay block S ka, to the clock input of the second registration block and is (L the clock output of the device, the information output of which is the switch output, and the output of the first registration block is connected to the information inputs of the second delay block and pause detector, the synchronization input of which is the synchronization input of the device, whose information input is combined with the information input of the first register, to the control input of which and the first one The first output of the master oscillator is connected to the input of the first delay unit, the second output of which is connected to the second clock input of the first delay unit.

Description

one

The invention relates to communications and is intended to receive binary signals in synchronous communication systems in which there is no synchronization before the start of a message, and its source is informational sprinkling of the message.

The purpose of the invention is to improve the accuracy of receiving binary information.

FIG. 1 shows a structural -scheme of a binary signal receiving device; in fig. 2 is a block diagram of the delay unit; in fig. 3 block diagram of the pause detector; in fig. 4 and 5 are time diagrams that show how the proposed device works.

The device for receiving binary signals contains the first 1 and second 2 registers, the first 3 and second 4 delay blocks, the first 5 and second 6 registration blocks, the switch 7, the master oscillator 8, the synchronization block 9, the synchronization signal extractor 10, the detector, 11 pauses, counter 12, trigger 13. Delay blocks 3 and 4 contain address counter 14, memory element 15, register 16, pause detector 11 contains the first element AND 17, the first element OR 18 shift register 19, the second element AND 20, the adding counter 21, the threshold element 22, the element is NOT 23, the third element And 24, in Ora element 25, the control unit 26. .

The device receiving binary signals works as follows.

The received binary signals in the form of a sequence of single elements 0.1 (Fig. 4a) are received via the information input of the device to the information input of the first register 1, the first registration unit 5 and the synchronization signal allocation unit 10 (in Fig. 4a the binary signals are shown without distortions ). The synchronization signal allocation unit 10 generates synchronization signals at its output in the form of short pulses coinciding in time with the fronts of the parcels (moments of changing significant positions, acting on the first (synchronizing) input of the synchronization unit. 9 The master geerator generates at its first and second outputs periodic sequences of pulses shifted one relative to the other by half 162 of the pulse repetition period and

having high stability

where B is the speed of manipulation of binary signals; m is an integer.

The synchronization unit 9 generates clock pulses at its first and second outputs, adjusting their phase by adding or excluding pulses controlled by synchronization signals from the pulse sequences of the master oscillator B and then dividing their frequency by m times. At the exact synchronization position, the clock pulses at the first output of the synchronization unit 9 coincide with the center (Fig. 4b), at the second output - with the border (Fig. 4c) of individual elements. .

The first register 1 discretes the received signals at the points in time specified at its control input by pulses from the first output of the master oscillator 8, and stores the samples received at that time for a time equal to the sampling period. The output signal of the first register 1 is fed to the information input of the first block 3 of the delay, which delays it by a time multiple of the duration 7o of the unit element And equal to the time of entry into the phase of the synchronization unit 9. The pulses from the outputs of the master oscillator 8 control the signal delay on the first and second clock inputs of the first 3 delay blocks.

The first 5 and second 6 registration blocks analyze the received and delayed binary signals and, at time points, which are set at their clock inputs by clock pulses from the first output 9 of the synchronization unit, form decisions about which binary elements were transmitted: O or 1. Output the signals of the second recording unit 6 are memorized by the second register 2, which also provides an additional delay for the time since its control input is affected by so-called pulses from the second output of the synchronization unit 9 ( ig. 4c), delayed by this time, 3 m. Regarding the recording clock pulses from the first output of the latter (Fig. 4b), the output signals of the first recording unit 5 arrive at the information input of the second delay block 4, which delays them for the time under control of the clock pulses, arriving at the first and second cycles, second inputs of the second block 4 delays, from the first and second outputs. block 9 of synchronization. The binary signals from the output of the second register 2 and the second delay block 4 are received respectively at the first and second inputs of the switch 7. The signals have the same delay relative to the received binary signals, but differ in the delay in their registration. The diagrams (Fig. 5) correspond to the case, when the pause duration is shorter than the time of entry into the phase, the communication begins. With the new phase of single elements. Since the first registration unit 5 takes the decisions directly from the incoming signals, the second registration unit 6 to the delayed signals, and the synchronization unit 9 sets the exact synchronism position after entering the phase in the initial part of the message, the low authenticity registration by the first registration unit 5 takes place at the beginning of the message (the shaded area in Fig. 4 with the second recording unit 6 is in the message message (the shaded area in Fig. 5c). The pause does not contain synchronizing information, therefore you have The fidelity of registration of delayed signals by the second registration unit 6 during a pause at the information input of the device is supported by the required stability of the transmitting and receiving side generator sets. The pause detector 11 analyzes the binary signals received at its information input from the code of the first registration unit 5 and at On the appearance of a pause between messages, a pulse (Fig. 5d) forms at the output of the pause detector 11, which sets the counter 12 to zero and the trigger 13 in one unit. The single state of the trigger 13 ( ur. 5d controls the switch 7 in such a way that a message section from the output of the second delay unit 4 (FIG. 56), characterized by recording the binary signals with high confidence, is switched to the information output of the reception device 16. The counter 12 summarizes the clock pulses from the second output of the synchronization unit 9, and after counting the time interval with the duration t forms at its output a pulse that sets the trigger 13 to zero. The zero condition of the trigger 13 (Fig. 5e) switches to the information output of the device the message section from the output of the first register 2 (Fig. 5c), also characterized by the registration of binary signals with high reliability. The zero state of the flip-flop 13 is confirmed by the counter 12 until the pause between the messages is again detected. The delay of the signals in the first 3 and second 4 blocks of the delay occurs as follows. The binary signals from the information input of the block 3, 4 delays arrive at the information input of the memory element 15. On the first 3 and second 4 clock inputs of the delay unit. The impulses distributed in time and space are blunt. The pulses from the first clock input are summed by the address counter 14, the code outputs of which are connected to the address inputs of the memory element 15. After the counter 14 establishes the address of the next address, the contents of the memory cell selected by it are read to the input of the register 16. The next pulse / second clock input then goes to the control input of the memory element 15, register 16 and writes the signal c to the first at the same address information input, and in the second - the read signal. The signal recorded in register 16 is transmitted to the output of the 3.4 delay block. The addresses of the cells of the memory element 15 periodically change from O to DoK -1 in the first block 3 delays and from O to -1 in the second delay block, where. Therefore, each recorded from the information input signal in the memory element 15 is transmitted to the output of the delay block 3.4 after N clocks and the first delay block 3 and after — clocks in the second delay block 4, while the delay time is proportional to the period 5 of the clock pulses on the second clock input block 3.4 delay. The pause detector 11 operates as follows. Binary signals from the output of the first registration block 5 are sent to the information input of the pause detector 11, the clock pulses accompanying them from the second output of the synchronization block 9 to the clock input of the pause M detectors. Each clock pulse passes through the second OR 25 element to the control input of shift register 19 and shifts its contents one bit to the right while simultaneously recording the binary signal that passes on. the information input of the 19th shift register through the third element AND 24 and the first element OR 18 at this time. As a result, at each clock interval (interval between adjacent clock pulses) the shift register 19 contains a selective combination formed by the binary signals received in this and preceding clock intervals where N is the number of bits of the register 19 shift. Each clock pulse. With the clock input of the pause detector 11 initiates the control block 26, which of the sync pulses arriving at the device’s INPUT sync, generates the following control signals in the clock and terval: on the first output of the control block 26, the recirculation command of the SSCR in the form of a logical 1 signal - on the second output - a single pulse; at the third output - a pack and 16 pulses, which coincides in time. and with CRC and following after a single pulse. The CRC from the second output opens the first element I 17 and, the passage through the element NOT 23. closes the third element AND 24. As a result, the pause detector 11 is switched to recirculation mode, in which the pause detector 11 information input is prohibited and the shift register 19 is disabled connected to its input through the first elements AND 17 and OR 18.- A single pulse from the second output of the control unit 26 sets the summing counter 21 to zero. Then, the stack of pulses from the third output of the control unit 26 passes through the second element OR 25 to the control input of the relay istra 19 performs shift and cyclic shift (recycling) it contains IMDG. The bits of the selective combination appearing in this case at the output of the shift register 19 are gated with pulses of the same bundle in the second element, And 20, and are fed to the input of the summing counter 21. At the end of the bundle, the selective combination takes the same position in the shift register 19, and the summing count | 21 will contain the number of its binary signals l..EdW this number exceeds the threshold number in the threshold element 22, the latter generates a pause detection signal, which is calculated at the output of the pause detector 11 at the time of the clock pulse at the gate input of the threshold element 22 from the clock input of the pause detector Ii (meaning the case when the pause is represented by binary signals 1).

FIG. g

FIG 3

Fig l

Post L

Pause Message

Claims (1)

A binary signal receiving device comprising a synchronization signal extraction unit and a synchronization unit connected in series, a first output connected to a clock input of the first registration unit, the information input of which is combined with the input of the synchronization signal extraction unit and is an information input of the device, while the outputs of the master oscillator are connected to the second and third inputs of the synchronization unit, which requires that, in order to increase the accuracy of reception, binary information is introduced into it the first register, the first delay unit, the second registration unit, the second register and the switch, as well as the second delay unit, a pause detector, a counter and a trigger, the output of which is connected to the control input of the switch, the second input of which is connected to the output of the second delay unit, in series this pause detector output is connected to the installation input of the counter and to the first installation input of the trigger, to the second installation input of which the output of the counter is connected, to the information input of which, as well as to to the second input of the pause detector, the second clock input of the second delay unit and the control input of the second register is connected to the second-output of the synchronization unit, the first output of which is connected to the first clock input of the second block _ About the delay, to the clock input of the second <g second registration block is the clock output of the device, the information output of which is the output of the switch, and the output of the first registration block is connected to the information inputs of the second delay block and pause detector, the synchronizing input of which is the synchronizing input of the device , the information input of which is combined with the information input of the first register, to the control input of which and the first clock input of the first delay unit is connected the first output for a supply generator, the second output of which is connected to the second clock input of the first delay unit. 9lU6ll ^{, B} PB (