SU1171799A2 - Device for interrupting when debugging programs - Google Patents

Abstract

DEVICE LLY INTERRUPTION DURING PROGRAMS of auth. St. No. 962945, differing from the fact that, in order to expand the field of application of the device for debugging real-time programs, the fourth and fifth elements OR, the tenth and eleven elements AND, the fourth and fifth registers, the fourth block are entered into the device comparison, a blocking trigger, an operation mode setting switch, the output of the ninth And element and the third OR element are connected respectively to the first to the second inputs of the fourth OR element, the output of which is connected to the first input of the tenth And element Exit tumbler specifying the operating mode is connected to the second input of the tenth AND gate, whose output is connected to the zero input of the lock latch and the first input of the eleventh AND gate, the device attribute command input coupled to the second input of the eleventh AND gate, the fourth input of the synchronization register, whose output. connected to the first input of the fourth comparison unit; the device’s address input is connected to the information inputs of the fourth and fifth registers; the output of the eleventh I element is connected to the synchronization input of the fifth register whose code is connected (L to the second input of the fourth comparison unit, the fourth code block). comparison is connected to the first input of the fifth RSHI element, the code of which is connected to the single input of the blocking trigger, the output of which is the output of the device’s time counter lock, the start input of the device and coupled to a second input of the fifth OR with the element;. of

Description

 1 .1 17 The invention relates to computing, namely, devices for program control, and can be used in the development and debugging of programs for computers. The drawing shows a block diagram of the proposed device. - The device contains the first register 1, the first comparison block 2, the second comparison block 3, the first element. And 4, the second register 5. The outputs of the first 1 and second 5 registers are connected respectively to the first inputs of the first 2 and second 3 comparison nodes, the outputs of which are connected respectively to the first and second inputs of the first And 4 element. The first information input 6 of the device is connected to the second input the first block 2 comparison. The device also contains a control register 7, a third register 8, a third comparison block 9, the first and second elements RTIM 10 and 11, the second, third and fourth elements AND 12-14, the first 15, the second 16 and the third 17 groups of elements I, p 18, sixth 19, seventh 20 and eighth 21 elements AND, element NOT 22, group of elements OR 23, nine element AND 24, third element OR 25, first 26, second 27, third 28 and fourth 29 control inputs, second 30 and third 31 information inputs, first 32 and second 33 control inputs. In addition, the drawing shows the register 34 command numbers. the write address register 35, the register number 36 of the general purpose register (RON) of the central processor (CPU), which are part of the central control of the computer and are not part of the device for interrupting the debugging of programs, and serve only to explain its operation. The device also includes a fourth element OR 37, the tenth element. And 38, a lock trigger 39, an operating mode setting switch 40, an eleventh element, a fourth register 42, a five register 43, a fourth comparison block 44, the fifth element KS 45 , the output 46 of the device’s time counter lockout, the device start-up run 47. Registers 1, 5, 7 and 8 are toggle registers. Register 1 serves to set the upper limit of addresses of the program being debugged, register 5 to set the lower limit of addresses of the program being debugged, register 7 to set debugging modes of operation (stop or interrupt by coincidence of the current command number with the specified command number, by coincidence of the current address The cells with the specified address of the cell and m, d,), and the register 8- to set the address. checks or command numbers in debug modes. The device can operate in one of four modes set using the toggle register 7 control,. In mode I, when writing to a cell whose address (the contents of register 35) coincides with the address dialed on the toggle register. 8, the device generates a signal at output 33, which goes to. a computer interruption system whose program is to be debugged. At the same time, the blocking of the operation of computer time counters (control output 46) is ensured, thereby achieving real-time shutdown. In mode y, if the address of the command being executed (the contents of register 34) coincides with the contents of register 8, control signals 33 and 46 are generated, Mode III differs from mode I by comparing not the contents of register 35, but the contents of register 36, and the interrupt signal is not generated by writing to a cell, but by writing to the general register whose number is in register 36. In W mode, The system generates a signal at outputs 33 and 46 when executing a transition command. Operation of the device in all debugging modes starts from setting the registers 1 and 5 to the beginning and end of the debugging zone (the first and last program addresses to be debugged). When the computer is running, the command number register 34 contains the number of the command to be executed, which via the first information input 6 The device enters the second inputs of the first and second blocks 2 and 3 of the comparison. At the output of the first comparison unit 2 there is a positive potential only if the command number is greater than the number dialed on the first register 1, and at the output of the second comparison unit 3 there is a signal

positive polarity only if the command number is less; numbers dialed on register 5.

This ensures the operation of the device in the area of the programs to be debugged. Outside this zone, the operation of the device is blocked by zero potential from the output of the element AND 4, which enters the inputs of the elements 18 and 19, and the zero potential of the output of these elements blocks the elements 21, 24 and 20. The zero potential from the output of the element 24 blocks the element OR 37 and the zero potential from the output of the element OR 37 blocks the element AND 28, thereby ensuring the zero state of the trigger 39 of the lock (the trigger is reset during the initial start of the computer on the Start-up signal - input 47 of the device, which through the element OR 45 enters the single input of the trigger 39 pa lock At the first 32, second 33 and third 46 actuating device outputs zero potential is present, but no effect okazgaaet narabote processor and computer time counters, which is subject to debugging program..

The operation of the device in mode I is as follows.

The program debugging operator sets the G and Debug modes on control register 7, and at the same time unit potentials appear on the first and fifth outputs of register 7. When executing the program to be debugged, the addresses of the e, my commands are between the adjoining devices on registers 1 and 5, therefore, at the output of the first element I 4 there is a positive potential.

Each write command in the computer's RAM is accompanied by a potential control, which comes from the processor through the first control input 26 of the device to the second input of the element 12, the first input of which receives a positive potential from the first output of the control register 7, from the output of the second element 12 positive potential through the second element OR 11 is fed to the control input of the third comparison unit 9, thereby comparing the information typed in the third register 8 with the contents of register 35 of the address

the record, which is part of the EVM. The contents of the record address register 35 through the first group of elements AND 15 and OR 23 are fed to the second information-input of the third block 9 of the comparison. When the contents of the third register 8 coincide with the contents of the register 35 of the write address, a positive potential is produced at the output of the comparison block 9, which enters the second input of the second element AND 18, and the first and third inputs receive the resolving potentials from the output of the first elements OR 10 and AND 4. The positive potential from the output of the first element And 18 and through the eighth element And 21, the third element of the ШШ 25 goes to the second control output 33 of the device, which is connected to the computer interrupt register. At the same time, the positive potential from the output of the AND 24 element goes through the OR element 37 to the first input of the AND 38 element, if there is a resolving positive potential (the operator performs the real-time operation mode before starting the program debugging) by setting switch 40 to Real time (PB ). Switch 40 delivers a positive potential to the input element And 38, a positive potential from the output software | The last arrives at the zero input of the blocking trigger 30, at the output 46 of which a positive potential is formed that blocks the operation of the computer time counters. Thus, the output signal 33 of the computer, the programs of which are to be debugged, terminates its operation and makes a call to a wedging (debugging) program, which performs predetermined actions depending on the programmer's debugging task, real-time computer time is provided. If there is a resolving positive potential with

the output of the element 38, which is fed to the first input of the element 41, and on the arrival of the control signal from the control input 27, which is supplied to the second input of the element 41,

a control signal is generated for recording information register 42 from the information input of the device 6. Thus,

memorizing the address of the command at the interrupted point of the program being debugged. After the computer leaves the debugging program, i.e. going beyond the debugging zone, which is determined by the toggle registers 1 and 5, at the output of the AND 2A element appears a zero potential, which through the OR 37 and AND 38 elements enters the zero input of the blocking trigger 39, thereby providing the last potential for its single input.

. After the interrupting (debugging) program of the computer is executed, the debugged program returns to the interrupted point, register 43 ensures that the current program address is memorized by the control signal from input 27 of the device, information input 43 is connected to device information input 6. When returning to the interrupted point of the program, the contents of registers 4 and 5 coincide, at the output of comparison unit 44 a positive potential is produced, which through the element OR 45 enters the single input of the blocking trigger 39 and sets it to the zero state. At the output 46 of the device, there appears a zero potential, which permits the further operation of the time counters of the ECM. Similarly, the device operates in other modes.

In ij mode, the device detects an interrupt signal if the command number dialed on register 8 matches the number on register 34 of the command number. The inclusion of each command is accompanied by a control signal fed to the computer, which includes the proposed device, to input 27. This control signal passes through the elements AND 13 and OR 23 n

interrogation of the third block 9 comparison.

.

In i | i mode, the device generates an interrupt signal when recording information into one of the general purpose registers of a computer, the number of which matches the number dialed in the third register 8. Device operation in W mode differs from mode I in that when writing to the general register The computer produces a control signal at output 28, which through the elements AND14 and OR11 enters the interrogation of the comparison circuit, the second input of which from register 36 through input 31, the group of elements AND 17 and the group of elements OR 23 enters the number of the general purpose register . In IV mode, the device must generate an interrupt signal when executing a transition command.

On the fourth and fifth outputs of the control register 7, positive potentials are established, from the output of the first element I 4 to the first input of the element I 19 arrives a positive potential, since debugging occurs within certain limits specified on registers 1 and 5. When executing the transition command, .second input element I 19 from the decoder of computer commands, through the quarter input 29 of the device receives a positive potential. The output positive potential through the elements AND 20 and OR 25 enters the computer interruption system. If a zero potential is set at the fifth output of the control register 7, then a unit potential appears at the output of the NOT 22 element, which enters the input of the AND 24 element. If the output of the control register 7 is set to one of the I 5 u or W modes , then the appearance of a positive potential at the output of the element And 18 leads to the appearance of a signal at the output of the element And 24 and at the control output 32 of the device. The signal from the control output 32 of the device enters the computer and causes it to stop.

At the same time, the positive potential from the output 32 of the device goes through the element OR 37 to the input of the element 38, when setting the real-time operation (the positive potential at the output of the key 40 setting the operation mode in real time), the lock is activated in the block 39. At the output 46 of the device, a positive potential appears, which prohibits the operation of computer time counters.

The blocking trigger 39 is reset by a Start signal received by the control input 47 of the device from the computer after the computer has been started by the operator. After resetting the trigger 39

The blocking is allowed for the further operation of computer time counters.

The proposed device is an effective and efficient means of interrupting the program being debugged when writing to a specific memory cell, when executing a transition command, when executing a command whose address is specified in advance, when writing to one of the general registers whose number is specified in advance. This ensures a significant increase in the efficiency of debugging and shortening the time for debugging programs.

In addition, it is possible to synchronously stop the operation of time counters of the computer with interruptions (or stops) of the computer processor when implementing debugging modes, and the device provides for the immediate neutralization of interruptions or stops, which is important when developing software for automated control systems operating in real time. . Neutralizing debugging interrupts and shutdowns also provides a command from false alarms (overflows) of computer time counters, oriented towards time control.

1.5 execution of individual sections of the program complex, which allows to increase the efficiency and reliability of the process of debugging complex software systems.

Claims (1)

DEVICE FOR INTERRUPTION WHEN DEBUGGING PROGRAMS by ed. St. No. 962945, characterized in that, in order to expand the scope of the device for debugging programs operating in real time, the fourth and fifth OR elements, the tenth and eleventh AND elements, the fourth and fifth registers, and the fourth comparison block are introduced into the device , a locking trigger, an operation mode setting switch, wherein the output of the ninth AND element and the third OR element are connected respectively to the first and second inputs of the fourth OR element, the output of which is connected to the first input of the tenth AND element, output m mblera job mode is connected. with the second input of the tenth element And, the output of which is connected to the zero input of the blocking trigger and the first input of the eleventh element And, the input of the command attribute of the device is connected to the second input of the eleventh element And, the synchronization input of the fourth register, the output of which. connected to the first input of the fourth comparison unit, the address input of the device is connected to the information inputs of the fourth and fifth registers, the output of the eleventh element is connected to the synchronization input of the fifth and fifth register, the output of which is connected to the second input of the fourth comparison unit, the output of the fourth comparison unit is connected with the first ί input of the fifth OR element, the output of which is connected to a single input of the blocking trigger, the output of which is the blocking output of the device’s time counter, the device’s start input is connected inen with the second input of the fifth element OR. SU p „1171799 • 1 1171799