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SG11201706914TA - Memory device controlling method and memory device - Google Patents

Memory device controlling method and memory device

Info

Publication number
SG11201706914TA
SG11201706914TA SG11201706914TA SG11201706914TA SG11201706914TA SG 11201706914T A SG11201706914T A SG 11201706914TA SG 11201706914T A SG11201706914T A SG 11201706914TA SG 11201706914T A SG11201706914T A SG 11201706914TA SG 11201706914T A SG11201706914T A SG 11201706914TA
Authority
SG
Singapore
Prior art keywords
memory device
controlling method
device controlling
memory
controlling
Prior art date
Application number
SG11201706914TA
Inventor
Kosuke Yanagidaira
Shouichi Ozaki
Original Assignee
Toshiba Memory Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Memory Corp filed Critical Toshiba Memory Corp
Publication of SG11201706914TA publication Critical patent/SG11201706914TA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Bus Control (AREA)
SG11201706914TA 2015-03-06 2015-03-06 Memory device controlling method and memory device SG11201706914TA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2015/056707 WO2016143009A1 (en) 2015-03-06 2015-03-06 Memory device control method, and memory device

Publications (1)

Publication Number Publication Date
SG11201706914TA true SG11201706914TA (en) 2017-10-30

Family

ID=56361441

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201706914TA SG11201706914TA (en) 2015-03-06 2015-03-06 Memory device controlling method and memory device

Country Status (6)

Country Link
US (2) US10725909B2 (en)
JP (1) JP6545786B2 (en)
CN (1) CN107430548B (en)
SG (1) SG11201706914TA (en)
TW (1) TWI529523B (en)
WO (1) WO2016143009A1 (en)

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KR102593178B1 (en) * 2016-08-19 2023-10-25 에스케이하이닉스 주식회사 Memory device, memory system having the same, and operating method thereof
US10747463B2 (en) * 2017-08-04 2020-08-18 Micron Technology, Inc. Apparatuses and methods for accessing hybrid memory system
KR102447499B1 (en) * 2017-10-19 2022-09-26 삼성전자주식회사 Storage device and operating method of storage device
JP7074453B2 (en) * 2017-10-30 2022-05-24 キオクシア株式会社 Memory system and control method
JP7006166B2 (en) * 2017-11-17 2022-01-24 富士通株式会社 Data transfer device and data transfer method
JP2019128829A (en) * 2018-01-25 2019-08-01 東芝メモリ株式会社 Semiconductor storage and memory system
TWI697099B (en) * 2018-05-24 2020-06-21 香港商艾思科有限公司 Memory device and control method thereof, and method of controlling memory device
US10558594B2 (en) 2018-05-24 2020-02-11 Essencecore Limited Memory device, the control method of the memory device and the method for controlling the memory device
CN110770699A (en) * 2018-08-22 2020-02-07 深圳市大疆创新科技有限公司 Data instruction processing method, storage chip, storage system and movable platform
US10902896B2 (en) * 2018-08-22 2021-01-26 Realtek Semiconductor Corporation Memory circuit and method thereof
JP2020102286A (en) * 2018-12-21 2020-07-02 キオクシア株式会社 Semiconductor storage device
JP7413108B2 (en) 2020-03-23 2024-01-15 キオクシア株式会社 semiconductor equipment
JP2021149999A (en) 2020-03-23 2021-09-27 キオクシア株式会社 Semiconductor storage device
JP2021152779A (en) 2020-03-24 2021-09-30 キオクシア株式会社 Semiconductor memory device
US11893276B2 (en) 2020-05-21 2024-02-06 Micron Technology, Inc. Apparatuses and methods for data management in a memory device
US12019565B2 (en) * 2022-06-30 2024-06-25 Ampere Computing Llc Advanced initialization bus (AIB)

Family Cites Families (15)

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JP3853537B2 (en) * 1999-04-30 2006-12-06 株式会社日立製作所 Semiconductor memory file system
JP2004021713A (en) * 2002-06-18 2004-01-22 Mitsubishi Electric Corp Semiconductor storage device
US7409473B2 (en) * 2004-12-21 2008-08-05 Sandisk Corporation Off-chip data relocation
JP2007310680A (en) * 2006-05-18 2007-11-29 Matsushita Electric Ind Co Ltd Nonvolatile storage device and its data transfer method
US20110264851A1 (en) 2006-12-07 2011-10-27 Tae-Keun Jeon Memory system and data transmitting method thereof
JP2008192201A (en) * 2007-02-01 2008-08-21 Matsushita Electric Works Ltd Ddrsdram and data storage system
KR100886354B1 (en) * 2007-05-17 2009-03-03 삼성전자주식회사 System and method of communication using multi-phase clock signal
FR2953307B1 (en) * 2009-12-01 2011-12-16 Bull Sas MEMORY DIRECT ACCESS CONTROLLER FOR DIRECT TRANSFER OF DATA BETWEEN MEMORIES OF MULTIPLE PERIPHERAL DEVICES
US8930647B1 (en) * 2011-04-06 2015-01-06 P4tents1, LLC Multiple class memory systems
US9164679B2 (en) * 2011-04-06 2015-10-20 Patents1, Llc System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class
JP2012230621A (en) * 2011-04-27 2012-11-22 Sony Corp Memory apparatus, memory control apparatus, and memory control method
US8700834B2 (en) * 2011-09-06 2014-04-15 Western Digital Technologies, Inc. Systems and methods for an enhanced controller architecture in data storage systems
US9881657B2 (en) * 2012-05-08 2018-01-30 Marvell World Trade Ltd. Computer system and method of memory management
JP2015056105A (en) * 2013-09-13 2015-03-23 株式会社東芝 Nonvolatile semiconductor storage device
US9639478B2 (en) * 2014-01-17 2017-05-02 International Business Machines Corporation Controlling direct memory access page mappings

Also Published As

Publication number Publication date
JPWO2016143009A1 (en) 2017-11-30
US20200334146A1 (en) 2020-10-22
US20170357581A1 (en) 2017-12-14
TWI529523B (en) 2016-04-11
WO2016143009A1 (en) 2016-09-15
CN107430548B (en) 2021-02-05
CN107430548A (en) 2017-12-01
TW201633053A (en) 2016-09-16
JP6545786B2 (en) 2019-07-17
US11500770B2 (en) 2022-11-15
US10725909B2 (en) 2020-07-28

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