SG10201809987YA - Package structure and packaging process - Google Patents
Package structure and packaging processInfo
- Publication number
- SG10201809987YA SG10201809987YA SG10201809987YA SG10201809987YA SG10201809987YA SG 10201809987Y A SG10201809987Y A SG 10201809987YA SG 10201809987Y A SG10201809987Y A SG 10201809987YA SG 10201809987Y A SG10201809987Y A SG 10201809987YA SG 10201809987Y A SG10201809987Y A SG 10201809987YA
- Authority
- SG
- Singapore
- Prior art keywords
- package structure
- packaging process
- packaging
- package
- Prior art date
Links
- 238000012858 packaging process Methods 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
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- H01L23/142—Metallic substrates having insulating layers
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- H01L23/367—Cooling facilitated by shape of device
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
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- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG10201809987YA SG10201809987YA (en) | 2018-11-09 | 2018-11-09 | Package structure and packaging process |
US16/513,480 US20200152557A1 (en) | 2018-11-09 | 2019-07-16 | Package structure and packaging process |
CN201911088365.3A CN111180434A (en) | 2018-11-09 | 2019-11-08 | Packaging structure and packaging method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG10201809987YA SG10201809987YA (en) | 2018-11-09 | 2018-11-09 | Package structure and packaging process |
Publications (1)
Publication Number | Publication Date |
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SG10201809987YA true SG10201809987YA (en) | 2020-06-29 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201809987YA SG10201809987YA (en) | 2018-11-09 | 2018-11-09 | Package structure and packaging process |
Country Status (3)
Country | Link |
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US (1) | US20200152557A1 (en) |
CN (1) | CN111180434A (en) |
SG (1) | SG10201809987YA (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11665813B2 (en) * | 2020-08-14 | 2023-05-30 | Toyota Motor Engineering & Manufacturing North America, Inc. | Power electronics cooling assemblies and methods for making the same |
US11264299B1 (en) * | 2020-09-03 | 2022-03-01 | Northrop Grumman Systems Corporation | Direct write, high conductivity MMIC attach |
CN112687673B (en) * | 2020-12-28 | 2022-07-12 | 华进半导体封装先导技术研发中心有限公司 | Chip embedded slide structure with different thicknesses and preparation method thereof |
CN112736073B (en) * | 2020-12-28 | 2022-07-12 | 华进半导体封装先导技术研发中心有限公司 | Silicon-based optical computation heterogeneous integrated module |
CN115621234A (en) * | 2021-07-13 | 2023-01-17 | 华为技术有限公司 | Packaging structure and packaging system |
US20240234222A9 (en) * | 2022-10-24 | 2024-07-11 | Nxp B.V. | Semiconductor device with cavity carrier and method therefor |
Family Cites Families (13)
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---|---|---|---|---|
US7993972B2 (en) * | 2008-03-04 | 2011-08-09 | Stats Chippac, Ltd. | Wafer level die integration and method therefor |
US20080157340A1 (en) * | 2006-12-29 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | RF module package |
US20080157316A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Multi-chips package and method of forming the same |
US9831170B2 (en) * | 2011-12-30 | 2017-11-28 | Deca Technologies, Inc. | Fully molded miniaturized semiconductor module |
US9318411B2 (en) * | 2013-11-13 | 2016-04-19 | Brodge Semiconductor Corporation | Semiconductor package with package-on-package stacking capability and method of manufacturing the same |
SG10201400390YA (en) * | 2014-03-05 | 2015-10-29 | Delta Electronics Int L Singapore Pte Ltd | Package structure |
SG10201501021PA (en) * | 2015-02-10 | 2016-09-29 | Delta Electronics Int L Singapore Pte Ltd | Package structure |
SG10201504271YA (en) * | 2015-05-29 | 2016-12-29 | Delta Electronics Int’L Singapore Pte Ltd | Power module |
SG10201508520PA (en) * | 2015-10-14 | 2017-05-30 | Delta Electronics Int’L Singapore Pte Ltd | Power module |
KR101681031B1 (en) * | 2015-11-17 | 2016-12-01 | 주식회사 네패스 | Semiconductor package and method of manufacturing the same |
JP6669586B2 (en) * | 2016-05-26 | 2020-03-18 | 新光電気工業株式会社 | Semiconductor device and method of manufacturing semiconductor device |
US10490478B2 (en) * | 2016-07-12 | 2019-11-26 | Industrial Technology Research Institute | Chip packaging and composite system board |
US20180166356A1 (en) * | 2016-12-13 | 2018-06-14 | Globalfoundries Inc. | Fan-out circuit packaging with integrated lid |
-
2018
- 2018-11-09 SG SG10201809987YA patent/SG10201809987YA/en unknown
-
2019
- 2019-07-16 US US16/513,480 patent/US20200152557A1/en not_active Abandoned
- 2019-11-08 CN CN201911088365.3A patent/CN111180434A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
US20200152557A1 (en) | 2020-05-14 |
CN111180434A (en) | 2020-05-19 |
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