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SG10201805428XA - Three-dimensional semiconductor devices including vertical structures with varied spacing and methods of forming the same - Google Patents

Three-dimensional semiconductor devices including vertical structures with varied spacing and methods of forming the same

Info

Publication number
SG10201805428XA
SG10201805428XA SG10201805428XA SG10201805428XA SG10201805428XA SG 10201805428X A SG10201805428X A SG 10201805428XA SG 10201805428X A SG10201805428X A SG 10201805428XA SG 10201805428X A SG10201805428X A SG 10201805428XA SG 10201805428X A SG10201805428X A SG 10201805428XA
Authority
SG
Singapore
Prior art keywords
columns
dimensional semiconductor
vertical structures
methods
forming
Prior art date
Application number
SG10201805428XA
Inventor
Kim Sungjoong
Lim Joon-Sung
Hwang Sung-Min
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201805428XA publication Critical patent/SG10201805428XA/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H01L29/4234—
    • H01L29/42392—
    • H01L29/6681—
    • H01L29/78642—
    • H01L29/788—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A three-dimensional semiconductor device is disclosed. The device may include an electrode structure that can include a plurality of electrodes that are stacked on a substrate and extend in a first direction. Vertical structures can penetrate the electrode structure to provide a plurality of columns spaced apart from each other in a second direction crossing the first direction. The plurality of columns can include first and second edge columns located adjacent to respective opposite edges of the electrode structure, and the plurality of columns can include a center column located between the first and second edge columns. Distances between adjacent ones of the plurality of columns can decrease in a direction from the first and second edge columns toward the center column. FIG. 26
SG10201805428XA 2017-08-02 2018-06-25 Three-dimensional semiconductor devices including vertical structures with varied spacing and methods of forming the same SG10201805428XA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020170098204A KR102414511B1 (en) 2017-08-02 2017-08-02 Three-dimensional semiconductor devices

Publications (1)

Publication Number Publication Date
SG10201805428XA true SG10201805428XA (en) 2019-03-28

Family

ID=65230394

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201805428XA SG10201805428XA (en) 2017-08-02 2018-06-25 Three-dimensional semiconductor devices including vertical structures with varied spacing and methods of forming the same

Country Status (4)

Country Link
US (2) US10411032B2 (en)
KR (1) KR102414511B1 (en)
CN (1) CN109390344A (en)
SG (1) SG10201805428XA (en)

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US11271002B2 (en) * 2019-04-12 2022-03-08 Micron Technology, Inc. Methods used in forming a memory array comprising strings of memory cells
TWI718566B (en) * 2019-06-21 2021-02-11 旺宏電子股份有限公司 3d memory array device and method for multiply-accumulate
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KR20210072276A (en) * 2019-12-09 2021-06-17 에스케이하이닉스 주식회사 Semiconductor memory device and manufacturing method thereof
KR20220077740A (en) * 2020-12-02 2022-06-09 삼성전자주식회사 Semiconductor device and electronica system including the same
CN112768489B (en) * 2021-02-04 2021-11-09 长江先进存储产业创新中心有限责任公司 Phase change memory and manufacturing method thereof
JP2022120425A (en) * 2021-02-05 2022-08-18 キオクシア株式会社 semiconductor storage device

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US20120208347A1 (en) * 2011-02-11 2012-08-16 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory devices and methods of fabricating the same
KR101936752B1 (en) * 2012-05-29 2019-01-10 삼성전자주식회사 Semiconductor device
KR102002802B1 (en) 2012-09-05 2019-07-23 삼성전자주식회사 Semiconductor device
KR102108879B1 (en) * 2013-03-14 2020-05-11 삼성전자주식회사 Vertical memory devices and methods of manufacturing the same
US9082826B2 (en) 2013-05-24 2015-07-14 Lam Research Corporation Methods and apparatuses for void-free tungsten fill in three-dimensional semiconductor features
CN104659207B (en) * 2013-11-19 2019-04-26 三星电子株式会社 Storage device
KR102128465B1 (en) 2014-01-03 2020-07-09 삼성전자주식회사 Vertical structure non-volatile memory device
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Also Published As

Publication number Publication date
US10886296B2 (en) 2021-01-05
KR102414511B1 (en) 2022-06-30
US20190393243A1 (en) 2019-12-26
CN109390344A (en) 2019-02-26
US10411032B2 (en) 2019-09-10
US20190043881A1 (en) 2019-02-07
KR20190014616A (en) 2019-02-13

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