SG10201500132YA - Methods of Patterning Line-Type Features using a Multiple Patterning Process that Enables the use of Tighter Contact Enclosure Spacing Rules - Google Patents
Methods of Patterning Line-Type Features using a Multiple Patterning Process that Enables the use of Tighter Contact Enclosure Spacing RulesInfo
- Publication number
- SG10201500132YA SG10201500132YA SG10201500132YA SG10201500132YA SG10201500132YA SG 10201500132Y A SG10201500132Y A SG 10201500132YA SG 10201500132Y A SG10201500132Y A SG 10201500132YA SG 10201500132Y A SG10201500132Y A SG 10201500132YA SG 10201500132Y A SG10201500132Y A SG 10201500132YA
- Authority
- SG
- Singapore
- Prior art keywords
- enables
- methods
- type features
- patterning
- spacing rules
- Prior art date
Links
- 238000000034 method Methods 0.000 title 2
- 238000000059 patterning Methods 0.000 title 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0278—Röntgenlithographic or X-ray lithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/186,396 US9287131B2 (en) | 2014-02-21 | 2014-02-21 | Methods of patterning line-type features using a multiple patterning process that enables the use of tighter contact enclosure spacing rules |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201500132YA true SG10201500132YA (en) | 2015-09-29 |
Family
ID=53782653
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201500132YA SG10201500132YA (en) | 2014-02-21 | 2015-01-08 | Methods of Patterning Line-Type Features using a Multiple Patterning Process that Enables the use of Tighter Contact Enclosure Spacing Rules |
Country Status (5)
Country | Link |
---|---|
US (1) | US9287131B2 (en) |
CN (1) | CN104867816B (en) |
DE (1) | DE102015200107B4 (en) |
SG (1) | SG10201500132YA (en) |
TW (1) | TWI581058B (en) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6366412B2 (en) * | 2014-08-01 | 2018-08-01 | キヤノン株式会社 | Pattern formation method |
US9412655B1 (en) * | 2015-01-29 | 2016-08-09 | Globalfoundries Inc. | Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines |
US9412649B1 (en) * | 2015-02-13 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating semiconductor device |
CN108701588B (en) * | 2016-01-29 | 2023-03-14 | 东京毅力科创株式会社 | Method and system for forming memory fin patterns |
US10109582B2 (en) | 2016-04-19 | 2018-10-23 | Taiwan Semiconductor Manufacturing Company Limited | Advanced metal connection with metal cut |
US9991156B2 (en) | 2016-06-03 | 2018-06-05 | International Business Machines Corporation | Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs |
US10083842B2 (en) * | 2016-11-16 | 2018-09-25 | Tokyo Electron Limited | Methods of sub-resolution substrate patterning |
US10275562B2 (en) | 2016-11-29 | 2019-04-30 | Taiwan Semiconductor Manufacturing Company Limited | Method of decomposing a layout for multiple-patterning lithography |
US9812324B1 (en) * | 2017-01-13 | 2017-11-07 | Globalfoundries Inc. | Methods to control fin tip placement |
US10147606B2 (en) * | 2017-03-07 | 2018-12-04 | Micron Technology, Inc. | Methods of forming semiconductor device structures including linear structures substantially aligned with other structures |
US11901190B2 (en) * | 2017-11-30 | 2024-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of patterning |
US10818505B2 (en) | 2018-08-15 | 2020-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned double patterning process and semiconductor structure formed using thereof |
CN113130303B (en) * | 2019-12-30 | 2023-10-17 | 中芯国际集成电路制造(上海)有限公司 | Mask and triple patterning method |
US20210265166A1 (en) * | 2020-02-20 | 2021-08-26 | International Business Machines Corporation | Via-via spacing reduction without additional cut mask |
CN113078057B (en) * | 2021-03-23 | 2022-09-23 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
US11710642B2 (en) | 2021-03-23 | 2023-07-25 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
CN118712048A (en) * | 2024-08-30 | 2024-09-27 | 全芯智造技术有限公司 | Multiple patterning method, electronic device, and computer-readable storage medium |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU2001290937A1 (en) * | 2000-09-13 | 2002-04-02 | Massachusetts Institute Of Technology | Method of design and fabrication of integrated circuits using regular arrays and gratings |
US6632576B2 (en) * | 2000-12-30 | 2003-10-14 | Intel Corporation | Optical assist feature for two-mask exposure lithography |
US6602642B2 (en) * | 2001-08-29 | 2003-08-05 | Taiwan Semiconductor Manufacturing Co., Ltd | Optical proximity correction verification mask |
US7673270B1 (en) * | 2007-03-13 | 2010-03-02 | Xilinx, Inc. | Method and apparatus for compensating an integrated circuit layout for mechanical stress effects |
US7861196B2 (en) * | 2008-01-31 | 2010-12-28 | Cadence Design Systems, Inc. | System and method for multi-exposure pattern decomposition |
KR100994715B1 (en) * | 2008-12-31 | 2010-11-17 | 주식회사 하이닉스반도체 | Method for forming fine pattern using quadruple patterning in semiconductor device |
US8355807B2 (en) * | 2010-01-22 | 2013-01-15 | Synopsys, Inc. | Method and apparatus for using aerial image sensitivity to model mask errors |
JP5254381B2 (en) * | 2011-02-23 | 2013-08-07 | 株式会社東芝 | Pattern formation method |
US9236267B2 (en) * | 2012-02-09 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cut-mask patterning process for fin-like field effect transistor (FinFET) device |
US8802574B2 (en) * | 2012-03-13 | 2014-08-12 | Globalfoundries Inc. | Methods of making jogged layout routings double patterning compliant |
TWI464795B (en) * | 2012-07-13 | 2014-12-11 | Apone Technology Ltd | Masking method for locally treating surface |
-
2014
- 2014-02-21 US US14/186,396 patent/US9287131B2/en active Active
- 2014-12-19 TW TW103144460A patent/TWI581058B/en not_active IP Right Cessation
-
2015
- 2015-01-08 DE DE102015200107.5A patent/DE102015200107B4/en not_active Expired - Fee Related
- 2015-01-08 SG SG10201500132YA patent/SG10201500132YA/en unknown
- 2015-02-16 CN CN201510085028.4A patent/CN104867816B/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US9287131B2 (en) | 2016-03-15 |
TWI581058B (en) | 2017-05-01 |
DE102015200107B4 (en) | 2020-06-10 |
TW201539115A (en) | 2015-10-16 |
DE102015200107A1 (en) | 2015-08-27 |
CN104867816A (en) | 2015-08-26 |
CN104867816B (en) | 2018-07-13 |
US20150243515A1 (en) | 2015-08-27 |
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