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SG10201500132YA - Methods of Patterning Line-Type Features using a Multiple Patterning Process that Enables the use of Tighter Contact Enclosure Spacing Rules - Google Patents

Methods of Patterning Line-Type Features using a Multiple Patterning Process that Enables the use of Tighter Contact Enclosure Spacing Rules

Info

Publication number
SG10201500132YA
SG10201500132YA SG10201500132YA SG10201500132YA SG10201500132YA SG 10201500132Y A SG10201500132Y A SG 10201500132YA SG 10201500132Y A SG10201500132Y A SG 10201500132YA SG 10201500132Y A SG10201500132Y A SG 10201500132YA SG 10201500132Y A SG10201500132Y A SG 10201500132YA
Authority
SG
Singapore
Prior art keywords
enables
methods
type features
patterning
spacing rules
Prior art date
Application number
SG10201500132YA
Inventor
Yuan Lei
Kye Jongwook
J Levinson Harry
Original Assignee
Globalfoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globalfoundries Inc filed Critical Globalfoundries Inc
Publication of SG10201500132YA publication Critical patent/SG10201500132YA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088Process specially adapted to improve the resolution of the mask
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0278Röntgenlithographic or X-ray lithographic processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
SG10201500132YA 2014-02-21 2015-01-08 Methods of Patterning Line-Type Features using a Multiple Patterning Process that Enables the use of Tighter Contact Enclosure Spacing Rules SG10201500132YA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/186,396 US9287131B2 (en) 2014-02-21 2014-02-21 Methods of patterning line-type features using a multiple patterning process that enables the use of tighter contact enclosure spacing rules

Publications (1)

Publication Number Publication Date
SG10201500132YA true SG10201500132YA (en) 2015-09-29

Family

ID=53782653

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201500132YA SG10201500132YA (en) 2014-02-21 2015-01-08 Methods of Patterning Line-Type Features using a Multiple Patterning Process that Enables the use of Tighter Contact Enclosure Spacing Rules

Country Status (5)

Country Link
US (1) US9287131B2 (en)
CN (1) CN104867816B (en)
DE (1) DE102015200107B4 (en)
SG (1) SG10201500132YA (en)
TW (1) TWI581058B (en)

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JP6366412B2 (en) * 2014-08-01 2018-08-01 キヤノン株式会社 Pattern formation method
US9412655B1 (en) * 2015-01-29 2016-08-09 Globalfoundries Inc. Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines
US9412649B1 (en) * 2015-02-13 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating semiconductor device
CN108701588B (en) * 2016-01-29 2023-03-14 东京毅力科创株式会社 Method and system for forming memory fin patterns
US10109582B2 (en) 2016-04-19 2018-10-23 Taiwan Semiconductor Manufacturing Company Limited Advanced metal connection with metal cut
US9991156B2 (en) 2016-06-03 2018-06-05 International Business Machines Corporation Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs
US10083842B2 (en) * 2016-11-16 2018-09-25 Tokyo Electron Limited Methods of sub-resolution substrate patterning
US10275562B2 (en) 2016-11-29 2019-04-30 Taiwan Semiconductor Manufacturing Company Limited Method of decomposing a layout for multiple-patterning lithography
US9812324B1 (en) * 2017-01-13 2017-11-07 Globalfoundries Inc. Methods to control fin tip placement
US10147606B2 (en) * 2017-03-07 2018-12-04 Micron Technology, Inc. Methods of forming semiconductor device structures including linear structures substantially aligned with other structures
US11901190B2 (en) * 2017-11-30 2024-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of patterning
US10818505B2 (en) 2018-08-15 2020-10-27 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned double patterning process and semiconductor structure formed using thereof
CN113130303B (en) * 2019-12-30 2023-10-17 中芯国际集成电路制造(上海)有限公司 Mask and triple patterning method
US20210265166A1 (en) * 2020-02-20 2021-08-26 International Business Machines Corporation Via-via spacing reduction without additional cut mask
CN113078057B (en) * 2021-03-23 2022-09-23 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof
US11710642B2 (en) 2021-03-23 2023-07-25 Changxin Memory Technologies, Inc. Semiconductor structure and manufacturing method thereof
CN118712048A (en) * 2024-08-30 2024-09-27 全芯智造技术有限公司 Multiple patterning method, electronic device, and computer-readable storage medium

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AU2001290937A1 (en) * 2000-09-13 2002-04-02 Massachusetts Institute Of Technology Method of design and fabrication of integrated circuits using regular arrays and gratings
US6632576B2 (en) * 2000-12-30 2003-10-14 Intel Corporation Optical assist feature for two-mask exposure lithography
US6602642B2 (en) * 2001-08-29 2003-08-05 Taiwan Semiconductor Manufacturing Co., Ltd Optical proximity correction verification mask
US7673270B1 (en) * 2007-03-13 2010-03-02 Xilinx, Inc. Method and apparatus for compensating an integrated circuit layout for mechanical stress effects
US7861196B2 (en) * 2008-01-31 2010-12-28 Cadence Design Systems, Inc. System and method for multi-exposure pattern decomposition
KR100994715B1 (en) * 2008-12-31 2010-11-17 주식회사 하이닉스반도체 Method for forming fine pattern using quadruple patterning in semiconductor device
US8355807B2 (en) * 2010-01-22 2013-01-15 Synopsys, Inc. Method and apparatus for using aerial image sensitivity to model mask errors
JP5254381B2 (en) * 2011-02-23 2013-08-07 株式会社東芝 Pattern formation method
US9236267B2 (en) * 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8802574B2 (en) * 2012-03-13 2014-08-12 Globalfoundries Inc. Methods of making jogged layout routings double patterning compliant
TWI464795B (en) * 2012-07-13 2014-12-11 Apone Technology Ltd Masking method for locally treating surface

Also Published As

Publication number Publication date
US9287131B2 (en) 2016-03-15
TWI581058B (en) 2017-05-01
DE102015200107B4 (en) 2020-06-10
TW201539115A (en) 2015-10-16
DE102015200107A1 (en) 2015-08-27
CN104867816A (en) 2015-08-26
CN104867816B (en) 2018-07-13
US20150243515A1 (en) 2015-08-27

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