RU2713868C1 - Apparatus for solving task of selecting technical means of complex system - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to computer engineering. Technical result is achieved due to the device for solving the task of selecting technical means of a complex system, comprising a clock pulse generator, a first AND element, a group of n counters, a group of n first registers, a group of n first comparison circuits, a group n of second AND elements, a group of n third elements AND, a group n of second registers, a group n of third registers, a matrix n*m of fourth registers, a group of n first multiplier units, a matrix n*m of second multiplier units, a first adder, a group of n second adders, a group of n second comparison circuits, a fourth AND element, a group n fifth registers, sixth register, fifth AND element, a group of sixth AND elements, a third comparison circuit, wherein it further includes a group of n seventh registers, a group of n units for raising to the power of an integer, a group of eight eighth registers, a delay element.

EFFECT: technical result consists in possibility of determining the probability of a set of equipment when selecting the optimum composition and number of equipment to perform a certain amount of work.

1 cl, 1 dwg

Description

The invention relates to the field of computer technology and can be used to obtain the optimal solution to the problem of choosing technical means when choosing the composition and number of technical means to perform a certain amount of work.

A device for solving the problem of solving the problem of choosing the technical means of a complex system [1], which allows you to get the exact solution to the problem of choosing the technical means of a system.

The disadvantage of this device is the inability to determine the probability of a set of technical means when choosing the optimal composition and number of technical means to perform a certain amount of work.

The objective of the invention is to create a device that determines the probability of a set of technical means when choosing the optimal composition and number of technical means to perform a certain amount of work.

This solution is achieved by the fact that in a device containing a clock pulse generator (GTI) 1, the first element And 2, a group of n counters 3 _i (i = 1 ... n, where n is the number of possible different types of hardware of the complex), group n first registers 4 ₁ ... 4 _n , group n of the first comparison schemes 5 ₁ ... 5 _n , group n of the second elements AND 6 ₁ ... 6 _n , group n of the third elements AND 7 ₁ ... 7 _n , group n of the second registers 8 ₁ ... 8 _n , the group n of third registers 9 ₁ ... 9 _n , the matrix n * m of the fourth registers 10 ₁₁ ... 10 _nm , the group n of the first blocks of multiplication 11 ₁ ... 11 _n , the matrix n * m of the second blocks of multiplication 12 ₁₁ ... 12 _nm , first adder 13, group n of second adders 14 ₁ ... 14 _n , group m of second comparison schemes 15 ₁ ... l5 _n , fourth element And 16, group m of fifth registers 17 ₁ ... 17 _n , sixth register 18, fifth element And 19, group of the sixth elements And 20, the third comparison circuit 21, the output of the GTI 1 is connected to the first input of the first element And 2, the output of which is connected to the first input of the counter 3 ₁ , the overflow output of the counter 3 _i (i = 1 ... n-1) is connected to the first input counter 3 _{i + 1} , the information output of the counter 3 _i (i = 1 ... n) is connected to the first input of the third elements AND 7 _i , to the first input of the first circuit comparing 5 _i (i = 1 ... n), to the first inputs of the same second multiplication blocks 12 _ij (i = 1 ... n, j = 1 ... m), to the first input of the first multiplication block 11 _i (i = 1 ... n), the second input of which is connected to the output of the third register 9 _i (i = 1 ... n), the output of the first block of multiplication 11 _{i is} connected to the same input of the first adder 13, the output of which is connected to the first input of the sixth element And 20 and to the first input of the third comparison circuit 21 the second input of which is connected to the output of the sixth register 18, and the output is connected to the first input of the fifth element And 19, the output of which is connected to the second input of the sixth element And 20 and to the second inputs of the third elements And 7 _i (i = 1 ... n), the output of each of which is connected to the input of the second register And 8 _i (i = 1 ... n), the output of which is the output 27 _i (i = 1 ... n) of the device, the output of the sixth element And 20 is connected to the input of the sixth register 18, the overflow output of the counter 3 _{n is} connected to the second input of the first element And 2, the outputs of the fifth registers 17 ₁ ... 17 _{m are} connected to the first inputs of the same second circuits comparison 15 _j (j = 1 ... m), the outputs of every fourth register 10 _ij (i = 1 ... n, j = 1 ... m) are connected to the second inputs of the same name of the second multiplication blocks 12 _ij , the output of each second multiplication block 12 _{ij is} connected to the same input of the adder 14 _j (j = 1 ... n), the output of which is connected to the second input of the second comparison circuit 15 _j (j = 1 ... n), the output of the second comparison circuit 15 _j (j = 1 ... n) is connected to the same input of the fourth element And 16, the output of which is connected to the second input of the fifth element And 19, the output of the first register 4 _i (i = 1 ... n) is connected to the first input of the first comparison circuit 5 _{i (i} = 1 ... n) and to the first input of the second group of aND gates 6 _{i (i} = 1 ... n), the second input of which is connected to the output ervoy circuit comparison 5 _{i (i} = 1 ... n), and an output connected to the second input of the homonymous counters 3 _{i (i} = 1 ... n), including the group of n seventh registers 22 ₁ ... 22 _n, group of n blocks exponentiation of an integer 23 ₁ ... 23 _n , group of eighth registers 24 ₁ ... 24 _n , delay element 25, counter overflow output 3 _{n is} connected to the input of delay element 25 and to the control inputs of the raising units to the power of an integer number 23 ₁ ... 23 _n , the first inputs of which connected to the outputs of the same second registers 8 ₁ ... 8 _n , the second inputs to the outputs of the same seventh registers 22 ₁ ... 22 _n , and the output is to the first input of the eighth registers 24 ₁ ... 24 _n , the output of the delay element 25 is connected to the control inputs of the eighth registers 24 ₁ ... 24 _n and is the output 29 of the device.

A search in the well-known scientific and technical literature did not reveal the presence of such technical solutions.

The invention is illustrated by the drawing, where the drawing (Fig. 1) shows a clock pulse generator (GTI) 1, element And 2, a group of n counters 3 ₁ ... 3 _n , a group of n registers 4 ₁ ... 4 _n , a group of n comparison circuits 5 ₁ ... 5 _n , group of n elements AND 6 ₁ ... 6 _n , group of n elements AND 7 ₁ ... 7 _n , group of n registers 8 ₁ ... 8 _n , group of n registers 9 ₁ ... 9 _n , matrix of n * m registers 10 ₁₁ ... 10 _nm group n of multiplication blocks 11 ₁ ... 11 _n , matrix n * m of multiplication blocks 12 ₁₁ ... 12 _nm , adder 13, group n of adders 14 ₁ ... 14 _n , group m of comparison circuits 15 ₁ ... 15 _n , AND element 16 , group n of registers 17 ₁ ... 17 _n , register 18, element AND 19, a group of elements And 20, a comparison circuit 21, a group of n registers 22 ₁ ... 22 _n , a group of n blocks raising to the power of an integer 23 ₁ ... 23 _n , a group of n registers 24 ₁ ... 24 _n , a delay element 25, the input of the device 26 , the outputs of the device 27 ₁ ... 27 _n , the outputs of the device 28 ₁ ... 28 _n and 29 together with the connections.

The device operates as follows.

In the initial state, all counters 3 _i (i = 1 ... n) are set to zero. The maximum code is entered in the register 18, for example, the code with units in all bits of the register 18.

The registers 10 _ij (i = 1 ... n, j = 1 ... m) are entered codes of the j-th characteristics of the i-th technical means. On the registers 22 _i (i = 1 ... n) are entered probability codes p _i uptime of the i-th technical means. On the registers 4 _i (i = 1 ... n) are entered the codes of the numbers of the minimum values of the number of complex hardware in the system. On the registers 17 _j (j = 1 ... m), codes of permissible total values of the j-th characteristics of the desired number of hardware are entered. On the registers 9 _i (i = 1 ... n) are entered the codes of "cost" of a unit of hardware of the complex. Installation inputs in the figure are not shown due to bulkiness.

The operation of the device begins after the start signal is supplied to the input 26 of the device, after which the pulses from the output of the GTI 1 begin to flow through the open element And 2 to the input of the counter 3 ₁ , since the zero signal from the overflow output of the counter 3 _n goes to the inverse input of the And 2 element.

The output of counter 3 _i (i = 1 ... (n-1)) overflow is connected to the counter input of the counter 3 _{i + 1} . From the output of the counter 3 _i (i = 1 ... n), the code goes to the input of the multiplication block of the same name 11 _i (i = 1 ... n), to the input of the comparison circuit 5 _i (i = 1 ... n), to the input of the group of elements AND 7 _i and to the inputs of the multiplication blocks 12 _ij (i = 1 ... n, j = 1 ... m). The second inputs of the multiplication block 11 _i (i = 1 ... n) and the multiplication block 12 _ij (i = 1 ... n, j = 1 ... m) receive codes from the outputs of the registers 9 _i (i = 1 ... n) and the registers 10 _ij (i = 1 ... n, j = 1 ... m).

The code from the output of the multiplication block 12 _ij (i = 1 ... m, j = 1 ... n) is supplied to the inputs of the same group of adders 14 _j , from the output of which the codes go to the first inputs of the same comparison schemes 15 _j . The second inputs of the comparison circuits 15 _j receive codes from the outputs of the registers 17 _j . At the output of the comparison circuit 15 _j , a single signal appears if the code from the output of the register 17 _{j is} not less than the code from the output of the adder 14 _j .

Next, a single signal from the output of the comparison circuit 15 _j goes to the input of the same element And 16, the output of which the signal goes to the first input of the And 19 element.

At the same time, the result code from the output of the multiplication unit 11 _i (i = 1 ... n) is fed to the input of the adder 13 of the same name, from the output of which the total code of the “cost” of the set of hardware is supplied to the second input of the group of elements 20 and to the first input of the second comparison circuit , the second input of which receives the code from the output of the register 18 with the value of the current "cost" of a set of hardware.

A single signal at the output of the comparison circuit 21 appears only if the “cost” code of the set of hardware at the output of the adder 13 is less than the “cost” code at the output of the register 18 with the value of the current “cost” of the set of hardware. A single signal from the output of the comparison circuit 21 is fed to the second input of the element And 19.

и на первый вход группы элементов И 20, на второй вход которой поступает код с выхода сумматора 13 для перезаписи его в регистр 18, куда записывается код минимальной «стоимости» набора технических средств.In the case of all single input signals at the inputs of the element And 19 from its output, a single signal is supplied to the first inputs of the group of elements And 7 _i

and to the first input of the group of elements And 20, the second input of which receives the code from the output of the adder 13 to overwrite it in register 18, where the code of the minimum "cost" of the set of hardware is written.

Through open groups of elements And 7 _{i, the} codes from the outputs of the 3 _i counters go to the inputs of the same registers 8 _i , which record the current values of the number of items of the i-th type of technical equipment.

поступают на счетные входы счетчиков 3_i+1. Сигнал с выхода переполнения счетчика 3_n поступает на инверсный вход элемента И 2, в результате чего прекращается подача импульсов с выхода ГТИ 1.Signals from overflow outputs 3 _i

arrive at the counting inputs of the counters 3 _{i + 1} . The signal from the counter overflow output 3 _n goes to the inverse input of the And 2 element, as a result of which the supply of pulses from the output of the GTI 1 stops.

Signal Frequency GTI 1 is selected considering the sequence reliable switching element AND 2, counters 3 ₁ ... 3 _n, circuits comparing 5 ₁ ... 5 _n, AND gates 6 ₁ ... 6 _n, groups of n AND gates 7 ₁ ... 7 _n, multiplying units 11 ₁ ... 11 _n , adder 13, groups of n adders 14 ₁ ... 14 _n , comparison schemes 151 ... 15 _m , element 16, element 19, elements 20, comparison schemes 21.

значения (1-p_i), а на вторые входы - с выходов регистров 8_i число используемых в системе i-ых технических средств.The signal from the overflow output of the last counter 3 _n also goes to the input of the delay element 25 and to the control inputs of the raising blocks to the power of an integer 23 ₁ ... 23 _n , the first inputs of which receive codes from the inverse outputs of the registers 22 _i

values (1-p _i ), and to the second inputs - from the outputs of the registers 8 _{i the} number of i-th technical means used in the system.

The delay element 25 delays the signal for the period of reliable operation of the blocks raising to the power of an integer 23 ₁ ... 23 _n , after which the contents of the blocks of raising to the power of an integer 23 ₁ ... 23 _n are rewritten to the corresponding registers 24 ₁ ... 24 _n , from whose inverse outputs at the outputs 28 ₁ ... 28 _{n of the} device, the values are taken (1- (1-p _i ) ⁱ ) of the probabilities of failure-free operation of all i-th technical means.

The result of the operation of the device are:

, на которых фиксируются коды чисел набора технических средств i-го типа

и могут быть сняты с выходов 27₁

устройства;codes on registers 8 _i

on which codes of numbers of a set of hardware of the i-th type are fixed

and can be removed from outputs 27 ₁

devices

values of P _i = (1- (1-p _i ) ⁱ ) uptime of the i-th technical equipment at the outputs 28 ₁ ... 28 _{n of the} device;

the value of the minimum (optimal) “cost” of the set of technical equipment in the register 18, as well as the signal of the end of operation of the 29 devices.

Used sources

1. RU N 2413287, class G06F 15/20.

2. RU N 2656543, cl. G06F 15/20.

Claims (1)

A device for solving the problem of choosing the hardware of a complex system, containing a clock generator (GTI) 1, the first element And 2, a group of n counters 3 _i (i = 1 ... n, where n is the number of possible different types of hardware of the complex), group n first registers 4 ₁ ... 4 _n , group n of the first comparison schemes 5 ₁ ... 5 _n , group n of the second elements AND 6 ₁ ... 6 _n , group n of the third elements AND 7 ₁ ... 7 _n , group n of the second registers 8 ₁ ... 8 _n , group n of third registers 9 ₁ ... 9 _n , matrix n * m of fourth registers 10 ₁₁ ... 10 _nm , group n of first blocks of multiplication 11 ₁ ... 11 _n , matrix n * m sec multiplication blocks 12 ₁₁ ... 12 _nm , the first adder 13, the group n of the second adders 14 ₁ ... 14 _n , the group n of the second comparison schemes 15 ₁ ... 15 _n , the fourth element And 16, the group n of the fifth registers 17 ₁ ... 17 _n , the sixth register 18, fifth element And 19, a group of six elements And 20, the third comparison circuit 21, the output of the GTI 1 is connected to the first input of the first element And 2, the output of which is connected to the first input of the counter 3 ₁ , the output of the overflow counter 3 _i (i = 1 ... n-1) is connected to the first input of the counter 3 _{i + 1} , the information output of the counter 3 _i (i = 1 ... n) is connected to the first input of the third elements And 7 _i , to the first input of the first comparison circuit 5 _i (i = 1 ... n), to the first inputs of the same second multiplication blocks 12 _ij (i = 1 ... n, j = 1 ... m), to the first input of the first multiplication block 11 _i (i = 1 ... n), the second input of which is connected to the output of the third register 9 _i (i = 1 ... n), the output of the first multiplication block 11 _{i is} connected to the same input of the first adder 13, the output of which is connected to the first input of the sixth element And 20 and to the first the input of the third comparison circuit 21, the second input of which is connected to the output of the sixth register 18, and the output is connected to the first input of the fifth element And 1 9, the output of which is connected to the second input of the sixth element And 20 and to the second inputs of the third elements And 7 _i (i = 1 ... n), the output of each of which is connected to the input of the second register And 8 _i (i = 1 ... n), the output which is the output 27 _i (i = 1 ... n) of the device, the output of the sixth element And 20 is connected to the input of the sixth register 18, the overflow output of the counter 3 _{n is} connected to the second input of the first element And 2, the outputs of the fifth registers 17 ₁ ... 17 _{n are} connected to first inputs of like second comparing circuits 15 _{j (j} = 1 ... n), the outputs of each of the fourth register 10 _ij (i = 1 ... n, j = 1 ... n) CONNECTION Nena to second inputs of like second blocks multiplication 12 _ij, the output of each second multiplying block 12 _ij is connected with the same input of the adder 14 _{j (j} = 1 ... n), the output of which is connected to the second input of the second comparison circuit 15 _{j (j} = 1 ... n ), the output of the second comparison circuit 15 _j (j = 1 ... n) is connected to the same input of the fourth element And 16, the output of which is connected to the second input of the fifth element And 19, the output of the first register 4 _i (i = 1 ... n) is connected to the first the input of the first comparison circuit 5 _i (i = 1 ... n) and to the first input of the second group of elements And 6 _i (i = 1 ... n), the second input to otoroy connected to the output of the first comparison circuit 5 _i (i = 1 ... n), and the output is connected to the second input of the counter of the same name 3 _i (i = 1 ... n), characterized in that it also includes a group of n seventh registers 22 ₁ ... 22 _n , group n of exponentiation blocks 23 ₁ ... 23 _n , group n of eighth registers 24 ₁ ... 24 _n , delay element 25, counter overflow output 3 _n connected to the input of delay element 25 and to the control inputs of exponentiation blocks integer 23 ₁ ... 23 _n , the first inputs of which are connected to the outputs of the same second registers 8 ₁ ... 8 _n , the second inputs to the outputs of the seventh registers of the same name 22 ₁ ... 22 _n , and the output to the first input of the eighth registers 24 ₁ ... 24 _n , the output of the delay element 25 is connected to the control inputs of the eighth registers 24 ₁ ... 24 _n and is the output 29 of the device.

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