RU2779569C1 - Logic circuit - Google Patents

Abstract

FIELD: computing technology.

SUBSTANCE: invention relates to a method for operation of a logic circuit, a set of logic circuits for the association with a replaceable component of a printing apparatus, and a replaceable cartridge of a printing apparatus for the connection to the printing apparatus. In the method, in response to a first command sent to the address of the logic circuit associated with a replaceable component of a printing apparatus via a serial data bus, wherein the first command indicates a first period of time, said logic circuit is used to generate a low-voltage condition on the serial data bus for a first duration based on the first period of time; and, in response to another first command sent to the same address of the same logic circuit via the serial data bus at a different point of time, wherein said other first command indicates a second period of time other than the first period of time, said logic circuit is used to generate a low-voltage condition on the serial data bus for a different duration, respectively, based on the second period of time.

EFFECT: possibility of controlling the voltage on a serial bus.

41 cl, 11 dwg

Description

BACKGROUND OF THE INVENTION

[0001] Serial data bus protocols, such as the Inter-Integrated Circuit Protocol (I ² C or I2C, and this designation is adopted here) and the Serial Peripheral Interface (SPI) protocol, allow at least one 'master' integrated circuit (IC) to communicate with at least one 'slave' IC, for example via a bus. I2C and other communication protocols transmit data according to the clock period. For example, a voltage signal may be generated, where a voltage value is associated with data. For example, a voltage value above x volts may indicate a logic "1", while a voltage value below x volts may indicate a logic "0", where x is a predetermined numerical value. By generating the proper voltage in each of several clock cycles, data can be transferred over a bus or other communication line.

[0002] Some 2D and 3D printing systems include one or more replaceable components of the printing device, such as print media containers (e.g., inkjet cartridges, toner cartridges, ink tanks, building material sources, etc.), inkjet print head assemblies, etc. In some examples, the logic circuit associated with the replaceable component(s) of the print device communicates with the logic circuit of the print device in which they are installed, for example, by transmitting information, for example, their identifier, capabilities, status, etc.

[0003] In some examples, these transmissions use I2C transmissions. In such examples, the master IC may generally be provided as part of the print device (which may be referred to as the 'master'), and the replaceable print device component will contain the 'slave' IC, although this is not true in all examples. There may be many slave ICs connected to the I2C link (eg containers of different print agent colors). The slave(s) IC may/may contain logic for performing data operations prior to responding to requests from the printing system logic.

[0004] In some examples, this may be intended to detect the physical position of slave devices that are attached along a serial bus. For example, you can assume that devices, such as removable components of the printer, occupy some specified physical position in the printer. For example, in a printer with ink supplies connected to a serial bus, there may be an expected position for, for example, a black cartridge, a yellow cartridge, a cyan cartridge, and a magenta cartridge, each of which may have a specific address according to the communication protocol. By detecting whether ink cartridges of a particular color have been incorrectly installed or swapped, printing with incorrect or intended colors can be prevented. The previous patent disclosure is US Patent Application Publication Number US 2011/0029705.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Non-limiting examples will be described below with reference to the accompanying drawings, in which:

[0006] FIG. 1 shows an example of a printing system;

[0007] FIG. 2 is an example of a replaceable component of a printing device;

[0008] FIG. 3 is an example of a printing device;

[0009] FIG. 4 is an example of a method for operating a logic circuit associated with a replaceable component of a printing device;

[0010] FIG. 4A is another example of a manner in which logic circuitry associated with a replaceable printer component operates;

[0011] FIG. 5 is a schematic example of a print device logic diagram and the logic circuit associated with replaceable print device components connected to a serial bus;

[0012] FIG. 6 is an example of another way of operating a logic circuit associated with a replaceable component of a printing device;

[0013] FIG. 7 is an example of a set of logic circuits;

[0014] FIG. 7A is another example of the operation of logic circuitry associated with a replaceable printer component;

[0015] FIG. 7B is another example of a set of logic circuits; and

[0016] FIG. 8 is an example of a replaceable printer component containing a set of logic circuits.

DETAILED DESCRIPTION

[0017] Some examples of I2C transmission applications are described herein in the context of a print device. However, not all examples are limited to such uses, and at least some of the principles set forth herein may be used in other contexts.

[0018] In some examples, logic in a printer may receive information from logic associated with a removable printer component via a communications interface and/or may send commands to a removable printer component. Exemplary printing devices include a 2D imaging device and a 3D additive manufacturing device, such as inkjet printers, dry toner printers, liquid toner printers, powder pad 3D inkjet printers, and the like. Exemplary printing device components include ink tanks; ink bottles; print heads; inkjet print head cartridges; dry toner tanks; dry toner cartridges; photoconductive cartridges; processing cartridges; liquid toner tanks; 3D printing agents including inks, stimulating agents, adhesives, inhibitors, etc.; building material for 3D printing; service components of the printing device; and/or any other component that may be interchangeable with respect to the host print device and may or may not contain print material. In this invention, the print material or print agent may include ink, dry or liquid toner, 3D printing agents, 3D building material (plastic, metal, etc.), fibers, and so on. The above reservoirs may contain colored print material.

[0019] Transfers between the printing device and removable components of the printing device installed in the device may provide various functions. For example, the identifier, functionality, and/or status of a pluggable printer component and/or logic associated therewith may be communicated to the printer logic via a communication interface. For example, logic associated with (or provided on or in) the print agent container may convey an identifier, such as a serial number and/or product brand, and/or identification characteristics, such as a color, a color map, a color map reconstruction recipe, the maximum amount of printing agent or functionality per printing device in which it is installed, see, for example, international patent applications no. The status, eg fill level, may be provided via a communication interface, eg such that the printing device may generate an indication of the fill level to the user. In some examples, the authentication process may be performed by the printing device. For example, the printing device may verify that the replacement component of the printing device comes from an authorized source to ensure its quality. For example, logic associated with a removable printer component may store secret keys and may be configured to generate session keys, session key identifiers, and/or message authentication codes to generate authenticated cryptographic responses to the printer, see, for example, U.S. Patent No. 9,619,663. The logic may also include additional authentication mechanisms, such as specialized hardware to calculate responses in predetermined, relatively short, time windows, see, for example, US Pat. No. 9,561,662. In some examples, the authentication process may include integrity checks. to ensure that the replaceable print device component and/or the logic associated with it functions as expected.

[0020] In turn, instructions for performing a job may be sent to the logic circuit of the printer device component from the logic circuitry associated with the printer device via a communication interface. For example, they may include instructions for performing an authentication or encryption function, a print media level registration function, print jobs, or other jobs.

[0021] At least some of the examples described below describe a set of logic circuits. The set of logic circuits may be associated with, for example, attached to, or located at least partially within a printer device plug-in component, and configured to communicate with the printer device controller via a bus provided as part of the printer device.

[0022] As used herein, the term 'set of logic circuits' refers to one or more logic circuits that can be interconnected or connected to each other with the ability to exchange data. When more than one logic is provided, they may be encapsulated as a single unit, or may be encapsulated separately, or may not be encapsulated, or some combination of the above may be possible. Each set may be configured to communicate via a serial bus interface.

[0023] In some examples, each set of logic circuits is provided with at least one processor and memory. In one example, a set of logic circuits may be, or may function as, a microcontroller or a secure microcontroller. During operation, the set of logic circuits may be attached to or combined with a replaceable component of the printing device.

[0024] In some examples, a set of logic circuits may respond to requests (or commands) of various types from a host device (eg, a printer device). The request may include a request for data, such as identification and/or authentication information (eg, a 'read' request). In other examples, the request may contain a 'record' request. Another request from the host may be a request to perform an action, such as performing at least one measurement or performing a print job, or the like. Another type of request may be a data processing action request.

[0025] In an interaction example, the host device may send a command to a set of logic circuits associated with a removable component of the printer device, which can execute the command and load the received data into memory (In some examples, into a buffer and / or a specific memory register). The host can send an additional command to read the response, so that the response is sent as serial data over the connected bus. Such a process can be used, for example, to obtain data stored in the memory of a set of logic circuits. For example, the first request may be a request for this bundle identifier, and may result in the bundle identifier being loaded into a memory buffer. A subsequent 'read' request may result in the data being read from the buffer and transmitted as a serial data signal.

[0026] In at least some examples, a plurality of such sets of logic circuits (each of which may be associated with one or another removable component of the printing device) can be connected to the I2C bus.

[0027] FIG. 1 shows an example of a printing system 100. The printing system 100 includes a printer 102 associated with a removable printer component 104 over a communication line 106 . Although for clarity, the replaceable component 104 of the printer is shown external to the device 102 of the printer, in some examples, the replaceable component 104 of the printer may be enclosed in the printer. Printing device 102 may be a 2D printing device or any type of 3D printing device.

[0028] The replaceable component 104 of the printer may, for example, contain a consumable resource of the printer 102 or a component whose life is likely to be less (in some examples significantly less) than that of the printer 102. For example, the print device component 104 may physically store ink, toner, 3D printing agent, or 3D printing powder, and may be intended to be replaced after significant consumption. The replaceable component 104 of the printing device may, for example, contain a container or cartridge of print material (which may be a container of building material for 3D printing, or a container for liquid printing agent for 2D or 3D printing). In some examples, the replaceable print device component 104 may include a print head or other dispensing component. While this example shows a single replaceable print device component 104, in other examples, there may be multiple replaceable print device components, such as containing containers for different colors of print agents, printheads (which may be combined with the containers), and the like.

[0029] In some examples, link 106 may comprise a serial bus, such as an I2C capable or compatible bus (hereinafter referred to as an I2C bus).

[0030] FIG. 2 shows an example of a replaceable print device component 200 that the replaceable print device component 104 shown in FIG. 1. The printer plug-in component 200 includes a data interface 202 integrated into the logic circuitry 204. During operation of the replaceable component 200 of the printer, the set of 204 logic circuits decodes the data received through the interface 202 data. Data interface 202 may include an I2C interface.

[0031] In some examples, logic circuitry 204 may be further configured to encode data for transmission over data interface 202. In some examples, there may be more than one data interface 202 provided for a single component 200.

[0032] In some examples, logic circuitry 204 may be configured to act as a 'slave' in I2C transmissions.

[0033] The replaceable print device component 200 in this example includes a print media reservoir 206, which may contain any of the print media examples discussed above.

[0034] FIG. 3 shows an example of a printing device 300. The printer 300 may provide the printer 102 shown in FIG. 1. The print device 300 includes a controller 304 that includes an interface 302 for association with a print device plug-in component and a communication bus 306 . Controller 304 contains logic circuitry. In some examples, interface 302 is an I2C interface and communication bus 306 is a communication bus with I2C capabilities.

[0035] In some examples, controller 304 may be configured to act as a host or master in I2C transmissions. The controller 304 may generate and send commands to at least one pluggable print device component 200, and may receive and decode responses received therefrom.

[0036] Such a print device 102, 300 and replaceable component(s) of the print device 104, 200 and/or their logic circuitry may be manufactured and/or sold separately. In an example, a user may receive the print device 102, 300 and own the device 102, 300 for several years, while many replacement parts 104, 200 of the print device may be purchased over the years, for example, as the print agent is used to create the printed product. Therefore, there may be at least a degree of forward and/or backward compatibility between the print device 102, 300 and the replaceable components 104, 200 of the print device.

[0037] FIG. 4 and 4A show an example of a method that can be performed by a set of logic circuits associated with a replaceable component of a printing device. In some examples, this method may be implemented in such a way that the printer device, in which the removable component of the printer device is installed, can determine the physical position of the removable component of the printer device. While the methods provided here can be used with communication protocols other than I2C, such as the Serial Peripheral Interface (SPI) protocol, it can be noted that in I2C protocols, multiple devices are connected in series on a single bus without any means of immediately detecting or declaring them. physical position or order. However, when considering, for example, SPI, there are two wiring configurations, parallel and series connected. In a parallel wiring configuration, there is a separate line dedicated to each ‘slave’ logic circuit, and in a serial wiring configuration, the devices are wired in series in a particular order, so their relative position can be verified in some other way. Therefore, the method provided here can be of particular benefit with protocols where it is otherwise difficult to check the physical position of a device, such as I2C. However, this is not a limitation.

[0038] In the example shown in FIG. 4, block 402 comprises receiving a first command sent to an address of logic associated with a removable print device component via a serial data bus, such as an I2C bus. In some examples, the first command may indicate an operating mode. In some examples, the first command may indicate a period of time. The address may be an I2C bus interface address stored and/or hardwired in a logic/logic set. The first command may be sent to an address by the controller of the print device. The first command may be a predefined command.

[0039] Block 404 comprises generating, by logic, a low voltage condition on the serial data bus. As described in more detail below, this may comprise essentially providing a connection between the serial data bus (and in particular the data line of the serial data bus) and ground. In one example, the low voltage is a nominal ground or reference voltage, eg, approximately 0 V. As will also be described below, the low voltage is lower than the high or default voltage state or condition.

[0040] Block 406 comprises monitoring the duration of the low voltage condition using a logic timer. The timer may comprise an integral timer internal to the logic circuit, for example, comprising a resistance-capacitance (RC) circuit configured to act as a timer, logic gates provided with a counter, crystal or ring oscillator, a phase locked loop (also known as as a phase lock loop) and the like, or any timer that logically forms part of a logic circuit provided in conjunction with a replaceable component of the printing apparatus. The timer may provide an internal clock signal that is provided even in the absence of a clock signal on the serial data bus. The timer can count and thus allows you to determine the duration of the timer period specified in the first command.

[0041] The timer may be designed to measure the time period of the command. In some cases, the timer is intended to measure time independently of other, general purpose, cycles in the actual set of I2C logic circuits, for example, I2C clocks and/or processing cycles of the host CPU or logic circuit. For example, a timer may be configured to count faster than a clock and may start and stop counting regardless of the timing of the clock. The timer may be configured to count independently of the speed of the logic/host CPU, eg having nominal specifications unrelated to the CPU.

[0042] In other examples, the logic circuit/logic stack may track a period of time based on tracking an external timer, such as an external clock, or by tracking external or internal waveforms, oscillating signals, etc., which in some cases may be suitable for determining the duration of a period of time. In one example, a set of logic circuits timer may be a timer in wireless communication with the logic circuit (and thus one timer can be shared by more than one logic circuit).

[0043] The method may comprise releasing the bus, or removing the low voltage condition, at the end of the time period such that the serial data bus assumes a different, high and/or default, voltage state or condition). This may, for example, include interruption of the connection to the ground. Outside of the time period, for example, before and after the duration of the time period initiated in response to the first command, the logic/logic stack may generate a high voltage condition. Alternatively, such a high voltage condition can be a default condition created by including a ‘pull-up’ resistor on the bus, as described below.

[0044] Considering, for example, the I2C data bus, it contains two communication lines: a serial data line (SDA) and a serial clock line (SCL). SDA and SCL can be two-way lines connected to the positive supply voltage through a current source or pull-up resistor.

[0045] In the absence of a signal on the line (ie, in the absence of a clock signal on the SCL and/or in the absence of a data signal on the data line), both lines may default to a high voltage state. The specific value of the voltage in the high voltage state depends on many operational factors, but in some examples may be several volts, for example, from about 3 to 6 volts. Therefore, although the overall 'high' voltage may be relatively low, it is high compared to the 'low' bus voltage condition, which may be, for example, less than 1 volt.

[0046] A master/master device (for example, in the present context, a processing circuit or a printer controller in which a plug-in printer is installed) can generate a clock signal by driving the voltage of the SCL line to a low state, for example, using a free-drain configuration to, in fact, , provide grounding. For example, a switch (eg, a FET) may be activated (closed) to instruct a low voltage state, then reopened so that a pull-up resistor on the line can drive the voltage to a high state. In other examples, a free collector configuration can be used in which a bipolar transistor (BJT) can be used for a similar result. Load and release timing provides a clock that is controlled by the master's processing circuitry.

[0047] For data communication, either the master or the slave (in this example, the logic associated with the plug-in print device) can selectively control the voltage on the SDA in a similar manner, lowering it (e.g., providing a connection to ground) or allowing it to 'float high'. ' (e.g. breaking ground connection). This is clocked: according to the I2C protocol, the state of the SDA line when the SCL line is high provides at least one bit of data. Generally, if the SDA line is in a low (and steady) state when SCL is in a high state, it means binary 0, and if the SDA line is in a high (and steady) state when SCL is in a high state, it means binary 1 , although obviously, in a given system, this may vary.

[0048] In one example of the method shown in FIG. 4, instead of providing a data signal that is timed to match the high state of the SCL line, the state of the SCL line is not considered. Instead, the voltage drops for a duration that is tracked by the logic timer (again, for example, by securing a connection to ground), then 'released', or may default to a high state (for example, by interrupting that connection). Indeed, in some embodiments, there may be no clock provided by the host for at least part, and in some examples, the entire duration of the low voltage condition.

[0049] As mentioned above, this method can be used in the context of detecting the physical position of replaceable components of a printing device, as described with reference to FIG. 5. For example, this method can be used when determining whether a replaceable component of a print device, such as a print media source, is installed at a designated position. In some instances, this may eliminate or reduce the use of a 'mechanical coding', whereby the replaceable print device component has a specific shape consistent with the 'slot' having a mating shape. This in turn reduces manufacturing complexity, since interchangeable components of a printing device, for example with different types of print media, such as different colors, can share a common physical design. In some examples, a combination of mechanical coding and the methods described here may be used. For example, in some applications where black (K) ink is typically dispensed more frequently than other colors (e.g., in contexts where text is frequently printed), black media supply cartridges may be physically larger than, for example, cyan supply cartridges. , magenta, or yellow media in the CMYK cartridge set. Therefore, in some instances, a mechanical coding may be used for the black cartridge (for example, due to the fact that the black cartridge is much larger than cartridges of other colors), which may be sufficient to ensure that the black cartridges are placed in the intended 'slot', and the methods described here can be used to ensure that cartridges of other colors are placed in the right places.

[0050] In some examples, the time period tracking function, such as with a timer, can be used for other purposes. For example, a set of logic circuits may be configured to have more than one I2C address, for example, to facilitate communication with different logic circuits or different functions contained in the set, over the same I2C bus interface of the logic set (for example, through the same the same single communication pad, and the same single power pad, the same single ground pad, and/or the same single clock pad). For example, default read/write data transmissions and low voltage generation and/or logging may be associated with a logic bank's primary address, which is the aforementioned array address. The set of logic circuits may be further configured to temporarily "switch" (ie, respond to commands addressed to it) to a secondary, eg, new and/or temporary, I2C address upon receipt of the corresponding command. Such an I2C address switch may be preceded by an instruction including a second time period. This second period of time may be monitored by the logic bank, for example using a timer, to determine the time during which the logic bank must respond to commands received at the secondary address. For example, the logic may be associated with a primary (eg, "first" or "default") address during a first time period and a secondary address during a second time period, with the first and second time periods being tracked using a timer. In this context, the first time period may be any time period outside of the second time period. In some practical examples, this second time period may be longer than the time period for generating a low voltage condition to allow sufficient time for data to be transferred to the secondary address, which time period may be longer than, for example, detecting the installation position of a replaceable device component. printing of this invention. Activating at least one other address may comprise setting (e.g., writing, overwriting, or changing) or causing the setting of another address (e.g., a new, temporary second address), for example, by writing a different address to a memory location that specifies the address of the package. logical circuits.

[0051] The logic circuitry may be configured to provide a first set of responses, or operate in a first mode, in response to instructions sent to a first address and provide a second set of responses, or operate in a second mode, in response to instructions sent to a secondary address. address. In other words, the address can trigger different functions provided by the circuit. In some examples, the first response set is available in response to commands sent to the first address and not in response to commands sent to the secondary address, and the second response set is available in response to commands sent to the secondary address and not in response to commands sent to to the first address. In some examples, the first set of the first set of responses may be cryptographically authenticated (eg, accompanied by message authentication, or otherwise cryptographically 'signed' and/or encrypted) and the second set of responses may not be cryptographically authenticated. In some examples, for example, the second address may be used to access other cells or sensors and the like that may be provided on or otherwise associated with the logic circuit.

[0052] Due to the multi-purpose nature of the time period tracking function, the execution times of these multiple tasks (e.g., position detection and transfer to a secondary address) can be specified depending on the characteristics of each platform of the printing device, for example, including speed, capabilities, logical set specifications circuits, the number of plug-in components that can be connected to a single bus, bus speed, etc.

[0053] FIG. 4A shows another example of the operation of logic circuitry associated with a replaceable printer component. In one example, this method may be performed without duration and/or timer tracking.

[0054] Block 402A in FIG. 4A includes receiving a first command similar to FIG. 4. Block 404A in FIG. 4A includes identifying a period of time from the first command and selecting or setting the duration of the low voltage condition based on the period of time. As will be presented in more detail below, a delay circuit corresponding to the received time period may be selected or set such that the delay circuit may be used to generate a low voltage condition before the end of the duration.

[0055] Block 406A comprises generating a low voltage condition for a selected or predetermined duration. For example, the logic delay circuit includes a delay line switch connected to the SDA line. Upon receiving the first command, the logic may activate the delay line switch, which will generate a low voltage condition on the SDA line until its internal logic stops operation, at which time the delay line switch will no longer generate a low voltage condition on the SDA line. The duration between firing and expiration may be approximately equal to, or slightly shorter or longer than, the identified time period, for example, sufficient to facilitate sampling by the printer, as will be explained below. In another example, a low voltage condition may be generated in a manner similar to that shown in FIG. 4, for example, using a similar internal logic timer that expires and switches at the end of its set duration, or other switching schemes may be used.

[0056] Block 408A comprises returning to a default voltage condition after the duration associated with the time period has elapsed. For example, the low voltage condition can be removed so that the serial data bus reverts to a high voltage and/or default voltage state or condition. In one example, the low voltage condition can be removed without first monitoring the timer. Conversely, the low voltage condition can be removed by terminating the delay circuit and/or by switching to the default voltage condition.

[0057] The method illustrated in FIG. 4 and the method illustrated in FIG. 4A may be repeated in the case where, for example, (i) the printer is reinitialized, (ii) a replacement printer component is installed or reinstalled in the printer, (iii) other replacement printer components are installed in the same printer, in which the current printer component is installed, or, (iv) between print jobs or maintenance activities, etc. For various reasons, the logic may receive a first instruction indicating a first time period in the first event, and a first instruction indicating a different, second time period in a subsequent event (which may be the same event at different times or a different event). Therefore, in response to a different first command (eg, block 402A) sent to the same (default) address of the same logic over the serial data bus at different times, where the first command indicates a second time period other than first time period, the logic may again generate a low voltage condition on the serial data bus (eg, block 406A), this time for a second duration based on the second time period, with the second duration different from the first duration based on the first time period. For different first commands at different times (eg, three, four, five, or many more first commands), where each time a different time period is indicated, the low voltage condition may be generated for a different appropriate duration each time. In some examples, the low voltage condition may be generated for varying durations without tracking the timer.

[0058] FIG. 5 shows an example of a serial bus 500 containing only four lines: two active lines, SDA and SCL, as described above, a voltage source connection Vdd, and a ground connection GND. Active lines are two-way. The voltage source connection Vdd is connected to the first voltage source 502, and the SDA line is connected to the second voltage source 504 via a pull-up resistor 506.

[0059] A host device 508, for example, including a printer device controller associated with an analog-to-digital converter 510, is coupled to bus 500. Bus 500, host device 508, and analog-to-digital converter 510 may be provided by a printer device. Host 508 includes processing circuitry associated with (in some examples included with) the printer. Four 'slave devices' 512a-d, which contain logic associated with the removable printer components 514a-d, in this example attached to them, are also connected to the bus 500. In this example, each of the removable printer components 514a-d contains an ink cartridge of one color or another.

[0060] In this example, each slave device 512a-d attached to bus 500 has its own unique address and may be a receiver and/or transmitter. In typical operation, the serial clock and serial data signals are provided from the master device 508 on the clock signal line SCL and the data line SDA, while the operating voltage for the slave devices is provided between the voltage source line Vdd and the ground line GND. Data signals may also be sent from slave device 512 to master device 508.

[0061] In an example, a transmission that starts with a start condition and ends with a stop condition may be referred to as an I2C “burst”. In an example of an I2C packet sent by master 508, this may contain the slave's address, an indication of whether the command is a read or write command (In some examples, these may collectively constitute a byte), an instruction code (which may be a second data byte), and, in some examples, any additional command data (eg, additional command parameters, message authentication codes (MACs), cyclic redundancy checks (CRCs), etc., which may be one or more subsequent bytes of data).

[0062] In the example operation of the method shown in FIG. 4, the master device 508 may first issue a start condition that acts as an ‘attention’ signal to all connected slave devices 512. This may, for example, be characterized by a voltage drop on the SDA line when the SCL voltage is high. The master 508 may then send a byte including the address of the slave 512 that the master 508 wishes to access and a bit that provides an indication of whether the access is a read or write operation.

[0063] After receiving the address byte, all slave devices 512a-d will compare it with their own address. In the absence of a match, slave 512 will generally wait for the next start condition that is initiated by master 508.

[0064] If the address matches, the circuit of this slave device 512a-d will receive the subsequent command information and then generate an acknowledgment response signal ("ACK" signal) (which may include a downshift of the SDA line for a specific clock period).

[0065] In some of the examples herein, the command may be a command that causes the slave device 512 to generate a low voltage condition for a period of time. A low voltage condition may be prescribed after the generation of the ACK response signal. The host 508 may then generate a stop condition.

[0066] After the master device 508 receives the handshake signal, (and in some examples after generating a stop condition), the master device 508 may attempt to confirm that the slave device 512 has generated a low voltage condition on the SDA (and, in some examples, may stop sending clock to SCL while this low voltage condition is pending).

[0067] In this example, a resistive voltage divider circuit is provided on serial bus SDA 500 to provide electronic detection of the respective physical positions of slave devices 512. In particular, multiple divider resistors 516a-d are provided on data line SDA, and there is a connection 518 from data line SDA analog-to-digital converter (ADC) 510. This configuration creates a divider ladder circuit (resistor ladder circuit) that causes the signal voltage from each device 512 to vary depending on the physical position of device 512, as devices 512 are connected to the divider circuit at different points. For example, the signal from slave 512d would pass through four of the divider resistors 516, while the signal from slave 512a would pass through only one of the divider resistors 516a. By registering the voltage value, the position of the slave device 512 generating the low voltage condition can be determined. In other words, each slave device 512 creates a specific low voltage condition. The voltage may be sensed using the ADC 510. The ADC 510 includes circuitry that converts an analog voltage into a digital signal indicative of the voltage level. This digital signal is used by the master 508 to electronically discriminate the physical position of the slaves 512 on the bus based on the voltage level of the signals from the slaves 512. The voltage can be compared to the expected voltage for the device 512 having the address used in the command.

[0068] ADC 510 may receive control signals from and provide data to host 508 over a communication line (which may be another communication bus). Although ADC 510 is shown separately from host 508, ADC 510 may physically form part of host 508, or may be located separately from it.

[0069] The ADC 510 and the ladder divider circuit can be configured to distinguish position by detecting the order of device voltages on bus 500 without interfering with the identification of the high and low states used in data transfer. In other words, all of the characteristically low voltages generated on the bus by each slave device 512 can be relatively removed from the threshold to characterize each data bit as high or low.

[0070] As one example, host 508 may be configured to detect any signal below a threshold as a low voltage condition when receiving data. For example, any voltage below 2 V, or below 1 V, at a high SCL voltage may be identified as a low data bit (0 in some examples), while values above this threshold may be identified as a high data bit (1 in some examples). In some examples, the threshold for detecting a low data bit is a voltage below 1.3 V.

[0071] However, the host 508 using the converted voltage from the ADC 510 can be configured to distinguish between specific signals that are below this threshold and slightly above zero (or nominally 0 V) (for example, up to a few hundred millivolts (mV)) to provide positional identification. Each divider resistor 516 may have sufficient resistance that the voltage created between the sum of the divider resistors 516 and the pull-up resistor 504 is below the low voltage threshold. However, the divider resistors 516 may be chosen small enough that the identification of the high voltage signals from the master 508 during normal operation is not unduly compromised, i. so that the high voltage remains relatively close to the maximum voltage provided by the second voltage source 504.

[0072] In one embodiment, each of the divider resistors 516 has a resistance of about 51 ohms, although this is only one of many resistance levels that can be used, and resistance levels can vary between different resistors 516. In such an example, the first and second sources 502 , 504 voltages may provide about 3.3 volts, and pull-up resistor 506 may be a resistor of about 1000 ohms (1 kΩ), i. a much larger resistance value than the divider resistors 516.

[0073] In other words, the divider resistors 516 can act as separate ‘additional’ pull-up resistors on the SDA line, preventing drops to nominal 0 V. This can provide, for example, a voltage spread of about 100-200 mV around the above values. The ADC 510 can measure them with 'counts'. For example, in a 3.3V system where a 9-bit ADC is provided, this in turn means that each sample represents about 6mV (which is obtained by dividing 3.3V by 512). Therefore, the ADC 510 can be expected to record from about 20 counts for the lowest voltage cartridge to about 80 counts for the highest voltage.

[0074] As mentioned above, the positions of at least some of the replaceable components of the print device can be checked using mechanical coding, rather than the methods described here. Therefore, the number of recorded voltage levels may be less than the number of, for example, used print cartridges.

[0075] It may be noted that since specific addresses are associated with the replaceable print device components 514a-d, a particular command can be sent to, for example, 514a, the voltage is sampled, and then the process can be repeated for each of the replaceable device components 514b, c, and d. print in sequence. If the replaceable components 514a-d of the printer are in the expected positions, an upward change in voltage value can be expected if measured in this order. If, however, the replaceable components 514a-d of the printer are not in the expected positions, this pattern (or, more generally, the expected relative stresses) will not be observed and a warning may be generated.

[0076] In practice, the period of time during which the SDA line is kept low may exceed the sampling time period. For example, slave device 512 may be instructed by master device 508 to hold the SDA line low for 50 ms. During this time, the host ADC 510 may sample the data line SDA in a number of time periods, such as 3 to 10 time periods. In some examples, if at least one of these readings falls outside a certain threshold range, the instruction may be repeated, producing new samples. In other examples, samples can be taken until a threshold of 'good' samples is exceeded. In some such examples, there may be a maximum allowed number of samples before an error condition is declared, for example, sampling will continue until 5 samples are taken that are within the expected range, or a maximum of 10 samples have been taken. If a ‘good’ set of samples is not obtained, an error may be indicated. The samples can be averaged to generate a representative value for this replaceable printer component 514a-d.

[0077] The sampling period may be relatively short. For example, after slave 512 is instructed to hold the SDA line low, master 508 may wait for the bus to be sampled so that the bus can be negotiated (eg, about 10 ms). Samples can be acquired in about 1 ms. However, the SDA line may be held low for a longer period, such as 50 ms, to allow rechecking and the like. This period may be specified in, or in some examples associated with, the first instruction (eg, by referring to a lookup table or register maintained in slave 512).

[0078] Therefore, it is not necessary to keep the SDA line low for the entire period of time specified in the first command, where applicable. However, it is possible that, at least statistically, slave 512 keeps the SDA line low in such a way that the sampling period is likely to last for the time that the SDA line is held low during at least one of the valid set of tests.

[0079] Obviously, the SDA line can be kept low, in fact, by sending a data signal formed by a sequence of data bits associated with a low voltage condition (eg, a sequence of 0-bits). As a result, the SDA line will be kept low for a period of time. However, when sending a data signal, the slave 512 can refer to the signal on the SCL, rather than its own internal timer, to determine when to release the SDA line so that it can return to a high state (i.e., when to clear a low voltage condition, such that the serial data bus assumes a different, high and/or default, voltage state or condition). However, in the methods provided herein, the low voltage condition was applied after the first instruction was given, regardless of any clock signal on the SCL bus (and in some cases, in the absence of any such clock signal on the SCL bus).

[0080] FIG. 6 and 7A show examples of a method for operating a logic circuit (eg, a set of logic circuits as described above) associated with a replaceable component of a printing device. In both examples, with reference to the respective blocks 602 and 702A, the logic receives, via the I2C data bus, the first command, which indicates the first time period. In this example, the first instruction also contains a start condition indication, a logic set address, an identification field indicating the write command, and a stop condition indication (eg, rising voltage on the data line during the high portion of the clock pulse).

[0081] In some examples, the time period may be selected based on attributes of the host device or its schema. In general, the time period may be long enough to ensure good samples are captured, but not so long as to unnecessarily lengthen the time taken to check the position of the printer's replaceable component.

[0082] Referring to FIG. 6, block 604 comprises generating, by logic, a low voltage condition on the I2C serial data line after receiving a stop condition indication (which itself follows the transmission of the command) and for substantially the duration of the first time period. As mentioned above, although in some examples the low voltage condition may be generated for the entire time period, in some examples the method may comprise allowing the serial data line to ‘float high’ for a portion of the first time period, i.e. line can be kept low in intermittent mode. In some examples, the serial data line may be held low for at least 60% of the first time period, or at least 70% of the first time period, or at least 80% of the first time period, or at least 90% of the first time period, or at least 95% of the first time period. In some examples, the voltage is kept low for a sufficient proportion to reliably match the sampling period. The duration of the low voltage condition comprises at least one sampling period, where the sampling is performed by the processing circuit of the printer, as described above. In addition, if the data line is kept low for an excessively long period of time, it results in blocked transmissions and may, for example, cause the host to generate a timeout error or the like.

[0083] Generating a low voltage condition after receiving a stop condition indicates that the bus will not be blocked during the current transmission of a data packet.

[0084] In this example, the generation of the low voltage condition coincides with a state in which no clock exists on the serial data bus, and block (step) 606 comprises monitoring the duration of the low voltage condition using an integrated logic timer.

[0085] The method further comprises, in block (step) 608, in response to a read request, having an identification field indicating the read mode, implementation, by the read operation logic. In other words, in addition to the specific features described here, the logic circuit can function as an I2C slave. The logic circuitry may exhibit other characteristics of an I2C slave, such as participating in authentication and/or credential exchanges, receiving or executing read and/or writing commands, performing processing tasks, etc.

[0086] In an example where the logic circuitry is configured to use an additional, different, secondary function and/or secondary address, the secondary function may comprise enabling or energizing a fifth pad or line, such as to connect to a subcircuit. The secondary address can be any address other than the default (or first or “primary”) address of the logic circuit. Accordingly, the method may further comprise, at block 610, invoking the secondary function and/or address for a different (eg, longer) period of time specified in the third instruction directed to the default address of the logic circuit. The logic circuitry may be configured, in response to the third command, to then respond to commands directed to the secondary address, and during that other period of time, reset its secondary address to the new secondary address before the duration expires.

[0087] In the example, the third command specifies a different (eg, longer) period of time to use the secondary function associated with the secondary address. Accordingly, the logic circuit responds to commands directed to the secondary address during this specified period of time. In an example, different secondary addresses may be used for a specified period of time, such as each session starting with a default secondary address, and then switching to new (eg, random or different) secondary addresses based on that new secondary address specified in a subsequent command. following the third command. Again, communication via the secondary address may be enabled for a duration based on the specified time period, but the duration of which need not be exactly that time period, as explained with reference to block 604. Different time periods may be specified in different third commands, so that the logic may be configured to enable communication via the secondary address for various respective durations. During these durations, the logic circuit may not respond to commands through its first default address.

[0088] In another example, corresponding to block 610, the logic may, based on a third instruction indicating a time period, enable a secondary function for the specified time period without activating the secondary address. For example, the secondary function includes powering or driving a subcircuit, for example, including a fifth pad or line separate from the power, ground, clock, and printer interface data lines. In a further example, the secondary address is enabled using a pluggable or connected second logic associated with the secondary function that can, in an intermediate state of logic, be disconnected from the rest of the logic, and, in an operational state of the logic, be connected to the rest of the logic as parts of the kit.

[0089] In one example, the logic circuitry is configured to track the duration of the time period specified in the third command, such as using a timer. The logic circuitry may be configured to switch back to a default address and/or function after the duration has elapsed. In another example, the logic circuit is not required to keep track of the duration. Rather, it is configurable or selectable for the delay circuit to match the (“different”) time period of the third command such that the logic switches back to a default address at the end of a predetermined or selected duration corresponding to the third command time period.

[0090] FIG. 7 shows an example of a logic circuit 700 for associating with a removable printer component, comprising logic 702, a serial data bus interface 704, a timer 706, and, in this example, a memory 708. During operation of the logic circuit 700, logic 702, in response to the first a command sent to the logic bank 700 via a serial data bus connected to the serial data bus interface 704, the logic bank 700 in this example is configured to generate a low voltage condition on the serial data bus and tracks the length of the time period using a timer 706. In some examples, the timer 706 may be in communication with the logic 702, such as over a wired or wireless link. In some examples, timer 706 may be provided on a common substrate with logic 702.

[0091] In some examples, logic 702 may be configured to track the length of a period of time without reference to a serial data bus clock. The serial data bus interface 704 may include an I2C data bus interface.

[0092] The first command may indicate a period of time, and logic 702 may be configured to generate a low voltage condition on the serial data bus for substantially the duration of the first period of time. Logic 702 may implement any aspects of the methods described above with respect to FIG. 4-6.

[0093] In response to the second command, logic 702 may be configured to write data received via serial data bus interface 704 to memory 708. In response to a read request, logic 702 may be configured to read data from memory 708 and transmit data signal through the interface 704 serial data bus.

[0094] FIG. 7A shows an example of how the logic circuit operates, differing in some respects from the method illustrated in FIG. 6. In one example, the method shown in FIG. 7A may be performed without tracking the timer. Block (step) 702A shown in FIG. 7A corresponds to block 602 in FIG. 6.

[0095] Block (step) 704A shown in FIG. 7A comprises setting or selecting a delay scheme (see, for example, FIG. 7B) based on a specified time period, where the time period, as explained above, may vary for different first commands. The delay circuit is used to generate the low voltage condition of the 706A block. Setting the delay circuit may include setting the delay time (or "expiration"), or duration, of the delay circuit, the duration of which, in some cases, is not yet predetermined, to facilitate returning or switching to a default voltage condition (for example, high ) after this duration. Selecting a delay circuit includes selecting one of a plurality of delay circuits included in the logic circuit, where each delay circuit has one or another predetermined characteristic duration to generate a low voltage condition, to facilitate, using the selected delay circuit, returning or switching to a condition default voltage (e.g. high) after the selected duration. The exemplary delay circuit(s) may be configured or selected, respectively, such that the duration of the low voltage condition corresponds to the time period of the first command. Accordingly, the duration may vary according to different time periods specified in different first commands. In some example, the delay circuit may include a timer or delay line switch, or other circuits that are pre-set or configured for some time delay to facilitate return to a default voltage condition after the duration elapses, for example, without having to monitor the timer.

[0096] Block 706A corresponds to block 604 in FIG. 6. In some examples, during execution, the features of blocks (steps) 604 and 706A shown in FIG. 6 and 7A, respectively, the logic circuit does not respond to other commands. In other words, the logic circuit may not respond to commands, thus generating a low voltage condition.

[0097] Block 708A comprises returning to a default voltage condition (eg, high) on the SDA line. The logic circuitry may revert to a default voltage condition without tracking the timer, eg, based on completion and/or switching of the delay circuitry at the end of the duration.

[0098] Block 710A in FIG. 7A corresponds to block 608 in FIG. 6. Block 712A in FIG. 7A corresponds to block 610 in FIG. 6. At block 712A, in one example, the duration associated with the third command time period is not tracked. For example, one delay scheme may be configurable, or one delay scheme from a plurality of delay schemes may be selected to terminate at the end of an appropriate duration (which may vary between different third commands) to switch back to a default address or function upon expiration (e.g. , variable) duration.

[0099] FIG. 7B shows another example of logic circuit 700B, or a set of logic circuits for association with a removable printer component, comprising logic 702B and delay circuitry 706B, a serial data bus interface (eg, line) 704B, and, in this example, memory 708B. In one example, logic circuitry 700B shown in FIG. 7B is an alternative to or different from the logic circuitry set 700 in FIG. 7. In another example, logic circuitry set 700B does not use the tracking function.

[00100] In operation, logic circuitry bank 700B may be configured to, in response to a first command sent to logic circuitry bank 700B via a serial data bus connected to serial data bus interface 704B, generate a low voltage condition on the serial data bus. The serial data bus interface 704B may include an I2C data bus interface. As explained, the first command may indicate a period of time, and logic 702B may be configured to generate a low voltage condition on the serial data bus for substantially the duration of the first period of time. Logic 702B and logic circuit 700B may implement any aspects of the methods described above with reference to FIG. 4A - 7A.

[00101] In response to the second command, logic 702B may be configured to write data received via serial data bus interface 704B to memory 708B. In response to a read request, logic 702B may be configured to read data from memory 708B and transmit a data signal through serial data bus interface 704B.

[00102] Logic 702B may further include a delay circuit 706B. In one example, delay circuit 706B represents a plurality of delay circuits. In one example, delay circuit 706B may include a plurality of delay line switches, each configured to turn off after a characteristic duration. An example delay line switch includes a transistor having a floating gate with leakage, or an R-C circuit and a comparator, for example, similar to aspects of the timer described above. In some examples, the delay circuit may include hardware similar or identical to a timer, such as described above with reference to block 406 of FIG. 4. In the example, a delay circuit 706B is connected to a serial data bus interface 704B, for example, connecting the serial data bus interface and microcontroller logic, although the delay circuit can be implemented in other hardware configurations to achieve the same results. In one example, logic 702B is configured, upon receipt of the first command, to select the delay line switch that corresponds to the specified time period and to operate it. The selected and enabled delay line switch is configured to generate a low voltage condition on the SDA line 704B until its operating time expires, at which time the switch will stop generating a low voltage condition on the SDA data bus interface 704B. A selected and enabled delay line switch may be configured to disable the (remaining) logic 702B from the SDA serial bus during the generation of a low voltage condition, prior to expiration of its operating time, such that communication on the SDA bus is not possible under such a low voltage condition. Therefore, the low voltage condition may be generated by different delay circuits having different characteristic durations, so that the low voltage condition may be generated for different durations corresponding to different delay circuits and different accepted time periods. In some instances, during the low voltage condition generation time, communication on the SDA 704B bus may not be possible.

[00103] Memory 708B may store a lookup table (LUT) and/or an algorithm that associates each delay circuit (eg, delay line switch) with a time period or range of time periods. Logic 702B may be configured, upon receipt of the first command, to select a delay scheme that corresponds to the received time period using the LUT and/or algorithm.

[00104] In another example, the delay circuit may be configurable for different durations, without a tracking function, using internal logic. For example, the delay circuit includes a plurality of delay line switches and/or other switches, for example connected in series, so that, depending on the required duration, an appropriate switch can be set or selected. The number of delay line switches that is used to generate a low voltage condition depends on the selected switch, so that the delay duration is determined by the accumulated durations of the different delay line switches used, so that the accumulated duration can be set according to the received time period. Other examples of switching circuits can be used to set the duration of the low voltage generation in accordance with the accepted time period. One skilled in the art will appreciate that as part of logic 702B, a single, configurable, delay circuit for several different times can be used, or a plurality of, for example, fixed and/or parallel delay circuits, each associated with a different characteristic delay time.

[00105] FIG. 8 shows an example of a replaceable component of a printing device containing a set of logic circuits as shown in FIG. 7. In this example, the replaceable component of the printing device is the print cartridge 800, the width of the housing 802 of which is less than its height. A print fluid outlet 804 (in this example, an outlet provided on the underside of the cartridge 800), an air inlet 806, and a recess 808 are provided on the front surface of the cartridge 800. The recess 808 extends over the top of the cartridge 800, and the I2C bus terminals 810 of the logic circuitry 812 (e.g., logic array 700 as described above) are provided on the side of the notch 808 against the inside wall of the side wall of the housing 802 near the top and front of the housing 802. In this example, the logic array 812 is provided against the inside of the side wall.

[00106] Examples in the present invention may be provided as methods, systems, or machine-readable instructions, such as any combination of software, hardware, firmware, and the like. Such computer-readable instructions may be included in a computer-readable storage medium (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) that stores computer-readable program codes.

[00107] The present invention has been described with reference to flowcharts and flowcharts of the method, devices and systems according to examples of the present invention. Although the above flowcharts show a specific execution order, the execution order may differ from that shown. Blocks described with respect to one flowchart may be combined with blocks of another flowchart. It should be understood that at least some of the blocks in the flowcharts and block diagrams, as well as combinations thereof, may be implemented by computer readable instructions.

[00108] Machine-readable instructions may, for example, be executed by a general purpose computer, a special purpose computer, an embedded processor, or processors of other programmable data processing devices to implement the functions described in the description and diagrams. In particular, the processor or processing circuit may execute machine readable instructions. Thus, the functional modules of the device and devices (eg, logic circuitry and/or controllers) may be implemented by a processor executing machine-readable instructions stored in memory, or by a processor acting in accordance with instructions embedded in the logic circuitry. The term ‘processor’ should be interpreted in a broad sense to include CPU, processing unit, ASIC, logic unit or field programmable gate array, etc. All methods and functional modules may be implemented by a single processor or shared between multiple processors.

[00109] Such computer-readable instructions may also be stored in a computer-readable storage (eg, a tangible computer-readable medium) and may direct the computer or other programmable processing devices to operate in a particular mode.

[00110] Such computer-readable instructions can also be downloaded to a computer or other programmable data processing devices, such that the computer or other programmable data processing devices perform several operations to create computer-implemented processing, thus, instructions executable on a computer or other programmable data processing devices, implement the functions indicated by the block(s) in the flowcharts and/or in the flowcharts.

[00111] Additionally, the principles set forth herein may be implemented in the form of a computer program product, wherein the computer program product is stored on a storage medium and contains a plurality of instructions to cause the computing device to implement the methods mentioned in the examples of the present invention.

[00112] While the method, apparatus, and related aspects have been described with reference to some examples, various modifications, changes, deletions, and substitutions can be made without departing from the spirit of the present invention. Therefore, the method, apparatus, and related aspects are intended to be limited only by the scope of the following claims and their equivalents. It should be noted that the above examples illustrate more than what is described here, and that many alternative implementations will be available to those skilled in the art without departing from the scope of the following claims. Features described with respect to one example may be combined with features of another example.

[00113] The word “comprising” does not exclude the presence of elements other than those listed in the claims, their mention in the singular does not exclude the plurality, and a single processor or other block may implement the functions of several blocks mentioned in the claims.

[00114] The features of any dependent claim may be combined with the features of any of the independent claims or other dependent claims.

[00115] In some examples, the method can be described in any of the following aspects.

[00116] Aspect 1: A method comprising, in response to a first command sent to an address of a logic circuit associated with a removable print device component, via a serial data bus, the first command indicating a first time period, generating, by the logic circuit, a low voltage condition on the serial data bus during the first duration based on the first time period; and in response to another first command sent to the same address of the same logic circuit via the serial data bus at different times, wherein the other first command indicates a second time period different from the first time period, generating, by the logic circuit , low voltage conditions on the serial data bus for a correspondingly different duration based on the second time period.

[00117] Aspect 2: The method of the previous aspect, further comprising removing the low voltage condition such that the serial data bus assumes a different high and/or default voltage state or condition after a period of time.

[00118] Aspect 3: The method according to the previous aspect, further comprising operating a delay circuit configured to maintain a low voltage condition for different time periods based on the received time period.

[00119] Aspect 4: the method according to aspect 2 or 3, comprising generating and removing a low voltage condition without tracking the duration of the time period.

[00120] Aspect 5: The method according to any one of aspects 2-4, comprising using a timer to maintain a low voltage condition.

[00121] Aspect 6: A method according to any one of aspects 2-5 comprising generating a low voltage condition on a serial data bus for substantially the duration of a time period specified in a respective one of said commands.

[00122] Aspect 7: The method according to any of the previous aspects other than aspect 4, comprising monitoring a low voltage condition.

[00123] Aspect 8: A method according to any previous aspect, comprising generating a low voltage condition on a serial data line of a serial data bus.

[00124] Aspect 9: The method according to any previous aspect, wherein the duration of the low voltage condition comprises at least one sampling period, wherein the sampling is performed by the processing circuit of the printing device during the sampling period.

[00125] Aspect 10: A method according to any previous aspect, wherein generating a low voltage condition coincides with a state in which no clock exists on the serial data bus.

[00126] Aspect 11: A method according to any previous aspect, wherein the first instruction comprises an identification field indicating a write command and an indication of a stop condition, the method further comprising generating, by logic, a low voltage condition on the serial data bus after receiving the indication of the stop condition.

[00127] Aspect 12: The method of Aspect 11, further comprising, upon expiration of the duration, in response to the read/write command, performing, by logic, read/write operations.

[00128] Aspect 13: A method according to any previous aspect, wherein the low voltage condition voltage value indicates the position of the replaceable print device component in the print device.

[00129] Aspect 14: a set of logic circuits for associating with a removable component of the printing device, comprising: logic and a serial data bus interface, wherein the serial data bus interface serves to interface with the serial data bus of the printing device and, wherein the logic serves, in response to the first a command sent to a set of logic circuits through a serial data bus connected to the serial data bus interface, the first command including a period of time, to generate a low voltage condition on the serial data bus for a duration based on the period of time, and, after the duration , to return to the default voltage condition on the serial data bus.

[00130] Aspect 15: A set of logic circuits according to aspect 14, wherein the logic is configured to generate a low voltage condition for different durations based on respective different received time periods.

[00131] Aspect 16: A set of logic circuits according to aspect 14 or 15, in which the logic is intended, in response to another first command sent to the set of logic circuits via a serial data bus connected to the interface of the serial data bus, and the other first command includes in itself a second time period, different from the first time period, to generate a low voltage condition on the serial data bus for a second duration based on the second time period, the second duration being different from the first duration, and, after the expiration of the second duration, to return to voltage over default on the serial data bus.

[00132] Aspect 17: A set of logic circuits according to any one of aspects 14-16, comprising a switch to return to a default voltage after a duration of time based on the received period of time.

[00133] Aspect 18: A set of logic circuits according to any one of aspects 14-17, in which the logic is configured, under a low voltage condition, not to respond to commands.

[00134] Aspect 19: A set of logic circuits according to any one of aspects 14-18, wherein the logic comprises a plurality of delay circuits for generating a low voltage condition on a serial data bus, each delay circuit being associated with a characteristic duration such that different delay circuits from the set delay schemes are associated with different durations, the logic serving to select a delay scheme based on the received time period.

[00135] Aspect 20: A set of logic circuits according to any one of aspects 14-19, wherein the logic comprises an adjustable delay circuit for generating a low voltage condition on the serial data bus for a variable duration, and adjusting the duration based on the received time period.

[00136] Aspect 21: A set of logic circuits according to any one of aspects 14-20, wherein the delay circuit, or each of them, is configured to terminate after a duration of time, the logic to return to a default voltage when the delay circuit terminates.

[00137] Aspect 22: A set of logic circuits according to aspect 18 or 19, containing a memory where a lookup table or algorithm is stored for selecting or adjusting a delay circuit.

[00138] Aspect 23: A set of logic circuits according to any one of aspects 14-22, configured to generate a low voltage condition on the serial data bus based on a period of time without tracking the duration of the period of time.

[00139] Aspect 24: A set of logic circuits according to any one of aspects 14-23, wherein the logic is configured to generate a low voltage condition for different durations based on respective different received time periods, the duration of each corresponding to a different range of time periods.

[00140] Aspect 25: A set of logic circuits according to any one of aspects 14-24, configured to track the duration of a period of time.

[00141] Aspect 26: A set of logic circuits according to any one of aspects 14-25, further comprising a timer.

[00142] Aspect 27: A set of logic circuits according to aspect 26, in which the logic is used to track the duration of a period of time using a timer.

[00143] Aspect 28: A set of logic circuits according to any one of aspects 14-27, in which the logic serves to remove a low voltage condition on the serial data bus at the end of a period of time.

[00144] Aspect 29: A set of logic circuits according to any one of aspects 14-28, wherein the logic is configured to cause the serial data bus to assume a different, high and/or default, voltage state or condition outside of a time period.

[00145] Aspect 30: A set of logic circuits according to any one of aspects 14-29, wherein the first instruction contains a logical address and ends with a stop condition, and the logic generates a low voltage condition upon receiving the stop condition.

[00146] Aspect 31: A set of logic circuits according to any one of aspects 14-30, wherein the logic is used to generate a low voltage condition without reference to a serial data bus clock signal.

[00147] Aspect 32: A set of logic circuits according to any one of aspects 14-31, in which the logic is used to generate a low voltage condition on the serial data bus for a substantially long period of time.

[00148] Aspect 33: A set of logic circuits according to any one of aspects 14-32, further comprising a memory where, in response to a second command outside of said duration, the logic is to write the data received via the serial data bus interface to the memory.

[00149] Aspect 34: A set of logic circuits according to any one of aspects 14-33, further comprising a memory where, in response to a read or write request outside of said duration, the logic is to read data from the memory or write data to the memory and transmit a data signal through serial data bus interface.

[00150] Aspect 35: A set of logic circuits according to any one of aspects 14-34, wherein the serial data bus interface is an I2C data bus interface.

[00151] Aspect 36: A set of logic circuits according to any one of aspects 14-35, configured to receive another command indicating a different time period and associated with a secondary function, and, upon receipt of this command, energize or operate a fifth pad or line, separate from the power, ground, clock, and printer interface data lines for a duration based on a specified different time period.

[00152] Aspect 37: A set of logic circuits according to any one of aspects 14-36, configured to communicate via more than one I2C address on the same I2C bus interface; receive another command via the default address, wherein the other command is different from the first command and indicates a different time period; and, respond to subsequent commands directed to a secondary I2C address other than the default address for a duration based on a different time period.

[00153] Aspect 38: A logic bank according to Aspect 37, wherein the logic bank does not respond from its default address for a duration based on a different time period.

[00154] Aspect 39: A set of logic circuits according to aspect 37 or 38, in which the set of logic circuits is configured, in response to a subsequent command directed to a secondary address and indicating a new secondary address that is again different from the previous addresses, to use a new secondary address, for the remainder of the duration based on another time period.

[00155] Aspect 40: A set of logic circuits according to aspect 37 or 38, in which the logic is configured to track or adjust the duration based on a period of time specified in another instruction using at least one of a delay circuit and a timer.

[00156] Aspect 41: A replaceable print device cartridge for connection to a print device, comprising a reservoir containing print material and a set of logic circuits according to any one of aspects 14-40.

Claims (57)

1. The method of operation of the logic circuit, containing the steps in which in response to a first command sent to the address of a logic circuit associated with a printer replaceable component via a serial data bus, the first command indicating a first period of time, the logic circuit generates a low voltage condition on the serial data bus for a first duration based on the first period time; and in response to another first command sent to the same address of the same logic circuit via the serial data bus at a different point in time, this other first command indicating a second time period different from the first time period, generate by said logic circuit a low voltage condition on the serial the data bus for a correspondingly different duration based on the second time period. 2. The method of the previous claim further comprising removing the low voltage condition such that the serial data bus assumes a different high and/or default voltage state or condition after said period of time has elapsed. 3. The method of the preceding claim, further comprising operating a delay circuit configured to maintain the low voltage condition for different time periods based on the received time period. 4. The method of claim 2 or 3, comprising generating and removing a low voltage condition without tracking the length of the time period. 5. The method according to any one of paragraphs. 2-4, comprising a step in which a timer is used to maintain a low voltage condition. 6. The method according to any one of paragraphs. 2-5, comprising the step of generating a low voltage condition on the serial data bus for essentially the duration of the time period specified in the corresponding one of the mentioned commands. 7. A method according to any one of the preceding claims, except for claim 4, comprising monitoring a low voltage condition. 8. A method according to any one of the preceding claims, comprising generating a low voltage condition on a serial data line of a serial data bus. 9. A method according to any one of the preceding claims, wherein the duration of the low voltage condition comprises at least one sampling period, wherein the sampling is performed by the processing circuit of the printing apparatus during the sampling period. 10. The method of any one of the preceding claims, wherein the generation of the low voltage condition coincides with a state in which no clock signal exists on the serial data bus. 11. The method according to any one of the preceding claims, wherein the first command comprises an identification field indicating a write command and indicating a stop condition, the method further comprising: generating, by said logic, a low voltage condition on the serial data bus after receiving the stop condition indication. 12. The method of claim 11, further comprising the step of performing a read/write operation by said logic in response to the read/write command after the duration has elapsed. 13. The method of any one of the preceding claims, wherein the low voltage condition voltage value indicates the position of the replaceable print device component in the print device. 14. A set of logic circuits for association with a replaceable component of a printing device, containing: logic and serial data bus interface, moreover, the serial data bus interface serves to interface with the serial data bus of the printing device, and wherein the logic serves, in response to a first command sent to the logic bank via a serial data bus connected to the serial data bus interface, the first command including a period of time, to generate a low voltage condition on the serial data bus for a duration based on said period of time, and after the duration has elapsed to return to the default voltage condition on the serial data bus. 15. The set of logic circuits of claim 14, wherein the logic is configured to generate a low voltage condition for different durations based on respective different received time periods. 16. A set of logic circuits according to claim 14 or 15, in which the logic is intended, in response to another first command sent to the set of logic circuits via a serial data bus connected to the serial data bus interface, and the other first command includes a second period time period other than the first time period to generate a low voltage condition on the serial data bus for a second duration based on the second time period, the second duration being different from the first duration, and after the expiration of the second duration to return to the default voltage on the serial data bus . 17. A set of logic circuits according to any one of paragraphs. 14-16, comprising a switch for returning to the default voltage after a time duration has elapsed based on the received time period. 18. A set of logic circuits according to any one of paragraphs. 14-17, in which the logic is configured, under a low voltage condition, not to respond to commands. 19. A set of logic circuits according to any one of paragraphs. 14-18, in which the logic contains a plurality of delay circuits to generate a low voltage condition on the serial data bus, wherein each delay scheme is associated with a characteristic duration such that different delay schemes from a plurality of delay schemes are associated with different durations, wherein the logic serves to select a delay scheme based on the received time period. 20. A set of logic circuits according to any one of paragraphs. 14-19, in which the logic contains an adjustable delay circuit for generating a low voltage condition on the serial data bus for a variable duration, and duration settings based on the received time period. 21. A set of logic circuits according to any one of paragraphs. 14-20, wherein the delay circuit, or each delay circuit, is configured to terminate after a duration of time has elapsed, the logic to return to a default voltage when the delay circuit terminates. 22. A set of logic circuits according to claim 18 or 19, containing a memory where a lookup table or algorithm is stored for selecting or setting a delay circuit. 23. A set of logic circuits according to any one of paragraphs. 14-22 configured to generate a low voltage condition on the serial data bus based on a period of time without tracking the length of the period of time. 24. A set of logic circuits according to any one of paragraphs. 14-23, wherein the logic is configured to generate a low voltage condition for different durations based on respective different received time periods, the duration of each corresponding to a different range of time periods. 25. A set of logic circuits according to any one of paragraphs. 14-24 configured to track the duration of a period of time. 26. A set of logic circuits according to any one of paragraphs. 14-25, further comprising a timer. 27. A set of logic circuits according to claim 26, in which the logic is used to track the duration of a period of time using a timer. 28. A set of logic circuits according to any one of paragraphs. 14-27, in which the logic serves to remove the low voltage condition on the serial data bus at the end of the time period. 29. A set of logic circuits according to any one of paragraphs. 14-28, wherein the logic is configured, outside of the time period, to cause the serial data bus to assume a different, high and/or default, voltage state or condition. 30. A set of logic circuits according to any one of paragraphs. 14-29, in which the first instruction contains a logical address and ends with a stop condition, and the logic generates a low voltage condition when the stop condition is received. 31. A set of logic circuits according to any one of paragraphs. 14-30, in which the logic is used to generate a low voltage condition without reference to a serial data bus clock signal. 32. A set of logic circuits according to any one of paragraphs. 14-31, in which the logic serves to generate a low voltage condition on the serial data bus for a substantially long period of time. 33. A set of logic circuits according to any one of paragraphs. 14-32, further comprising a memory where, in response to a second command outside of said duration, the logic is to write the data received via the serial data bus interface to the memory. 34. A set of logic circuits according to any one of paragraphs. 14-33, further comprising a memory, where in response to a read or write request outside the mentioned duration, the logic should read data from the memory or write data to the memory and transmit the data signal through the serial data bus interface. 35. The set of logic circuits of claim 34, wherein the serial data bus interface is an I2C data bus interface. 36. A set of logic circuits according to any one of paragraphs. 14-35, configured to receive another command indicating a different time period and associated with a secondary function, and upon receipt of this command, energize or enable a fifth pad or line separate from the power, ground, clock, and printer interface data lines, over a duration based on a specified different time period. 37. A set of logic circuits according to any one of paragraphs. 14-36, made with the possibility communicate via more than one I2C address on the same I2C bus interface; receive another command via the default address, wherein the other command is different from the first command and indicates a different time period; and respond to subsequent commands directed to the secondary I2C address for a duration based on a different time period. 38. The logic suite of claim 37, wherein the logic suite does not respond from its default address for a duration based on a different time period. 39. The set of logic circuits according to claim 37 or 38, in which the set of logic circuits is configured, in response to a subsequent command directed to a secondary address and indicating a new secondary address, which again differs from the previous addresses, to use a new secondary address, on the remainder of the duration based on another time period. 40. A set of logic circuits according to claim 37 or 38, in which the logic is configured to track or adjust the duration based on the period of time specified in another command using at least one of the delay circuit and the timer. 41. Replaceable cartridge of the printing device for connection to the printing device, containing a reservoir containing print media, and a set of logic circuits according to any one of paragraphs. 14-40.

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