RU2441328C2 - Methods and apparatus for generating multiple cyclic redundancy code (crc) values - Google Patents

Abstract

FIELD: information technology. ^ SUBSTANCE: according to one aspect of the invention, multiple cyclic redundancy code (CRC) values are calculated based on multiple bits by using a selected generating polynomial for the CRC control value, where at least one CRC control value is calculated based on a first subset of multiple bits with determination of the bit order and at least one other CRC control value is calculated based on a second subset of multiple bits with another bit order. The second subset of bits can overlap with the first subset of bits. ^ EFFECT: high probability of successful decoding. ^ 49 cl, 12 dwg

Description

FIELD OF THE INVENTION

The present invention relates to methods and apparatus for generating a plurality of cyclic redundancy check (CRC) control values.

State of the art

A wireless communication system generally includes a plurality of base stations and a plurality of mobile stations, often a single base station communicating with a set of mobile stations. Transmission from a base station to a mobile station is known as downlink communication. Similarly, transmission from a mobile station to a base station is known as uplink communication. Both base stations and mobile stations can use multiple antennas to transmit and receive radio signals. The radio signal may be either orthogonal frequency division multiplexing (OFDM) signals or code division multiple access (CDMA) signals. The mobile station may be a personal digital assistant (PDA), a laptop computer or a handheld device.

In the Long-Term Development System according to the Third Generation Partnership Project (3GPP LTE), when a large transport block is encountered, it is segmented into a plurality of code blocks so that a plurality of coded packets can be created, which provides advantages such as the possibility of implementing parallel processing or pipelining and finding a flexible compromise between power consumption and hardware complexity.

The current technical solution for the high-speed shared data channel (HS-DSCH) creates only one 24-bit cyclic redundancy check (CRC) value for the entire transport block in order to detect errors in this block. When creating and transmitting multiple code blocks in one transmission time interval (TTI), the receiver may correctly decode some code blocks and incorrectly decode others. In this case, the receiver sends back to the transmitter the message "I do not confirm (NAK)", because the CRC for this transport block has not passed the verification.

SUMMARY OF THE INVENTION

Thus, it is an object of the present invention to provide improved methods and apparatus for generating cyclic redundancy check values for a plurality of code blocks.

Another objective of the present invention is the provision of an improved method and device for detecting errors.

According to one aspect of the present invention, a plurality of cyclic redundancy check values based on a plurality of bits are calculated. At least one cyclic redundancy check value is calculated based on a subset of the plurality of bits. Then, a plurality of cyclic redundancy check values and a plurality of bits are transmitted through at least one transmit antenna.

According to another aspect of the present invention, a cyclic redundancy check value for a transport block is calculated based on a transport block of information bits by using a selected generating polynomial for a cyclic redundancy check value. The transport block is segmented into at least one code block. The cyclic redundancy check value for the at least one code block is then calculated based on the at least one code block by using the selected generating polynomial for the cyclic redundancy check value, the cyclic redundancy check value for one code block is calculated based on the corresponding one code block block. Finally, at least one code block and a cyclic redundancy check value for at least one code block are transmitted through at least one transmit antenna. In this method, information bits in a transport block are interleaved after calculating a cyclic redundancy check value for a transport block, but before calculating a cyclic redundancy check value for at least one code block.

Information bits in a transport block may be interleaved with bits in a cyclic redundancy check value for a transport block.

Alternatively, information bits in a transport block may be interleaved without using bits in a cyclic redundancy check value for a transport block.

Information bits in a transport block may be interleaved until the transport block is segmented into at least one code block.

Alternatively, information bits in a transport block may be interleaved after segmenting the transport block into at least one code block.

Information bits in a transport block may be interleaved by applying interleaving patterns that are shorter than the length of the code block.

Information bits in a transport block may be interleaved by replacing at least one information bit with another information bit in a transport block.

According to a further aspect of the present invention, a cyclic redundancy check value for a transport block is calculated based on a sequence of information bits in a transport block by using a selected generating polynomial for a cyclic redundancy check value. The transport block is then segmented into at least one code block. The cyclic redundancy check value for at least one code block is calculated based on the at least one code block by using the selected generating polynomial for the cyclic redundancy check value, the cyclic redundancy check value for one code block being calculated based on the corresponding one code block . Finally, at least one code block and at least one cyclic redundancy check value for the code block is transmitted through at least one transmit antenna. In this method, before computing the corresponding cyclic redundancy check value, either the bit sequence in the transport block or the bit sequence in at least one code block is reverse-ordered.

In particular, the cyclic redundancy check value for the transport block can be calculated based on the natural bit order of the transport block, and the cyclic redundancy check value for the code block can be calculated based on the reverse order of the bit sequence in the code block.

Alternatively, the cyclic redundancy check value for the transport block can be calculated based on the reverse bit sequence in the transport block, and the cyclic redundancy check value for the code block can be calculated based on the natural order of the bit sequence in the code block.

According to another aspect of the present invention, a cyclic redundancy check value for a transport block is calculated based on a transport block of information bits by using a selected generating polynomial for a cyclic redundancy check value. A transport block is segmented into a plurality of code blocks. The bits in the cyclic redundancy check value for the transport block are allocated to each of the code blocks. Then, a plurality of cyclic redundancy check values for code blocks are calculated based on the plurality of code blocks by using the selected generating polynomial for a cyclic redundancy check value, wherein a cyclic redundancy check value for each code block is calculated based on the corresponding code block. Finally, a plurality of code blocks and a plurality of cyclic redundancy check values for code blocks are transmitted through at least one transmit antenna.

According to a further aspect of the present invention, at least one code block from a bit sequence and at least one cyclic redundancy check value for a code block is received via at least one antenna. The at least one code block is decoded. The cyclic redundancy check value for the at least one code block is checked by using the selected generating polynomial for the cyclic redundancy check value to determine if said at least one code block is decoded correctly. If this at least one code block is decoded correctly, it is connected in series to create a transport block. Check the cyclic redundancy check value for this transport block by using the selected generating polynomial for the cyclic redundancy check value to determine if the transport block is decoded correctly. In this method, a bit sequence in either at least one code block or a transport block is reordered after checking the cyclic redundancy check value for at least one code block, but before checking the cyclic redundancy check value for the transport block.

According to another aspect of the present invention, a plurality of cyclic redundancy check values are calculated based on a plurality of bits by using a plurality of generating polynomials for a cyclic redundancy check value. In this method, a first generating polynomial for a cyclic redundancy check value is used to calculate a first cyclic redundancy check value based on a first set of bits, and a second generating polynomial for a cyclic redundancy check value is used to calculate a second cyclic redundancy check code value based on a second set bit.

The first plurality of bits may be a subset of the second plurality of bits.

Alternatively, the first plurality of bits may be an expanded set of the second plurality of bits.

In yet another alternative embodiment, the first plurality of bits may overlap the second plurality of bits.

The first cyclic redundancy check value and the second cyclic redundancy check value may have different lengths.

Alternatively, the first cyclic redundancy check value and the second cyclic redundancy check value may have the same length.

According to a further aspect of the present invention, a cyclic redundancy check value for a transport block is calculated based on a transport block of information bits by using a first generating polynomial for a cyclic redundancy check value. The transport block is segmented into at least one code block. The cyclic redundancy check value for at least one code block is then calculated based on the at least one code block by using a second generating polynomial for the cyclic redundancy check value, the cyclic redundancy check value for one code block being calculated based on the corresponding one code block block. Finally, at least one code block and a cyclic redundancy check value for at least one code block are transmitted through at least one antenna.

According to yet another aspect of the present invention, at least one code block of a bit sequence and a cyclic redundancy check value for at least one code block are received via at least one antenna. The at least one code block is decoded. The cyclic redundancy check value for this at least one code block is then checked by using a second generating polynomial for the cyclic redundancy check value to determine if said at least one code block is decoded correctly. If said at least one code block is decoded correctly, then it is connected in series to create a transport block. Finally, the cyclic redundancy check value for the transport block is checked by using the first generating polynomial for the cyclic redundancy check value to determine if the transport block is correctly decoded.

Brief Description of the Drawings

A more complete assessment of the invention and the many inherent advantages can be obtained and clarified by referring to the following detailed description together with the accompanying drawings, in which the same reference characters indicate the same or similar components, where:

Figure 1 is a schematic illustration of the operation of a hybrid automatic retransmission request (HARQ) system;

FIG. 2 is a schematic illustration of an example of using a cyclic redundancy check (CRC) check value for a transport block and segmentation into code blocks; FIG.

3A is a schematic illustration of the operation of a transmitter for calculating a CRC of a transport block and a CRC of a code block as one embodiment of the invention in accordance with the principles of the present invention;

Fig. 3C is a schematic illustration of the operation of a transmitter for computing a transport block CRC and a code block CRC as another embodiment of the invention in accordance with the principles of the present invention;

4 is a schematic illustration of an example CRC of a transport block and a CRC of a code block as one embodiment of the invention in accordance with the principles of the present invention;

5A is a schematic illustration of the operation of a receiver for computing a CRC code block and a CRC transport block;

Fig. 5B is a schematic illustration of the operation of a receiver for computing a CRC of a code block and a CRC of a transport block as one embodiment of the invention in accordance with the principles of the present invention;

5C is a schematic illustration of the operation of a receiver for computing a CRC of a code block and a CRC of a transport block as another embodiment of the invention, consistent with the principles of the present invention;

6A is a schematic illustration of the operation of a transmitter for computing a CRC of a code block and a CRC of a transport block as yet another embodiment of the invention in accordance with the principles of the present invention;

6B is a schematic illustration of the operation of a receiver for computing a CRC of a code block and a CRC of a transport block as another embodiment of the invention in accordance with the principles of the present invention; and

7 is a schematic illustration of an example CRC of a transport block and a CRC of a code block as one embodiment of the invention in accordance with the principles of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Hybrid Automatic Repeat reQuest (HARQ) is widely used in communication systems to combat decoding failure and improve reliability. As shown in FIG. 1, each data packet is encoded using some forward error correction (FEC) scheme to create multiple subpackets. Each subpacket may contain only a portion of the encoded bits. If a failure occurs during the transmission of subpacket k, as indicated by the message “I do not acknowledge (NAK)” in the feedback channel confirming the transmission, a retransmission subpacket (subpacket k + 1) is sent to help the receiver decode the packet. Retransmission subpackets may contain code bits other than previous subpackets. The receiver can gently combine or jointly decode all received subpackets to increase the likelihood of successful decoding. Typically, the maximum number of transmissions is formed taking into account reliability, a possible delay in the transmission of a packet, and complexity of implementation.

In the 3rd Generation Partnership Project (3GPP) Long-Term Development System (LTE), when a transport block is large, it is segmented into a plurality of code blocks so that a plurality of coded packets can be created, which provides the advantage of being able to implement parallel processing or pipelining processing and providing a flexible compromise between power consumption and hardware complexity. The current technical solution for the HS-DSCH creates only one 24-bit cyclic redundancy check (CRC) value for the entire transport block in order to detect errors in this block. If multiple code blocks are created and transmitted in one transmission time interval (TTI), the receiver may correctly decode some of these code blocks and incorrectly decode others. In this case, the receiver will send a feedback message "I do not confirm (NAK)" to the transmitter, since the CRC check for this transport block gave a negative result. The relationship between the transport block, transport block CRC (TB CRC) and code block segmentation is shown in FIG. 2.

Assume that the L-bit polynomial CRC is used to create the CRC. We denote the generating polynomial CRC as

(1)

(one)

In general, for a message:

(2)

(2)

CRC coding is performed in a systematic manner. Denote the CRC parity bits in the indicated message as p ₀ , p ₁ , ..., p _L-1 , which can also be represented as polynomials:

(3)

(3)

The polynomial p (x) for CRC can be calculated by shifting the indicated message by L bits and then dividing the resulting sequence by the generating polynomial g (x). The remainder is the message CRC m (x). In mathematical form

(4)

(four)

where q (x) is the quotient of dividing m (x) · x ^L by g (x). When rearranging the terms of the above equation, the polynomial

(5)

(5)

gives a remainder of 0 when divided by g (x).

Note that if each bit in the message is binary, then the message can be represented as a polynomial defined over the Galois binary field (GF (2)). In this case, the operation '+' and '-' are equivalent. In other words, if the message bits are binary, then messages with an attached CRC control value can be represented either as m (x) · x ^L + p (x), or as m (x) · x ^L - p (x). In the further description of this invention, let us assume for convenience that the message bits are binary. However, the ideas disclosed in this invention are, of course, applicable to non-binary message bits.

The invention provides methods and apparatus for calculating a plurality of CRC control values for transmission, increasing transmission reliability and reducing transmitter and receiver complexity.

Aspects, features and advantages of the invention will become apparent from the following detailed description, illustrated by several specific embodiments of the invention, including the best option contemplated for implementing the invention. The invention can also be carried out according to other variants, and its individual details can be modified in various obvious aspects, provided that all these changes do not go beyond the essence and scope of the invention. Accordingly, the drawings and their description should be considered by nature as illustrations and not as limitations. The invention is illustrated by an example in the accompanying drawings, which is not a limitation. The following illustrations use the data channel in LTE systems as an example. However, the technique shown here, of course, can be used on another channel in LTE systems and other data channels, control channels, or other channels in other systems where this may find application.

First, we illustrate the concept of a transport block, a code block, a cyclic redundancy check (CRC) reference value for a transport block, and a code block CRC. A portion of the coding processing chain using the CRC of the transport block, but not the CRC of the code block, is shown in FIG. 3A. A transport block consists of a bit stream. At step 210, the transport block CRC is calculated and attached to the bitstream. Many transport blocks in the transmission time interval can be sequentially coupled (step 220), if necessary. If the size of the transport block (or interlocked transport blocks) exceeds Z (the maximum size of the considered code block), then segmentation is performed for the transport block (or interlocked transport blocks) (step 220) into code blocks. An example of the resulting code blocks is shown in FIG. 2. In step 230, CRC code blocks are calculated and attached to each of the code blocks. Then, before transmitting the code blocks, channel coding is performed (step 240), as well as a hybrid HARQ request at the physical layer and rate matching (step 250).

3B shows a portion of a coding processing sequence using a transport block CRC and a code block CRC. In step 310, the transport block CRC is calculated and attached to the bitstream. At 320, bit interleaving is performed in the transport block. In step 330, multiple transport blocks in a transmission time interval (TTI) are sequentially coupled and segmentation into code blocks is performed for the transport block (or concatenated transport blocks) (step 330). Next, code blocks CRCs are calculated and CRCs are attached to each of the code blocks (step 340). Then, before transmitting the code blocks, channel coding is performed (step 350), as well as a hybrid HARQ request at the physical layer and rate matching (step 360).

In another example shown in FIG. 3C, the transport block CRC is calculated and attached to the bitstream (step 410). A plurality of transport blocks in a transmission time interval (TTI) are successively concatenated (step 420) and segmented into code blocks for the transport block (or concatenated transport blocks) (step 420). Interleave the bits in the transport block (step 430). Then, the code block CRCs are calculated and attached to each of the code blocks (step 440). Then, before transmitting the code blocks, channel coding is performed (step 450), as well as a hybrid HARQ request at the physical layer and rate matching (step 460).

However, note that in the subsequent embodiments described in this invention, the transport blocks may or may not contain the CRC of the transport block until the transport blocks are concatenated or segmented into code blocks. After segmentation into code blocks, CRCs may be created for some or all of the code blocks. For illustrative purposes, assume that a code block CRC is created for each code block, although the ideas disclosed in this invention are, of course, applicable in other cases. For simplicity, we assume that there is only one transport block. However, all variations in this invention apply to cases where there are multiple transport blocks and clutch transport blocks. Also note that all the options in this invention are applicable for calculating CRC in both the transmitter and the receiver.

Figure 4 shows an example of attaching a transport block CRC (TB CRC) and a code block CRC (CB CRC). CB CRC can be used to verify that the code block is decoded correctly and to terminate additional iterations of turbo decoding by the turbo decoder if the CB CRC test is successful. Without the use of CB CRC, a turbo decoder can perform the maximum number of iterations for each code block. Assuming that for a plurality of code blocks, a pipelined processing option at the receiver is adopted, then the code blocks are decoded sequentially. In the case when there is only one confirmation channel for the transport block, there will be no confirmation for it (that is, the message “I do not confirm” will take place), as long as there is an error in at least one code block. If, after the maximum number of iterations, the CRC check for the code block gives a negative result, the receiver may skip decoding the remaining code blocks and send a “do not confirm” message. In the absence of CB CRC, the receiver may continue to decode other code blocks even though one code block already has an error. After decoding all code blocks, the receiver can check the TB CRC reference value to find that there is an error in the transport block. Therefore, the introduction of a CB CRC check can reduce the number of unnecessary iterations of turbo decoding at the receiver, resulting in energy savings and simplified processing. On the other hand, with each use of CB CRC, the probability of erroneous CRC determination increases, which can lead to the termination of decoding iterations when the code block was incorrectly decoded. In addition, this error cannot be detected without a transport block CRC (TB CRC). Note that an undetected error seriously affects communication, since it will propagate to higher levels of the communication protocol and initiate retransmissions at a higher level, which reduces the overall quality of the communication channel and impairs user interaction. Thus, the TB CRC reference value is used to reduce the frequency of erroneous CRC determination for the entire transport block.

In the first embodiment, according to the principles of the invention, the first order of multiple bits is used in calculating the first CRC, and the second order of multiple bits is used in calculating the second CRC. In the example shown in FIG. 4, in order to facilitate implementation, the same generating polynomial for CRC can be used to create both TB CRC and CB CRC. In this case, if the same order or bit sequence is used to create TB CRC and CB CRC, then an erroneous sequence leading to erroneous detection in CB CRC can also lead to erroneous detection in TB CRC. To avoid this, the bits are reordered after creating the TB CRC, but do so before creating the CB CRC. Note that bit reordering / interleaving can only be applied to a portion of information bits or TB CRC bits. For example, bit reordering / interleaving can only be applied to information bits, but not to TB CRC bits. Alternatively, bit reordering / interleaving can be applied to both information bits and TB CRC bits.

3B and 3C show two examples of how bit reordering / interleaving in a processing sequence at a transmitter can be performed. 3B, interleaving / reordering of a transport block bitstream is performed before segmentation into code blocks; while in FIG. 3C, interleaving / reordering is applied to each code block after segmentation into code blocks. Reordering / interleaving at the entire transport block level, as shown in FIG. 3B, may cause a processing time delay for the entire transport block; reordering / interleaving at the code block level, as shown in FIG. 3C, may cause a delay in processing time of one code block.

Similarly, to further reduce the delay from interleaving, reordering / interleaving patterns that have a smaller range than the code block can also be used. For example, a simple reordering pattern may be the replacement of at least one bit with another bit in a stream. Note that such a reordering pattern introduces a delay due to interleaving of no more than one bit if the two bits are adjacent. Of course, a replacement operation can be applied to more than one bit in a stream. In fact, this operation can be applied to all bits in a stream. One example is the replacement of even bits with odd bits. Again, the reordering / interleaving of bits can be applied only to part or all of the information bits, but not to TB CRC bits. Alternatively, bit reordering / interleaving can be applied to both information bits and TB CRC bits.

Alternatively, TB CRC can be calculated using the natural bit order, and CB CRC can be calculated using the reverse bit order. The reverse order can be applied before the segmentation of the transport block. Alternatively, the reverse order may be applied after segmentation of the transport block. Also, TB CRC can be calculated using the reverse bit sequence, and CB CRC can be calculated using the natural order of the bit sequence. Again, the reverse bit order can only be applied to information bits, but not to TB CRC bits. Alternatively, the reverse bit order can be applied to both information bits and TB CRC bits. Note that CB CRCs are calculated based on the reverse order of the bit sequence in the corresponding code block. Also note that the reverse bit order applied to information bits with or without TB CRC bits is applicable only in the case of calculating CB CRC based on the reverse bit order.

According to another alternative embodiment, the reordering / interleaving of bits may be implemented as part of the block clutch / segmentation. For example, if segmentation of a transport block (together with a CRC of a transport block) into a plurality of code blocks is necessary, then it is possible to scatter CRC bits of a transport block into each code block. This provides efficient interleaving, but this approach can be challenged since no additional block is created in the encoding chain.

5A-5C show examples of how a receiver performs reordering / interleaving of a bitstream between CB CRC calculation and TB CRC calculation. 5A shows a portion of the processing at the receiver assuming that between the execution of the CB CRC check and the TB CRC check, bit reordering / interleaving is not performed. In particular, in FIG. 5A, when a wireless terminal (i.e., a base station or user equipment unit) receives a data channel signal, a hybrid physical HARQ request and rate matching are first performed in step 510. Then code blocks of the data channel signal are decoded (step 520). Check the code block CRC to find out if the code blocks are decoded correctly (step 530). Then, code blocks are coupled to the transport block (step 540). The transport block CRC is checked to see if it is decoded correctly. If bit reordering / interleaving is applied on the transmitter side, as shown in FIGS. 3B and 3C, then the receiver performs bit reordering / deinterleaving, respectively, as shown in FIGS. 5B and 5C, respectively. 5B, reordering / deinterleaving (step 650) of the transport block bitstream after code block concatenation is performed (step 640); while in FIG. 5C, reordering / deinterleaving is performed for each code block (step 740) until code blocks are concatenated (step 750). Reordering / interleaving at the level of the entire transport block, as shown in FIG. 5B, may cause a delay in processing time for the entire transport block; reordering / interleaving at the code block level, as shown in FIG. 5C, may cause a delay in processing time of one code block.

Obviously, by combining the above embodiments of the invention in various ways, many other versions can be obtained without going beyond the scope of the invention.

In the second embodiment of the invention, according to its principles, when calculating the first CRC based on the first set of bits, the first generating polynomial for CRC is used, while when calculating the second CRC based on the second set of bits, the second generating polynomial for CRC is different from the first generating polynomial for CRC Again, it should be noted that FIG. 4 is used here as an example. There is one CRC transport block, namely CRC "A". In calculating the CRC “A” based on all information bits in the transport block designated as the bit stream S _TB , as shown in FIG. 4, where S _TB = S ₁ ∪ S ₂ ∪ S ₃ , the generating polynomial g ₁ (x) is used for CRC. There are three CRC code blocks, namely CRC “B”, CRC “C” and CRC “D”, respectively. The second generating polynomial g ₂ (x), which is different from g ₁ (x), is used in calculating the CRC “B”, “C” and “D” of the code block. CRC "B" is calculated based on the information bits in the first code block, which are indicated in this figure as a bit stream S ₁ ; CRC "C" is calculated based on the information bits in the second code block, which are indicated in this figure as a bit stream S ₂ ; CRC "D" is calculated based on the information bits in the third code block, which are indicated in this figure as the bit stream S ₃ , and CRC "A" of the transport block. Denote the bitstream obtained by coupling S ₃ and “A” as S ₄ , that is, S ₄ = S ₃ U “A”. In other words, the CRC “D” is calculated based on the bit stream S ₄ .

In this embodiment, the second plurality of bits may be a subset of the first plurality of bits. For example, the polynomial g ₂ (x) is used in computing CRC “B” based on S ₁ , while the polynomial g ₁ (x) is used in calculating CRC “A” based on S _TB . Bit stream S ₁ is a subset of bit stream S _TB .

Alternatively, the first plurality of bits may be an extended set of the second plurality of bits. For example, the polynomial g ₁ (x) is used in calculating CRC “A” based on S _TB, while g ₂ (x) is used in calculating CRC “A” based on S ₂ . Bit stream S _TB is an extended set of bit stream S ₂ .

As another alternative, the first plurality of bits may overlap with the second plurality of bits. For example, the polynomial g ₁ (x) is used in the calculation of CRC “A” based on S _TB, while g ₂ (x) is used in the calculation of CRC “A” based on S ₄ . The bit stream S _TB overlaps with the bit stream S ₄ , S _TB ∩ S ₄ = S ₃ .

The first CRC and the second CRC may have different lengths.

As an alternative, the first CRC and the second CRC may be the same length. For example, if the first CRC and the second CRC are 24 bits long, then the generating polynomials g ₁ (x) and g ₂ (x) for the CRC can be selected as follows:

As an alternative, the generating polynomials g ₁ (x) and g ₂ (x) for CRC can be selected as follows:

FIG. 6A shows operations in a transmitter using a generating polynomial g ₁ (x) for CRC to calculate a CRC of a transport block and a generating polynomial g ₂ (x) to calculate a CRC of a code block. 6B shows corresponding operations at the receiver. In particular, as shown in FIG. 6A, the transport block CRC is calculated on the transmitter side using the generating polynomial g ₁ (x) for the CRC, and then attach it to the transport block (step 810). The transport block may be segmented into multiple code blocks (step 820). Multiple CRC code blocks are calculated by using the generating polynomial g ₂ (x) for the CRC (step 830). Then, channel coding is performed (step 840) and a hybrid HARQ request at the physical layer and rate matching (step 850). As shown in FIG. 6B, on the receiver side, when receiving a data channel signal, a hybrid HARQ request at the physical layer and rate matching are first performed (step 910). Then, code blocks of the data channel signal are decoded (step 920). At step 930, the CRC of the code blocks of the generating polynomial g ₂ (x) for the CRC is checked to see if the code blocks are decoded correctly. Then, code blocks are coupled to the transport block (step 940). In step 950, the transport block CRC is checked using the generating polynomial g ₁ (x) for the CRC to find out if the transport block is decoded correctly.

However, it is noted that the ideas disclosed in this invention are not limited to computing CRC transport blocks and CRC code blocks. For example, the idea of using different generating polynomials for CRCs to compute different CRCs based on overlapping bit streams can generally be applied to other technical solutions where there are many CRCs.

For example, as shown in FIG. 7, a transport block CRC is not calculated until it is segmented into code blocks. The transport block is segmented into three code blocks. A code block CRC is calculated for each of the three code blocks. CB0_CRC is obtained from the bits in code block 0 using the generating polynomial g ₁ (x); CB1_CRC is obtained from the bits in code block 1 using the generating polynomial g ₁ (x); CB2_CRC is obtained from the bits in code block 0, code block 1 and code block 2 using the generating polynomial g ₂ (x), which is different from g ₁ (x). CB0_CRC can be used to stop iteration of turbo decoding or error detection for code block 0, CB1_CRC can be used to stop iterations of turbo decoding or error detection for code block 1, CB2_CRC can be used to stop iterations of turbodecoding or error detection for code block 2. At the same time CB2_CRC provides error detection for the entire transport block.

Obviously, by combining in various ways the above embodiments of the invention, many other versions can be obtained without departing from the scope of the invention.

Claims (49)

1. A communication method comprising
computing a cyclic redundancy check value for the transport block based on information bits in the transport block by using the selected generating polynomial for the cyclic redundancy check value and attaching the cyclic redundancy code check value of the transport block to the transport block;
segmenting a transport block having a cyclic redundancy check code value of the transport block into at least one code block;
calculating at least one cyclic redundancy check value for the code block based on at least one code block by using the selected generating polynomial for the cyclic redundancy check value, wherein one cyclic redundancy check value for the code block is calculated based on one corresponding code block; and
transmitting at least one code block associated with a transport block having a cyclic redundancy check code value of a transport block, and at least one cyclic redundancy check code value for a code block, through at least one transmit antenna, wherein information bits in the transport block are interleaved after calculating the control value of the cyclic redundancy code for the transport block, but before calculating at least one control value of the cyclic redundancy code o redundant code for the code block. 2. The method according to claim 1, comprising interleaving the information bits in the transport block together with the bits in the control value of the cyclic redundancy code for the transport block. 3. The method according to claim 1, comprising interleaving information bits in a transport block without interleaving bits in a control value of a cyclic redundancy code for a transport block. 4. The method according to claim 1, comprising interleaving information bits in the transport block before segmenting the transport block into at least one code block. 5. The method according to claim 1, comprising interleaving the information bits in the transport block after segmenting the transport block into at least one code block. 6. The method according to claim 1, comprising interleaving information bits in a transport block by applying interleaving patterns having a shorter duration than the length of the code block. 7. The method according to claim 1, comprising interleaving information bits in a transport block by replacing at least one information bit with another information bit in a transport block. 8. The method according to claim 1, comprising interleaving information bits in a transport block by replacing even information bits with odd information bits in a transport block. 9. A communication method comprising
calculating a cyclic redundancy check code value for a transport block for a sequence of information bits in a transport block by using a selected generating polynomial for a cyclic redundancy code check value and attaching a cyclic redundancy code check value to a transport block;
segmentation of a sequence of information bits in a transport block having a control value of a cyclic redundancy code of the transport block by at least one code block;
calculating at least one cyclic redundancy check value for the code block based on at least one code block by using the selected generating polynomial for the cyclic redundancy check value, wherein one cyclic redundancy check value for the code block is calculated based on one corresponding code block; and
transmitting at least one code block associated with a transport block having a cyclic redundancy check code value of a transport block, and at least one cyclic redundancy check code value for a code block, through at least one transmit antenna, wherein either the bit sequence in the transport block or the bit sequence in at least one code block is arranged in the reverse order before calculating the corresponding control value in a loop redundant code. 10. The method according to claim 9, containing
computing a cyclic redundancy check value for the transport block based on the natural order of the bit sequence in the transport block; and
computing a cyclic redundancy check value for the code block based on the reverse bit sequence in the code block. 11. The method of claim 10, comprising reverse ordering the bit sequence in the transport block together with the bit sequence in a cyclic redundancy check code value for the transport block before segmenting the transport block into at least one code block. 12. The method of claim 10, comprising reverse ordering the bit sequence in the transport block without reverse ordering the bit sequence in a cyclic redundancy check code value for the transport block before segmenting the transport block into at least one code block. 13. The method according to claim 10, containing the reverse ordering of the bit sequence in the corresponding code block after segmenting the transport block into at least one code block. 14. The method according to claim 9, containing
computing a cyclic redundancy check value for the transport block based on the reverse bit sequence in the transport block; and
computing a cyclic redundancy check value for the code block based on the natural order of the bit sequence in the code block. 15. A communication method comprising
computing a cyclic redundancy check value for the transport block based on information bits in the transport block by using the selected generating polynomial for the cyclic redundancy check value and attaching the cyclic redundancy code check value of the transport block to the transport block;
segmenting a transport block having a cyclic redundancy check code value of the transport block into at least one code block;
the distribution of bits in the control value of the cyclic redundancy code for the transport block in each of the code blocks;
calculating a plurality of cyclic redundancy check values for the code block based on the plurality of code blocks by using the selected generating polynomial for the cyclic redundancy check value, each cyclic redundancy check value for the code block being calculated based on the corresponding code block; and
transmitting a plurality of code blocks associated with a transport block having a cyclic redundancy check code value of a transport block, and a plurality of cyclic redundancy code control values for a code block, via at least one transmit antenna. 16. A method of communicating, comprising
receiving at least one code block of the bit sequence and at least one cyclic redundancy check value for the code block through at least one receiving antenna;
decoding at least one code block;
checking at least one cyclic redundancy check value for the code block by using the selected generating polynomial for the cyclic redundancy check value to determine if at least one code block is decoded correctly;
when correctly decoding at least one code block, the serial connection of this at least one code block to create a transport block; and
checking the cyclic redundancy check value for the transport block by using the selected generating polynomial for the cyclic redundancy check value to determine whether the transport block is decoded correctly, and the bit sequence in either at least one code block or the transport block is reordered after checking the control value of the cyclic redundant code of at least one code block, but before checking the control value, the cycle Cesky redundancy for the transport block. 17. The method according to clause 16, containing the reordering of the bit sequence in the transport block after the serial connection of at least one code block. 18. The method according to clause 16, containing the reordering of the bit sequence in at least one code block before serial connection of at least one code block. 19. A communication method comprising
computing a plurality of cyclic redundancy check values for a plurality of bits by using a plurality of generating polynomials for a cyclic redundancy check value, the first generating polynomial for a cyclic redundancy check value being used to calculate a first cyclic redundancy check value based on a plurality of transport block bits, and a second the generating polynomial for the cyclic redundancy check value is used to subtract dividing a second cyclic redundancy check value based on a plurality of bits of a code block; and
transmitting a plurality of bits and a plurality of cyclic redundancy check values through at least one transmit antenna. 20. The method according to claim 19, containing the first plurality of bits, which is a subset of the second plurality of bits. 21. The method according to claim 19, containing the first plurality of bits, which is an extended set of the second plurality of bits. 22. The method according to claim 19, comprising a first plurality of bits overlapping a second plurality of bits. 23. The method according to claim 19, containing the first control value of the cyclic redundancy code and the second control value of the cyclic redundancy code having different lengths. 24. The method according to claim 19, containing the first control value of the cyclic redundancy code and the second control value of the cyclic redundancy code having the same length. 25. The method according to paragraph 24, containing the first control value of the cyclic redundancy code and the second control value of the cyclic redundancy code having a length of 24 bits, as well as the first generating polynomial g ₁ (x) for the control value of the cyclic redundancy code and the second generating polynomial g ₂ (x) for the control value of the cyclic redundancy code, which are respectively set in the form:
g ₁ (x) = x ²⁴ + x ²³ + x ⁶ + x ⁵ + x + 1 and
g ₂ (x) = x ²⁴ + x ²³ + x ¹⁴ + x ¹² + x ⁸ +1. 26. The method according to paragraph 24, containing the first control value of the cyclic redundancy code and the second control value of the cyclic redundancy code having a length of 24 bits, as well as the first generating polynomial g ₁ (x) for the control value of the cyclic redundancy code and the second generating polynomial g ₂ (x) for the control value of the cyclic redundancy code, which are respectively set in the form:
g _l (x) = x ²⁴ + x ²³ + x ¹⁴ + x ¹² + x ⁸ +1 and
g ₂ (x) = x ²⁴ + x ²³ + x ⁶ + x ⁵ + x + 1. 27. A communication method comprising
computing a cyclic redundancy check value for a transport block based on a plurality of bits of a transport block by using a first generating polynomial for a cyclic redundancy check value;
segmentation of the transport block into at least one code block;
calculating at least one cyclic redundancy check value for a code block based on a plurality of bits of at least one code block by using a second generating polynomial for a cyclic redundancy check value, wherein one cyclic redundancy check value for a code block is calculated based on one corresponding code block; and
transmitting at least one code block and at least one cyclic redundancy check value for the code block through at least one transmit antenna. 28. A communication method comprising: receiving at least one code block of a bit sequence and at least one cyclic redundancy check value for a code block through at least one receiving antenna;
decoding at least one code block;
checking at least one cyclic redundancy check value for the code block by using a second generating polynomial for the cyclic redundancy check value to determine if the at least one code block is correctly decoded;
when correctly decoding at least one code block, the serial connection of this at least one code block to create a transport block; and
checking the cyclic redundancy check value for the transport block by using the first generating polynomial for the cyclic redundancy check value to determine if the transport block is decoded correctly. 29. A wireless terminal in a communication system, comprising
a cyclic redundancy check code generator for a transport block calculating a cyclic redundancy check code value for a transport block based on information bits in a transport block by using a selected generating polynomial for a cyclic redundancy check code value and attaching a cyclic redundancy check code value of a transport block to a transport block;
a code block generator segmenting a transport block having a cyclic redundancy code of the transport block by at least one code block;
a generator of at least one cyclic redundancy check code value for a code block, computing at least one cyclic redundancy check code value for a code block based on at least one code block by using a selected generating polynomial for a cyclic check value a redundant code, wherein one cyclic redundancy check code value for a code block is calculated based on one corresponding code block;
an interleaver interleaving information bits in the transport block after the generator calculates the cyclic redundancy check code for the transport block by the generator of the cyclic redundancy check code for the transport block, but before the cyclic redundancy code checksum for the code block generates at least one cyclic redundancy check code redundant code for a code block; and
at least one antenna transmitting at least one code block associated with a transport block having a cyclic redundancy check code value of a transport block, and at least one cyclic redundancy check code value for a code block. 30. The wireless terminal of claim 29, comprising an interleaver interleaving information bits in a transport block together with bits in a cyclic redundancy check code value for a transport block. 31. The wireless terminal of claim 29, comprising an interleaver interleaving information bits in a transport block without interleaving bits in a cyclic redundancy check code value for a transport block. 32. The wireless terminal of claim 29, comprising an interleaving unit interleaving information bits in a transport block before segmenting the transport block into at least one code block. 33. The wireless terminal according to clause 29, containing the interleaving unit, interleaving information bits in the transport block after segmentation of the transport block, at least one code block. 34. The wireless terminal of claim 29, comprising an interleaver interleaving information bits in a transport block by applying interleaving patterns having a shorter duration than a code block length. 35. A wireless terminal in a communication system, comprising
a cyclic redundancy check code generator for a transport block, calculating a cyclic redundancy check code value for a transport block for a sequence of information bits in a transport block by using a selected generating polynomial for a cyclic redundancy check value and attaching a cyclic redundancy check code value of a transport block to a transport block;
a code block generator segmenting a sequence of information bits in a transport block having a control value of a cyclic redundancy code of the transport block by at least one code block;
a cyclic redundancy check code generator for a code block, computing at least one cyclic redundancy check code for a code block based on at least one code block by using a selected generating polynomial for a cyclic redundancy check value, and one control the cyclic redundancy value for the code block is calculated based on one corresponding code block;
a reordering unit that reorders either a bit sequence in a transport block or a bit sequence in at least one code block before either a cyclic redundancy check value generator for a transport block or a cyclic redundancy check value generator for a code block computes the corresponding cyclic redundancy check value; and
at least one antenna transmitting at least one code block associated with a transport block having a cyclic redundancy check code value of a transport block, and at least one cyclic redundancy check code value for a code block. 36. The wireless terminal according to clause 35, containing
a cyclic redundancy check code generator for a transport block calculating a cyclic redundancy check code value for a transport block based on the natural order of the bit sequence in the transport block; and
a cyclic redundancy check code generator for a code block, calculating a cyclic redundancy check code value for a code block based on the reverse order of the bit sequence in the code block. 37. The wireless terminal according to clause 35, containing
a cyclic redundancy check code generator for a transport block calculating a cyclic redundancy check code value for a transport block based on the reverse bit sequence in the transport block; and
a cyclic redundancy check code generator for a code block computing a cyclic redundancy check code value for a code block based on the natural order of the bit sequence in the code block. 38. A wireless terminal in a communication system comprising a cyclic redundancy check value generator
for a transport block, calculating a cyclic redundancy check code value for a transport block based on information bits in a transport block by using a selected generating polynomial for a cyclic redundancy code check value and attaching a cyclic redundancy code check value to a transport block;
a code block generator segmenting a transport block having a control value of a cyclic redundancy code of the transport block by at least one code block;
a distribution unit allocating bits in a cyclic redundancy check code value for a transport block to each of the code blocks;
a cyclic redundancy check code generator for a code block computing a plurality of cyclic redundancy check values for a code block based on a plurality of code blocks by using a selected generating polynomial for a cyclic redundancy check value, each cyclic redundancy check value for a code block is calculated based on corresponding code block; and
at least one antenna transmitting a plurality of code blocks associated with a transport block having a cyclic redundancy check code value of a transport block, and a plurality of cyclic redundancy code check values for a code block. 39. A wireless terminal in a communication system, comprising
at least one antenna receiving at least one code block of a bit sequence and at least one cyclic redundancy check value for a code block;
a code block decoding unit decoding at least one code block;
a cyclic redundancy check code check unit for a code block that checks at least one cyclic redundancy check code value for a code block by using a selected generating polynomial for a cyclic redundancy check value to determine if at least one code code is decoded correctly block;
a transport block generator that connects at least one code block in series to create a transport block;
a cyclic redundancy check code check unit for a transport block verifying a cyclic redundancy check code value for a transport block by using a selected generating polynomial for a cyclic redundancy check code value to determine if the transport block is decoded correctly;
a reordering unit reordering a bit sequence in either at least one code block or a transport block after the verification unit checks the cyclic redundancy check value for the code block by at least one cyclic redundancy check value for the code block, but before checking by the verification unit of the control value of the cyclic redundancy code for the transport block of the control value of the cyclic redundancy code for the transport block. 40. The wireless terminal according to claim 39, comprising a reordering unit reordering the bit sequence in the transport block after the serial connection of the at least one code block by the transport block generator. 41. The wireless terminal according to claim 39, comprising a reordering unit reordering a bit sequence in at least one code block prior to serial connection of at least one code block by a transport block generator. 42. A wireless terminal in a communication system, comprising
at least one cyclic redundancy check value generator calculating a plurality of cyclic redundancy check values for a plurality of bits by using a plurality of generating polynomials for a cyclic redundancy check value, the first generating polynomial for a cyclic redundancy check value being used to calculate the first control value cyclic redundancy code based on the many bits of the transport block, and the second generating nogochlen reference value for the cyclic redundancy code is used for calculating a second reference value of the cyclic redundancy code based on the plurality of bits of the code block; and
at least one antenna transmitting a plurality of bits and a plurality of cyclic redundancy check values. 43. The wireless terminal of claim 42, comprising a first plurality of bits, which is a subset of the second plurality of bits. 44. The wireless terminal of claim 42, comprising a first plurality of bits, which is an extended set of a second plurality of bits. 45. The wireless terminal of claim 42, comprising a first plurality of bits overlapping a second plurality of bits. 46. The wireless terminal of claim 42, comprising a first cyclic redundancy check value and a second cyclic redundancy check value having different lengths. 47. The wireless terminal of claim 42, comprising a first cyclic redundancy check value and a second cyclic redundancy check value having the same length. 48. A wireless terminal in a communication system, comprising
a cyclic redundancy check code generator for a transport block calculating a cyclic redundancy check code value for a transport block based on a plurality of bits of a transport block by using a first generating polynomial for a cyclic redundancy check value;
a code block generator segmenting a transport block into at least one code block;
a generator of at least one cyclic redundancy check code value for a code block, computing at least one cyclic redundancy check code value for a code block based on a plurality of bits of at least one code block by using a second generating polynomial for the control cyclic redundancy code values, wherein one cyclic redundancy check code value for a code block is calculated based on one corresponding code block; and
at least one antenna transmitting at least one code block and at least one cyclic redundancy check value for the code block. 49. A wireless terminal in a communication system, comprising
at least one antenna receiving at least one code block of a bit sequence and at least one cyclic redundancy check value for a code block;
a code block decoding unit decoding at least one code block;
a cyclic redundancy check code check unit for a code block that checks at least one cyclic redundancy check code value for a code block by using a second generating polynomial for a cyclic redundancy check value to determine if at least one code code is decoded correctly block;
a transport block generator that connects at least one code block in series to create a transport block; and
a cyclic redundancy check code check unit for a transport block verifying a cyclic redundancy check code value for a transport block by using a first generating polynomial for a cyclic redundancy check code value to determine whether the transport block is decoded correctly.

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