RU2367001C1 - System for access to memory with adaptively adjustable speed of operation - Google Patents

Abstract

FIELD: physics, computer technology.

SUBSTANCE: system comprises common access busbar, external memory, which is connected to common access memory, module of synchronising clock frequency signal control, main master-module that preserves exclusive access to memory during system operation in mode of energy preservation, master-modules connected to busbar and generating requests for access to it, busbar arbiter. It is equipped with counting device of busbar useful cycles, counting device of busbar full cycles and device for comparison and control of clock frequency of busbar arbiter and external memory.

EFFECT: provision of automatic selection of operational speed.

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Description

The invention relates to computing, and in particular to the field of processing streaming data in a multiprocessor system on a chip.

The field of processing streaming data (compression, decompression of video) is a rapidly developing area. The resolution of equipment (cameras and high-definition screens) and the quality of image processing are increasing. At the same time, the devices become more compact, the requirements for the energy consumption of the product increase, and the means of satisfying them are still insufficient in full.

Known technical solutions [1, 2] that access the shared external memory without adjusting the speed of rotation, which is a significant drawback of this solution of systems, because they have high power consumption, which affects the consumer properties of the system.

The closest technical solution is a system that uses a bus arbiter to turn off [3], including:

- shared bus

- external memory connected to the shared bus,

- a clock control signal module,

- the main master module that retains exclusive access to memory when the system is in energy conservation mode,

- master modules connected to the bus and generating requests for access to it,

- turning off the master module,

- tire arbiter.

Functional diagram of the prototype [3] is presented in figure 1.

The notation is made in the presented diagram, where: 1 is the shared bus, 2 is the external memory, 3 is the clock synchronization signal control module, 4 is the main master module that maintains exclusive access to the memory when the system is operating in energy conservation mode, 5 - master modules connected to the bus and generating requests for access to it, 6 - turning off the master module, 7 - bus arbiter.

As follows from the description of the prototype system [3] and from the functional diagram presented in figure 1, the system has disadvantages:

1. Activity on the bus and determining the conditions for the system to enter the energy conservation mode are observed programmatically by external means. External speed control significantly reduces the speed and responsiveness of the system to changes.

2. In the energy conservation mode, the right to access the bus belongs exclusively to one master module 4, the bus is not used, which significantly reduces the functionality of the system.

The objective of the invention is to find a technical solution, which consists in the automatic selection of the speed of the system with external memory, increasing the speed of tuning the system to the general load level, and providing access to the bus of all master modules in all operating modes as a result of adding useful bus clocks to the system of the calculating device , a full bus clock counting device, and a comparison and control device.

To achieve the named technical result in a system using a bus arbiter to turn off [3], containing:

- shared bus

- external memory connected to the shared bus,

- a clock control signal module,

- the main master module that retains exclusive access to memory when the system is in energy conservation mode,

- master modules connected to the bus and generating requests for access to it,

- tire arbiter

include blocks that are the hallmarks of the invention:

- calculator of useful bus ticks,

- total bus clock counter,

- a device for comparing and controlling the clock frequency of the bus arbiter and external memory.

Patent studies have shown that the combination of features of the invention is new, which proves the novelty of the claimed device.

In addition, patent studies have shown that in the literature there are no data showing the influence of the distinguishing features of the claimed invention on the achievement of a technical result, which confirms the inventive step of the proposed device design.

This set of distinctive features allows to achieve the named technical result.

The functional diagram of the device according to the alleged invention is illustrated in figure 2.

The device shown in figure 2, contains: 1 - bus, 2 - external memory, 3 - control module, 4 - main master module, 5 - master modules, 7 - bus arbiter, 8 - calculating device useful bus ticks, 9 - calculating device for full bus clocks, 10 - device for comparing and controlling the clock frequency of the bus arbiter and external memory.

In our system, where the load on the shared memory array varies depending on the mode, you can significantly save energy by reducing the speed of working with shared external memory to the minimum necessary for this mode. Sustainable long-term changes in the load level on the shared external memory are also possible when working in the selected mode.

The logic of the access bus to the shared external memory with adaptive adjustable speed of operation is discussed below.

Initial conditions: the maximum clock frequency of the external memory and the bus arbiter is set. The streaming data processing system (multiprocessor system on a chip) works according to its own algorithm. Each master module requests access to external memory and accesses it through a bus arbiter. During the access of each master module, the counting device of useful bus clocks (8) summarizes the total activity of all K devices. At the same time, the “k” of the full bus clocks (the full possible bandwidth of the bus and external memory) is counted by the total bus clock counter (9).

The comparison device (10) finds the ratio of the useful exchange rate “K” on the bus to the total possible speed “k” at a given (maximum) clock frequency. The ratio will be less than (or equal to) one.

With a smaller ratio (incomplete loading of the bus), the comparing module sets another (lower) value of the clock frequency of the bus arbiter and external memory.

The grid of values “N” of the clock frequencies “F (N)” is defined as a incremental increase in the minimum base clock frequency of the system. So, for example, for a video processing system using a standard external SDRAM memory with a maximum clock frequency of up to 200 MHz, it is proposed to use a frequency grid step equal to 27 MHz (a multiple of the frequency of output and reception of input data).

In this system, the frequency grid step will be as follows:

Grid Step Number (N) Clock Frequency F (N) (MHz) The ratio Mmin (N) = F (N) / F (N + 1) one 27 0.5 2 54 0.66 3 81 0.75 four 108 0.8 5 135 0.833 6 162 0.857 7 189 0.875 8 (216) -

In the device for comparing and controlling the clock frequency of the bus arbiter and external memory (10), the values and ratios K (N) and k (N) are compared and, if K (N) / k (N) <Mmin (N), then the next smaller according to the grid, the value of the clock frequency; otherwise, for K (N) / k (N) = 1, the next higher value of the clock frequency is selected. If Mmin (N) = <K (N) / k (N) <1, then the value of the clock frequency grid does not change.

Thus, the speed of working with external memory is adaptively adjusted to the bus load level, power consumption is minimized when the external memory is operating at lower speeds.

The implementation example described above is a special case. The proposed system can be used for any other type of tasks without going beyond the scope of patent claims.

Literature

1. Philips semiconductors, Integrated MPEG AVGD decoders SAA7215; SAA7216; SAA7221, Preliminary specification, 2001 Mar 28, page 2. www.platan.ru/pdf/1dist/philips/SAA7215_7216_7221_

2. Robert Cravotta, 2002 DSP directory, www.ednmag.com, paper edn040402, April 2002 N4, page 56, TEXAS INSTRUMENTS 'TMS320DSCX FAMILY.

3. US Patent Application 20070067652 System using bus arbiter to power down.

Claims (1)

A memory access system with adaptively adjustable operating speed, comprising a shared bus, an external memory connected to a shared bus, a clock synchronization signal control module, a main master module that preserves exclusive memory access when the system is operating in energy conservation mode, a master -modules connected to the bus and generating requests for access to it, bus arbiter, characterized in that it is equipped with a counting device of useful bus clocks, a counting device of full bus clocks and bus roystvom comparison and control the clock frequency of the bus arbiter and the external memory.

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