RU2010414C1 - Digital synthesizer of sinusoidal signals - Google Patents

Abstract

FIELD: radio engineering. SUBSTANCE: digital synthesizer of sinusoidal signals has variable frequency generator, fixed frequency generator, change-over switch, first and second formers of controlling signals, unit of control over direction of count, reversible counter, buffer amplifier, permanent storage, digital-to-analog converter, polarity change-over switch, controlled low-pass filter, comparator and D flip-flop. D input of flip-flop is connected to its inversion output. EFFECT: increased reliability thanks to expulsion of some elements and to decrease of some functional couplings. 2 dwg

Description

 The invention relates to radio engineering and can be used to generate electrical signals of a sinusoidal shape with an arbitrarily changing or oscillating frequency.

 Known digital frequency synthesizer with frequency modulation, containing keys, integrating filters, low-pass filter, tunable generator, frequency divider with variable division coefficient, switches, phase detector, modulated signal source, controlled attenuators, voltage bias unit, integrator, phase modulator, comparators , OR element, control unit, reference generator, delay element, frequency setting unit and standard voltage generator [1].

 The disadvantage of this device is the great complexity of execution, which leads to a decrease in the reliability of uptime.

 Closest to the proposed technical essence is a digital sinusoidal signal synthesizer containing a series-connected variable frequency generator, a switch, a direction control unit, a reversible counter, a buffer amplifier, a constant memory unit, a digital-to-analog converter, a polarity switch and a low-pass filter, a fixed-frequency generator the output of which is connected to another switch input, a counting trigger, the first and second control signal conditioners, the input of the counting trigger is connected to the input of the reversible counter, the clock input and output of the loan of which are connected respectively to the output of the switch and the other input of the counting direction control unit, the input of the second driver of control signals is connected to the output of the switch, the control input of which is connected to the output of the first driver of control signals, output the second driver of the control signals is connected to the control input of the managed low-pass filter, a comparator, the first input of which is connected to the output the digital-to-analog converter, and a D-trigger, the output of which is connected to the control input of the polarity switch, while the second input of the comparator is connected to a common bus, and the C- and D-inputs of the D-trigger are connected to the outputs of the comparator and counting trigger, respectively [2].

 The disadvantage of this synthesizer is also a large number of elements and the connections between them, which leads to a decrease in the reliability of the failure-free operation of the device.

 The purpose of the invention is to increase reliability by eliminating certain elements and reducing the number of functional relationships.

 In FIG. 1 shows a functional circuit diagram of a digital synthesizer of sinusoidal signals; in FIG. 2 - time diagrams of work.

 The digital sinusoidal signal synthesizer contains a variable frequency generator 1, a fixed frequency generator 2, a switch 3, a first driver 4 of the control signals, a unit 5 for controlling the direction of counting, a counter 6, a second driver for 7 control signals, a buffer amplifier 8, a block 9 of constant memory, digital-to-analog a converter (DAC) 10, a polarity switch 11, a controlled low-pass filter (LPF) 12, a comparator 13, a D-trigger 14.

A digital synthesizer of sinusoidal signals works as follows. Generator 1 includes a self-oscillating sawtooth voltage generator and a voltage-controlled generator (not shown) in series with it. At the output of the generator 1 there is a signal with a periodically smoothly changing frequency. At the output of the generator 2 there is a signal with a fixed frequency. Both signals are fed to switch 3, which transmits pulses from either generator 1 or generator 2. These pulses are fed to the inputs of the counting direction control unit 5, which generates the summing-subtracting signals of the reversing counter 6, as well as the inputs of the reversing counter 6 and the second shaper 7 control signals. Unit 5 controls the direction of the account determines the operating mode of the reversible counter 6 as follows. In the first quarter of the signal period, the reverse counter 6 operates in the addition mode, in the second quarter in the subtraction mode, in the third in the addition mode, in the fourth in the subtraction mode. A series of addresses generated by the reversible counter 6, enters through the buffer amplifier 8, which serves to convert signal levels, and also, if necessary, to increase the load capacity of the reversible counter, to block 9 of permanent memory. In permanent memory unit 9 previously recorded binary codewords corresponding discrete values of a sine function in the first quadrant, ie. E. Between the phase angles otθ ₁ = ⁰ ° to θ ₂ = ^{90 °.} In accordance with the incoming addresses, the read-only memory unit 9 in the first and third quarters of the period issues binary codes of the sine function values from θ ₁ = 0 ^о to θ ₂ = 90 ^о in the DAC 10, and in the second and fourth quarters of the period it issues to the DAC 10, which is unipolar, the binary codes of the values of the sine function are from θ ₁ = 0 ^о to θ ₂ = 90 ^о , and in the second and fourth quarters of the period from θ ₂ = 90 ^о to θ ₁ = 0 ^о in such a way, for a full period to the switch input polarity 11 and the input of the comparator 13 from the output of the DAC 10 (Fig. 2A - two unipolar fixation half-waves with nous). The comparator 13 (Fig. 2b), by the zero value of the function at its first input, generates a synchronization signal, according to which the trigger 14 is switched (Fig. 2c, d), the output signal of which controls the polarity switching using the polarity switch 11, at the moments when the function passes through zero (Fig. 2e). Managed low-pass filter 12 is controlled by the second shaper 7. The first shaper 4 generates a pulse whose duration is equal to the sum of the signal delays on the reverse counter 6, buffer amplifier 8 and constant memory unit 9, to ensure synchronized operation of the controlled low-pass filter 12 with a change in the code at the input of the DAC 10. Second the driver 7 on the trailing edge of the pulse coming from the first driver 4, generates a pulse whose duration is equal to the duration of the transition process occurring in the DAC 10. Thus, controlled by the low-pass filter 12, unitary enterprise The second driver 7, which works simultaneously with changing the code at the output of the DAC 10, eliminates undesirable transients and introduces minimal distortion into the output signal.

 Thus, the reliability of uptime is increased due to a decrease in the number of elements and a decrease in the number of functional connections. (56) 1. USSR author's certificate N 1543544, cl. H 03 L 7/16, 1990.

 2. Copyright certificate of the USSR N 1596427, cl. H 03, 19/00, 1988.

Claims (1)

 DIGITAL SYNTHESIS OF SINUSOIDAL SIGNALS, containing serially connected variable-frequency generator, switch, counter-control unit, reversible counter, buffer amplifier, read-only memory block, digital-to-analog converter, and digital-to-frequency converter, frequency, the output of which is connected to the other input of the switch, the first and second formers of control signals, including the clock input and output of the loan of the reversible counter with respectively, with the output of the switch and the other input of the control unit of the counting direction, the input of the second driver of the control signals is connected to the output of the switch, the input of the control of which is connected to the output of the first driver of the control signals, the output of the second the comparator is connected to the output of the digital-to-analog converter, the direct output of the D-trigger is connected to the control input of the polarity switch, the second input ompapatopa connected to the common bus and an output connected to kompapatopa C-input of D-tpiggepa, characterized in that the D-input of D-tpiggepa invepsnym connected to its output.