RU2079145C1 - Selective device for detection of single-phase short circuits to ground for cable lines - Google Patents

Abstract

FIELD: electric instruments. SUBSTANCE: method involves weight processing of high harmonics of capacitance current using characteristics of cable lines. Weight digital filtering results in 10-15 percent improvement in probability of correct detection of single-phase short circuits. Device has zero sequence current transformer, matching circuit, spectral processing unit, amplitude detectors, indication unit, current relay, two multiplexers, analog-to-digital converter, weight adder, demultiplexer, code selection unit, gate circuit, threshold gate and cu and control unit. EFFECT: increased efficiency of detection. 3 cl, 7 dwg

Description

 The invention is intended to determine the cable in which a single-phase earth fault occurred in a branched three-phase cable network with isolated or compensated neutral, and can be used to monitor and diagnose the state of the cable network of large electrical substations (usually 6 10 kV), providing power to industrial facilities and housing estates.

A device is known for overcurrent protection of a zero sequence with a current relay connected at the output of a zero sequence current transformer (TTNP) (1). However, such protection can be performed provided that the total value of the capacitive currents of the fundamental frequency of 50 Hz of all elements of a given network (ΣI _i ) is approximately 10 times higher than the largest value of the capacitive current of one element (I _i ). Thus, the disadvantage of the device is the inability to work with a small number of connections, as well as in the presence in the group of connections of one with a large length, and, therefore, with a large capacitive current. The known device "Search-1" uses a fixed setting for 5, 7, 11 and 13 harmonics of a frequency of 50 Hz to select faults and allows operation in the frequency band. However, it does not take into account the parameters of the cable network, which is its drawback.

 The known device "Probe" works on the principle of comparing the amplitudes and phases of the currents with only 11 harmonics, but information about other harmonics is not used, which significantly limits its capabilities.

 A common characteristic of analogues is that they impose restrictions on the parameters of the cable network and when using them it is impossible to take into account information about the analyzed network.

 The closest is the device USZ-ZM, containing series-connected TTNP, a spectral processing unit, an equilibrium harmonic adder and an indicator device (2). The USZ-ZM device uses information on the level of several higher harmonics in order to increase the selectivity of single-phase earth faults in cable lines. However, the equilibrium summation of the higher harmonics does not take into account the features of the cable line (its length, load power and other parameters of the cable line), which reduces the efficiency of the selectivity of the prototype.

 The aim of the invention is to increase the efficiency of the selective determination of single-phase earth faults in cable lines.

 This goal is achieved by the fact that in a selective device for determining a single-phase earth fault, which includes N measuring channels, each of which contains a series-connected current transformer of zero sequence (TTNP) and a matching stage, series-connected block of spectral processing and M amplitude detectors, and also an indicator unit and a current relay. The first multiplexer, a second multiplexer connected in series, an analog-to-digital converter (ADC), a weight adder, a demultiplexer, a code selection unit and a key circuit, as well as a threshold element and a control unit, are introduced.

 The proposed device uses weighting of the spectral components of higher harmonics, taking into account the features of the cable line parameters, as well as additional logic processing using the output signal of a current relay driven by the current induced in the second winding of the zero sequence current transformer that controls the key circuit through the threshold element.

 To analyze cable lines for determining a single-phase earth fault, the first and second multiplexers, an ADC, a weight adder, a demultiplexer, a maximum selection circuit, a key circuit, a threshold element, and a control unit are introduced.

 In FIG. 1 is a functional diagram of the device; figure 2 is a structural diagram of a block selection code; figure 3 is the same, a digital weight adder; in FIG. 4 the same maximum selection block; figure 5 an example of a possible implementation of the block selection of the maximum of two binary numbers; Fig.6 functional diagram of the control unit; Fig.7 timing diagrams of the operation of the device.

 A selective device for determining a single-phase earth fault contains N measuring channels, each of which includes a series-connected TTNP1 and a matching stage 2, a series-connected spectral processing unit 3 and amplitude detectors 4, as well as an indicator unit 5 and a current relay 6, each output of the spectral unit processing connected to the corresponding inputs of the amplitude detector 4, and the inputs of the relay 6 of the current and the matching stage 2 are combined.

 The device also contains a first multiplexer 7 and a second multiplexer 8, ADC 9, a weight digital adder 10, a demultiplexer 11, a code selection unit 12 and a key circuit 13, and a threshold element 14 and a control unit 15 connected in series.

 The device operates as follows. When a single-phase short circuit occurs in an isolated neutral network, the capacitive components of the current to earth change, which leads to an imbalance in the zero sequence currents in the damaged line (3). In this case, a signal appears from the output of the secondary winding of TTNP 1 containing the components of the higher odd harmonics (1 3). With TTNP 1, a signal is simultaneously supplied to the inputs of the current relay 6 and the matching stage 2, from the output of which the signal through the first multiplexer 7 is fed to the spectral processing unit 3. This block represents a set of analog filters tuned to the 3rd, 5th, 7th, 11th and 13th harmonics of the main operating frequency of 50 Hz. Harmonic signals are fed to amplitude detectors 4, which highlight the effective value of each harmonic. The second multiplexer 8 sequentially connects the analog values of the amplitudes of each harmonic to the ADC input 9, where the analog harmonic level is converted into a digital code, which is recorded in the first shift register of the weighted digital adder 10.

где U_k взвешенный цифровой отсчет,
a_i весовые коэффициенты,
X_M-i цифровые коды гармоник.After all digital harmonic codes are recorded in the corresponding shift registers, block 10 calculates the weighted sum of harmonics according to the algorithm:

where U _{k is a} weighted digital sample,
a _i weights
X _Mi digital harmonics codes.

The information value U _k corresponding to each cable line is supplied through the demultiplexer 11 to the input of the code selection unit 12, in which the maximum level signal is selected and recorded in the corresponding Nth shift register. The functional purpose of block 12 is to determine the maximum code of the information signal that is input to one of the key stages. When a single-phase earth fault occurs in one of the N cable lines, higher harmonics currents flow, which are transformed into TTNP 1, which will lead to the possible operation of several current relays 6 (in the form of insufficient selectivity). The signal from the output of the current relay is fed to the input of the threshold element 14, the output of which, as a result of "tipping", forms a logical unit. The signal of the unit is fed to the input of the key circuit 13, which the equipment is “fixed” to a specific cable line. If there is a phase fault to earth in this cable line, then the logical unit will also go to the second input of one key circuit. A key circuit in the presence of information signals at its inputs about a single-phase circuit of a cable line will unambiguously give an information code to the corresponding indicator, which are also hardware-sealed behind each cable line. The indicator device will record a unique phase fault to earth in a particular cable line.

 Block 12 code selection / Fig.2/ works as follows. N shift registers 16 contain digital codes of information signals for each cable line, which are supplied under the action of a control signal to N inputs of the maximum selection circuit 17 and simultaneously to the first inputs of N comparators 18. The maximum selection circuit 17 passes the maximum number code that arrives to the second combined inputs of the comparator 18. In one of the comparators 18, the digital codes coincide and there will be a logical unit at its output, and a logical zero on the other comparators. Shear registers 16 and comparators 18 are hardware-assigned to each cable line.

Digital weight adder 10 / Fig. 3 / works as follows. The input of the first of M series-connected shift registers 19 receives digital information about the levels of higher harmonics of one of the cable lines. Under the action of the control signal, information from the shift registers 19 is transmitted to the first outputs of the multipliers 20, to the second inputs of which, under the action of the control signals, digital codes of weight coefficients a _i corresponding to this cable line are received. Weighting factors for each cable line are stored in read-only memory 21 / ROM /. The cable line code (senior digits of the address) and the code of the weight coefficient number (lower digits of the address) are received at the address inputs of the ROM. In accordance with the specified address control unit 15, a digital code is selected from the ROM corresponding to the specified weight coefficient number for the analyzed cable line. The weights a _i in the binary number system are programmed taking into account the features of the cable line. After multiplying the digital codes of the harmonic levels X _Mi by the corresponding weight coefficient a _{i, the} products arrive at the inputs M of the input adder 22. At the moment the control signal arrives at the adder, the resulting sum (digital code) is sent to the demultiplexer for further processing.

The maximum selection block 17 (Fig. 4) contains M2 circuits 23 for selecting the maximum number from two binary numbers X ₁ and X ₂ . An example of a possible implementation of the scheme for selecting the maximum of two binary numbers is shown in FIG. 5. It contains a digital comparator 24, the inputs of which are two binary numbers X ₁ , X ₂ . Depending on the ratio at the output of the comparator, a logical unit is formed at one of the outputs. The three states X ₁ > X ₂ , X ₁ = X ₂ and X ₂ > X ₁ correspond to the active outputs on one of the three outputs of the digital comparator, the first two outputs of which go to the OR 25 circuit. From the output of the OR circuit, the signal (corresponding to the state X ₁ > X ₂ ) enters the first key circuit 26, from the output of which the digital code of the number X ₂ enters the input of the second association circuit 27. The combining circuit combines the outputs of the first and second key circuits 26, 28 and represents groups of two input OR circuits, the number of which is equal to the number of bits of the combined codes. In some cases, combining the outputs of the first and second key circuits can be performed by the installation method. The digital signal from the third output of the comparator 24 under the condition X ₂ > X _{2 is} fed to the first input of the second key circuit 28, the second input of which receives the code number X ₂ . If the number X ₂ > X ₁ , then the second key circuit 28 is triggered and the code of the number X ₂ through the combining circuit 27 is supplied for comparison to the next stage of comparison to a similar maximum selection circuit 23. Thus, in FIG. 4 and shows one of the options for implementing the scheme for choosing the maximum of numbers on the elements of digital computer technology.

The control unit (Fig. 6) contains a serially connected master clock generator 29, a first frequency divider 30 and a counter 31 of the upper bits of the address (arriving at the ROM 21 of the weight adder 10 /, serially connected to the first delay element 32 and the counter 33 of the address (arriving at the demultiplexer 11), the second delay element 34 and the second frequency divider 35 connected in series, as well as the counter 36 of the least significant bits of the address (received by the ROM 21 of the weight adder 10), the first shaper 37, the second shaper 38 and the third ph ripper 39. The frequency of the master oscillator 29 is selected maximum based on the upper frequency of the analyzed signal spectrum (f _t 2 • f _max 1.3 kHz in accordance with the theorem of V. A. Kotelnikov). To convert the analog signal to a digital code, the ADC 9, whose conversion frequency is f _t . A signal with a frequency f _t comes from the third output 3 of the control unit 15. The counter 36 of the least significant bits of the address converts the frequency into an address code. Digital address codes are received from the control unit output to the corresponding inputs of the second multiplexer 8 and the digital weight adder 10. The first and second formers generate control signals for the weight adder 10 to work, the first delay element 32 and the demultiplexer address counter 33 form a demultiplexer address code delayed relative to the code line addresses. This delay is necessary to synchronize the operation of the device. Similarly, the second delay element 34 and the second frequency divider 35 form a delayed control signal circuit of the block 12 code selection. Thus, the control unit 15 provides a consistent "demand" of cable lines to detect a single-phase earth fault.

 At the simultaneous level of harmonics in a cable line with a length of 3 km and a load operating current of 100 A, the effectiveness of the proposed technical solution, evaluated by the probability of correct detection of a fault, exceeded the prototype efficiency by (10-15%) depending on the variation in the harmonic weight coefficients in comparison with simple averaging harmonics, as is done in the prototype. YY2a

Claims (3)

 1. A selective device for determining single-phase faults in cable lines, containing N measuring channels, each of which is made in the form of a series-connected zero-sequence current transformer and a matching stage, an input connected to the input of the current relay, a spectral processing unit connected to the outputs of the matching stages measuring channels, and the outputs with the inputs of the corresponding M amplitude detectors, an indicator unit, characterized in that the first multiplexer through the cat The second outputs of N matching stages are connected to the inputs of the spectral processing unit, a second multiplexer is connected in series, the corresponding inputs of which are connected to the outputs of M amplitude detectors, an analog-to-digital converter, a weight digital adder and a demultiplexer, a code selection unit, N keys, threshold elements and a control unit the corresponding outputs of which are connected to the control inputs of the first and second multiplexers, analog-to-digital converter, weighted digital adder, demultiplex and the code selection block, while N outputs of the demultiplexer are connected to the corresponding inputs of the code selection block, N outputs of which are connected to the first (N 1) inputs of the corresponding keys, the second inputs of which are connected to the outputs of the corresponding current relays of the measuring channels through the corresponding threshold elements, outputs all keys are connected to the corresponding indicators of the indicator unit, N terminals of the secondary windings of the zero sequence current transformers are the corresponding inputs of the device.  2. The device according to claim 1, characterized in that the code selection block is made in the form of N shift registers, the first inputs of which are the corresponding inputs, and the combined second inputs are the control input of the code selection block, N comparators, the outputs of which are the corresponding outputs of the code selection block , and a circuit for selecting the maximum code, the output of which is connected to the first inputs of the corresponding comparators, and the corresponding inputs to the outputs of the corresponding shift registers and the second inputs of the comparators.  3. The device according to p. 1, characterized in that the weighted digital adder is made in the form of M shift registers, the combined first inputs of which are the input of the weighted digital adder, M multipliers, the first inputs of which are connected to the outputs of the corresponding shift registers, the adder, the inputs of which are connected with the outputs of the respective multipliers, and the output is the output of a weighted digital adder, and a read-only memory block, the outputs of which are connected to the second inputs of the respective multipliers, and the combined second inputs of the reg ters shift inputs volatile memory block (M + 1) th input of the adder are the respective control inputs of the digital adder weight.

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